Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32727
Void-Free Bonding of Si/Ti/Ni Power Integrated Circuit Chips with Direct Bonding Copper Alumina Substrates through Ag3Sn Intermetallic Interlayer

Authors: Kuan-Yu Chiu, Yin-Hsuan Chen, Tung-Han Chuang

Abstract:

Ti/Ni/Ag/Sn-metallized Si chips were bonded to Ni/Pd/Au-surface finished DBC (Direct Bonding Copper) alumina substrate through the formation of an Ag3Sn intermetallic interlayer by solid–liquid interdiffusion bonding method. The results indicated that the holes and gaps at the bonding interface could be effectively prevented. The intermetallic phases at the bonding interface between the Si/Ti/Ni/Ag/Sn wafer and the DBC substrate were identified as Ag3Sn, Ni3Sn4, and Ni3Sn2. The average bonding strength was about 19.75 MPa, and the maximum bonding strength reached 35.24 MPa.

Keywords: BGBM, Backside Grinding and Backside Metallization, SLID bonding, Solid–liquid Interdiffusion Bonding, Si/Ti/Ni/Sn, Si/Ti/Ni/Ag/Sn, intermetallic compound.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 266

References:


[1] Lee, H., Smet, V., & Tummala, R. (2019). A review of SiC power module packaging technologies: Challenges, advances, and emerging issues. IEEE Journal of Emerging and Selected Topics in Power Electronics, 8(1), 239-255.
[2] J. A. Warren et al., “Energy impacts of wide band gap semiconductors in U.S. Light-duty electric vehicle fleet,” Environ. Sci. Technol., vol. 49, no. 17, pp. 10294–10302, 2015.
[3] P. L. Dreike, D. M. Fleetwood, D. B. King, D. C. Sprauer and T. E. Zipperian, "An overview of high-temperature electronic device technologies and potential applications", IEEE Trans. Compon. Packag. Manuf. Technol. A, vol. 17, no. 4, pp. 594-609, Dec. 1994.
[4] P. G. Neudeck, R. S. Okojie and L.-Y. Chen, "High-temperature electronics-a role for wide bandgap semiconductors?", Proc. IEEE, vol. 90, no. 6, pp. 1065-1076, Jun. 2002.
[5] J. Watson and G. Castro, "A review of high-temperature electronics technology and applications", J. Mater. Sci. Mater. Electron., vol. 26, no. 12, pp. 9226-9235, 2015.
[6] Kim, N. P., & Cooley, R. F. (1987). Wafer back metallization for semiconductor packaging. Thin Solid Films, 153(1-3), 447-457.
[7] Ghosh, G. (2001). Dissolution and interfacial reactions of thin-film Ti/Ni/Ag metallizations in solder joints. Acta Materialia, 49(14), 2609-2624.
[8] J. G. Bai, J. Yin, Z. Zhang, G.-Q. Lu, and J. D. van Wyk, “High-temperature operation of SiC power devices by low-temperature sintered silver die-attachment,” IEEE Trans. Adv. Packag., vol. 30, no. 3, pp. 506–510, Aug. 2007.
[9] C. Göbl and J. Faltenbacher, “Low temperature sinter technology die attachment for power electronic applications,” in Proc. 6th Int. Conf. Integr. Power Electron. Syst. (CIPS), Mar. 2010, pp. 1–5.
[10] Munding, A., Hübner, H., Kaiser, A., Penka, S., Benkart, P., & Kohn, E. (2008). Cu/Sn solid–liquid interdiffusion bonding. In Wafer Level 3-D Ics Process Technology (pp. 1-39). Springer, Boston, MA.
[11] A. Munding, A. Kaiser, P. Benkart, E. Kohn, A. Heittmann, H. Hübner and U. Ramacher, “Scaling aspects of microjoints for 3D chip interconnects,” Solid-State Device Research Conference, 2006. pp. 262 - 265.
[12] P. Ramm, M.J. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel and H. Reichl, “Through silicon via technology - processes and reliability for wafer-level 3D system integration,” Electronic Components and Technology Conference, 2008. pp. 841 - 846.
[13] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, “Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking,” ECTC 2010, pp. 858 - 863.
[14] R. Agarwal, W. Zhang, P. Limaye and W. Ruythooren, “High Density Cu-Sn TLP Bonding for 3D Integration,” ECTC 2009, pp. 345 - 349.
[15] H.A. Mustain, W.D. Brown and S.S. Ang, “Transient Liquid Phase Die Attach for High-Temperature Silicon Carbide Power Devices,” Components and Packaging Technologies 2010, pp. 563 - 570.
[16] L. Menager, M. Soueidan, B. Allard, V. Bley and B. Schlegel, “A Lab-Scale Alternative Interconnection Solution of Semiconductor Dice Compatible with Power Modules 3-D Integration,” Power Electronics, IEEE Transactions on (Volume:25, Issue: 7), July 2010, pp. 1667 - 1670.
[17] K. Guth, D. Siepe, J. Görlich, H. Torwesten, R. Roth, F. Hille and F. Umbach, “New Assembly and Interconnects beyond Sintering Methods,” Proceedings of PCIM, pp. 232-237 (2010).