Search results for: high power amplifier

Authors: Wang Xing-hua, Zhong Shun-an, Zhang Zhuo

Abstract:

A kind of behavior model for discrete sampling and hold amplifier with charge transmission is analyzed. The transfer function and behavior features are based on the main AC responses of operation amplifier. The result used in pipelined and sigma-delta ADC shows the exact of model of sampling and hold amplifier, and the non-ideal factors are taken into account.

Keywords: SHA, response, behavior, transfer function.

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Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari

Abstract:

In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.

Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.

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Authors: Hyunwon Moon

Abstract:

It is necessary to realize new biomedical wireless communication systems which send the signals collected from various bio sensors located at human body in order to monitor our health. Also, it should seamlessly connect to the existing wireless communication systems. A 5.8 GHz ISM band low power RF front-end receiver for a biomedical wireless communication system is implemented using a 0.5 µm SiGe BiCMOS process. To achieve low power RF front-end, the current optimization technique for selecting device size is utilized. The implemented low noise amplifier (LNA) shows a power gain of 9.8 dB, a noise figure (NF) of below 1.75 dB, and an IIP3 of higher than 7.5 dBm while current consumption is only 6 mA at supply voltage of 2.5 V. Also, the performance of a down-conversion mixer is measured as a conversion gain of 11 dB and SSB NF of 10 dB.

Keywords: Biomedical, low noise amplifier, mixer, receiver, RF front-end, SiGe.

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Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

Abstract:

Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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Authors: Sanghoon Park, Kijin Kim, Kwangho Ahn

Abstract:

An active RC filters with a 880 / 1760 MHz dual bandwidth tuning ability is present for 60 GHz unlicensed band applications. A third order Butterworth low-pass filter utilizes two Cherry-Hooper amplifiers to satisfy the very high bandwidth requirements of an amplifier. The low-pass filter is fabricated in 90nm standard CMOS process. Drawing 6.7 mW from 1.2 V power supply, the low frequency gains of the filter are -2.5 and -4.1 dB, and the output third order intercept points (OIP3) are +2.2 and +1.9 dBm for the single channel and channel bonding conditions, respectively.

Keywords: Butterworth filter, active RC, 60 GHz, CMOS, dual bandwidth, Cherry-Hooper amplifier.

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Authors: V. Eramo, E. Miucci, A. Cianfrani, A. Germoni, M. Listanti

Abstract:

We evaluate the average energy consumption per bit in Optical Packet Switches equipped with BENES switching fabric realized in Semiconductor Optical Amplifier (SOA) technology. We also study the impact that the Amplifier Spontaneous Emission (ASE) noise generated by a transmission system has on the power consumption of the BENES switches due to the gain saturation of the SOAs used to realize the switching fabric. As a matter of example for 32×32 switches supporting 64 wavelengths and offered traffic equal to 0,8, the average energy consumption per bit is 2, 34 · 10-1 nJ/bit and increases if ASE noise introduced by the transmission systems is increased.

Keywords: Benes, Amplifier Spontaneous Emission Noise, EnergyConsumption, Optical Packet Switch.

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Authors: Abdulamgid.T. Bouzed, Suleiman. M. Elhamali

Abstract:

The technical realization of data transmission using glass fiber began after the development of diode laser in year 1962. The erbium doped fiber amplifiers (EDFA's) in high speed networks allow information to be transmitted over longer distances without using of signal amplification repeaters. These kinds of fibers are doped with erbium atoms which have energy levels in its atomic structure for amplifying light at 1550nm. When a carried signal wave at 1550nm enters the erbium fiber, the light stimulates the excited erbium atoms which pumped with laser beam at 980nm as additional light. The wavelength and intensity of the semiconductor lasers depend on the temperature of active zone and the injection current. The present paper shows the effect of the diode lasers temperature and injection current on the optical amplification. From the results of in- and output power one may calculate the max. optical gain by erbium doped fiber amplifier.

Keywords: Amplifier, erbium doped fiber, gain, lasers, temperature.

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Authors: S. Aisyah Azizan, M. Syafiq Azmi, Yuki Harada, Yoshinobu Maeda, Takaomi Matsutani

Abstract:

We introduced an all-optical multicasting characteristics with wavelength conversion based on a novel all-optical triode using negative feedback semiconductor optical amplifier. This study was demonstrated with a transfer speed of 10 Gb/s to a non-return zero 231-1 pseudorandom bit sequence system. This multi-wavelength converter device can simultaneously provide three channels of output signal with the support of non-inverted and inverted conversion. We studied that an all-optical multicasting and wavelength conversion accomplishing cross gain modulation is effective in a semiconductor optical amplifier which is effective to provide an inverted conversion thus negative feedback. The relationship of received power of back to back signal and output signals with wavelength 1535 nm, 1540 nm, 1545 nm, 1550 nm, and 1555 nm with bit error rate was investigated. It was reported that the output signal wavelengths were successfully converted and modulated with a power penalty of less than 8.7 dB, which the highest is 8.6 dB while the lowest is 4.4 dB. It was proved that all-optical multicasting and wavelength conversion using an optical triode with a negative feedback by three channels at the same time at a speed of 10 Gb/s is a promising device for the new wavelength conversion technology.

Keywords: Cross gain modulation, multicasting, negative feedback optical amplifier, semiconductor optical amplifier.

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Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua

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A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

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Authors: Yeon-kug Moon, Kang-Yoon Lee, Yun-Jae Won, Seung-Ok Lim

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This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of 0.19mm2.

Keywords: component ; Channel selection filters, DC offset, programmable gain amplifier, tuning circuit

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Authors: Deogratius Musiige, François Anton, Vital Yatskevich, Laulagnet Vincent, Darka Mioc, Nguyen Pierre

Abstract:

This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.

Keywords: Radio frequency, high power amplifier, baseband, LTE, power, emulation, homotopy, interval analysis, Tx power, register-transfer level.

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Authors: P. Prasad Rao, K. Lal Kishore

Abstract:

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: S. M. Abbas, M. A. Hannan, S. A. Samad, A. Hussain

Abstract:

This paper presented a modified efficient inductive powering link based on ASK modulator and proposed efficient class- E power amplifier. The design presents the external part which is located outside the body to transfer power and data to the implanted devices such as implanted Microsystems to stimulate and monitoring the nerves and muscles. The system operated with low band frequency 10MHZ according to industrial- scientific – medical (ISM) band to avoid the tissue heating. For external part, the modulation index is 11.1% and the modulation rate 7.2% with data rate 1 Mbit/s assuming Tbit = 1us. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD P Spice 16.2 software tool and for real-time simulation, the electronic workbench MULISIM 11 has been used.

Keywords: Implanted devices, ASK techniques, Class-E power amplifier, Inductive powering and low-frequency ISM band.

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Authors: Sanaz Haddadian, Rahele Hedayati

Abstract:

A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).

Keywords: Analog Integrated Circuit Design, Sample & Hold Amplifier and CMOS Technology.

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Authors: Mehmet Nefes, Selman Demirel, Hasan H. Ertok, Cenk Sen

Abstract:

A typical reliability engineering problem regarding communication satellites has been considered to determine redundancy allocation scheme of power amplifiers within payload transponder module, whose dominant function is to amplify power levels of the received signals from the Earth, through maximizing reliability against mass, power, and other technical limitations. Adding each redundant power amplifier component increases not only reliability but also hardware, testing, and launch cost of a satellite. This study investigates a multi-objective approach used in order to solve Redundancy Allocation Problem (RAP) for a communication satellite payload transponder, focusing on design cost due to redundancy and reliability factors. The main purpose is to find the optimum power amplifier redundancy configuration satisfying reliability and capacity thresholds simultaneously instead of analyzing respectively or independently. A mathematical model and calculation approach are instituted including objective function definitions, and then, the problem is solved analytically with different input parameters in MATLAB environment. Example results showed that payload capacity and failure rate of power amplifiers have remarkable effects on the solution and also processing time.

Keywords: Communication satellite payload, multi-objective optimization, redundancy allocation problem, reliability, transponder.

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Authors: Hasmayadi Abdul Majid, Rohana Musa

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This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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Authors: Somkiat Lerkvaranyu, Yoshikazu Miyanaga

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In this paper, a new technique of signal detection has been proposed for detecting the orthogonal frequency-division multiplexing (OFDM) signal in the presence of nonlinear distortion.There are several advantages of OFDM communications system.However, one of the existing problems is remain considered as the nonlinear distortion generated by high-power-amplifier at the transmitter end due to the large dynamic range of an OFDM signal. The proposed method is the maximum likelihood detection with the symbol estimation. When the training data are available, the neural network has been used to learn the characteristic of received signal and to estimate the new positions of the transmitted symbol which are provided to the maximum likelihood detector. Resulting in the system performance, the nonlinear distortions of a traveling wave tube amplifier with OFDM signal are considered in this paper.Simulation results of the bit-error-rate performance are obtained with 16-QAM OFDM systems.

Keywords: OFDM, TWTA, nonlinear distortion, detection.

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Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.

Keywords: Piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

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Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication systems. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. A major drawback of OFDM is the high Peak-to-Average Power Ratio (PAPR) of the transmit signal which can significantly impact the performance of the power amplifier. In this paper we have compared the PAPR reduction performance of Golay and Reed-Muller coded OFDM signal. From our simulation it has been found that the PAPR reduction performance of Golay coded OFDM is better than the Reed-Muller coded OFDM signal. Moreover, for the optimum PAPR reduction performance, code configuration for Golay and Reed-Muller codes has been identified.

Keywords: OFDM, PAPR, Perfect Codes, Golay Codes, Reed-Muller Codes

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

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This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: Self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier.

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Authors: Maninder Kaur Gill, Alpana Agarwal

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It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device under test, open-loop voltage gain, operational amplifier, test circuit.

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Authors: Rahul Bansal, Sudipta Majumdar

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This paper presents the closed form nonlinear expressions of bipolar junction transistor (BJT) differential amplifier (DA) using perturbation method. Circuit equations have been derived using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The perturbation method has been applied to state variables for obtaining the linear and nonlinear terms. The implementation of the proposed method is simple. The closed form nonlinear expressions provide better insights of physical systems. The derived equations can be used for signal processing applications.

Keywords: Differential amplifier, perturbation method, Taylor series.

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Authors: Bhaba Priyo Das, Neville Watson, Yonghe Liu

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In recent years Operational Transconductance Amplifier based high frequency integrated circuits, filters and systems have been widely investigated. The usefulness of OTAs over conventional OP-Amps in the design of both first order and second order active filters are well documented. This paper discusses some of the tunability issues using the Matlab/Simulink® software which are previously unreported for any commercial OTA. Using the simulation results two first order voltage controlled all pass filters with phase tuning capability are proposed.

Keywords: All pass filter, Operational Transconductance Amplifier, Simulation.

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Authors: R. Blicha

Abstract:

High Peak to Average Power Ratio (PAPR) of the transmitted signal is a serious problem in multicarrier systems (MC), such as Orthogonal Frequency Division Multiplexing (OFDM), or in Multi-Carrier Code Division Multiple Access (MC-CDMA) systems, due to large number of subcarriers. This effect is possible reduce with some PAPR reduction techniques. Spreading sequences at the presence of Saleh and Rapp models of high power amplifier (HPA) have big influence on the behavior of system. In this paper we investigate the bit-error-rate (BER) performance of MC-CDMA systems. Basically we can see from simulations that the MC-CDMA system with Iterative algorithm can be providing significantly better results than the MC-CDMA system. The results of our analyses are verified via simulation.

Keywords: MC-CDMA, Iterative algorithm, PAPR, BER, Saleh, Rapp, Spreading Sequences.

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Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

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In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: Channel simulation, electromagnetic simulation, power-aware signal integrity analysis, power integrity, PIPro.

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Authors: Pepin Magnangana Zoko Goyoro, Ibrahim James Moumouni, Sroy Abouty

Abstract:

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient method of data transmission for high speed communication systems. However, the main drawback of OFDM systems is that, it suffers from the problem of high Peak-to-Average Power Ratio (PAPR) which causes inefficient use of the High Power Amplifier and could limit transmission efficiency. OFDM consist of large number of independent subcarriers, as a result of which the amplitude of such a signal can have high peak values. In this paper, we propose an effective reduction scheme that combines DCT and SLM techniques. The scheme is composed of the DCT followed by the SLM using the Riemann matrix to obtain phase sequences for the SLM technique. The simulation results show PAPR can be greatly reduced by applying the proposed scheme. In comparison with OFDM, while OFDM had high values of PAPR –about 10.4dB our proposed method achieved about 4.7dB reduction of the PAPR with low complexities computation. This approach also avoids randomness in phase sequence selection, which makes it simpler to decode at the receiver. As an added benefit, the matrices can be generated at the receiver end to obtain the data signal and hence it is not required to transmit side information (SI).

Keywords: DCT transform, OFDM, PAPR, Riemann matrix, SLM.

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Authors: Antonis Constantinides, Christos Yiallouras

Abstract:

The coaxial transformer-coupled push-pull circuitry has been used widely in HF and VHF amplifiers for many decades without significant changes in the topology of the transformers. Basic changes over the years concerned the construction and turns ratio of the transformers as has been imposed upon the newer technologies active devices demands. The balun transmission line transformers applied in push-pull amplifiers enable input/output impedance transformation, but are mainly used to convert the balanced output into unbalanced and the input unbalanced into balanced. A simple and affordable alternative solution over the traditional coaxial transformer is the coreless planar balun. A key advantage over the traditional approach lies in the high specifications repeatability; simplifying the amplifier construction requirements as the planar balun constitutes an integrated part of the PCB copper layout. This paper presents the performance analysis of a planar LDMOS MRFE6VP5600 Push-Pull amplifier that enables robust operation in Band III, DVB-T, DVB-T2 standards but functions equally well in Band II, for DRM+ new generation transmitters.

Keywords: Amplifier, balun, complex impedance, LDMOS, planar-transformers.

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Authors: Seong-Ho Song, Ki-Seob Kim, Seon-Woo Lee, Seop-Hyeong Park

Abstract:

Based on a theoretical erbium-doped fiber amplifier (EDFA) model, we have proposed an application of disturbance observer(DOB) with proportional/integral/differential(PID) controller to EDFA for minimizing gain-transient time of wavelength -division-multiplexing (WDM) multi channels in optical amplifier in channel add/drop networks. We have dramatically reduced the gain-transient time to less than 30μsec by applying DOB with PID controller to the control of amplifier gain. The proposed DOB-based gain control algorithm for EDFA was implemented as a digital control system using TI's DSP(TMS320C28346) chip and experimental results of the system verify the excellent performance of the proposed gain control methodology.

Keywords: EDFA, Disturbance observer, gain control, WDM.

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