Search results for: RISC MicroProcessor

Authors: Ioannis P. Panagopoulos, Christos C. Pavlatos, George K. Papakonstantinou

Abstract:

Conventional approaches in the implementation of logic programming applications on embedded systems are solely of software nature. As a consequence, a compiler is needed that transforms the initial declarative logic program to its equivalent procedural one, to be programmed to the microprocessor. This approach increases the complexity of the final implementation and reduces the overall system's performance. On the contrary, presenting hardware implementations which are only capable of supporting logic programs prevents their use in applications where logic programs need to be intertwined with traditional procedural ones, for a specific application. We exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of those derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation is programmable, supports the execution of hybrid applications, increases the performance of logic derivations (experimental analysis yields an approximate 1000% increase in performance) and reduces the complexity of the final implemented code. The proposed hardware design is supported by a proposed extended C-language called C-AG.

Keywords: Attribute Grammars, Logic Programming, RISC microprocessor.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

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The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Moe Moe Htun, Khin Htar Nwe

Abstract:

In this paper, parallel interface for microprocessor trainer was implemented. A programmable parallel–port device such as the IC 8255A is initialized for simple input or output and for handshake input or output by choosing kinds of modes. The hardware connections and the programs can be used to interface microprocessor trainer and a personal computer by using IC 8255A. The assembly programs edited on PC-s editor can be downloaded to the trainer.

Keywords: Parallel I/O ports, parallel interface, trainer, two 8255 ICs.

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Authors: Mountassar Maamoun, Abdelhamid Meraghni, Abdelhalim Benbelkacem, Daoud Berkani

Abstract:

This paper describes an efficient hardware implementation of a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique, based on the use of software/hardware system and a reduced physical address, enlarges the interfacing capacity of the microprocessor-based systems, uses the Direct Memory Access (DMA) to increases the frequency of the new bus, and improves the speed of data exchange. While using this architecture in microprocessor-based system or in computer, the input of the hardware part of our system will be connected to the bus system, and the output, which is a new bus, will be connected to an external device. The new bus is composed of a data bus, a control bus and an address bus. A Xilinx Integrated Software Environment (ISE) 7.1i has been used for the programmable logic implementation.

Keywords: Interfacing, Software/hardware System, CPLD, programmable logic, DMA.

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Authors: Tae-Yeong Lee, Eun-Ju Yoo, Won-Yeong Choi, Young-Woo Park

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This paper presents a 24 watts SEPIC converter design and control using microprocessor. SEPIC converter has advantages of a wide input range and miniaturization caused by the low stress at elements. There is also an advantage that the input and output are isolated in MOSFET-off state. This paper presents the PID control through the SEPIC converter transfer function using a DSP and the protective circuit for fuel cell from the over-current and inverse-voltage by using the characteristic of SEPIC converter. Then it derives them through the experiments.

Keywords: DC-DC Converter, Fuel-Cell, Microprocessor Control, Military Converter, SEPIC Converter

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Authors: Abdullah A. Wardak

Abstract:

This paper describes an interfacing of C and the TMS320C6713 assembly language which is crucially important for many real-time applications. Similarly, interfacing of C with the assembly language of a conventional microprocessor such as MC68000 is presented for comparison. However, it should be noted that the way the C compiler passes arguments among various functions in the TMS320C6713-based environment is totally different from the way the C compiler passes arguments in a conventional microprocessor such as MC68000. Therefore, it is very important for a user of the TMS320C6713-based system to properly understand and follow the register conventions when interfacing C with the TMS320C6713 assembly language subroutine. It should be also noted that in some cases (examples 6-9) the endian-mode of the board needs to be taken into consideration. In this paper, one method is presented in great detail. Other methods will be presented in the future.

Keywords: Assembly language, high level language, interfacing, stack, arguments.

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Authors: Sheikh I. Azid, Bibhya Sharma

Abstract:

A low cost Short Message System (SMS) based Home security system equipped with motion, smoke, temperature, humidity and light sensors has been studied and tested. The sensors are controlled by a microprocessor PIC 18F4520 through the SMS having password protection code for the secure operation. The user is able to switch light and the appliances and get instant feedback. Also in cases of emergencies such as fire or robbery the system will send alert message to occupant and relevant civil authorities. The operation of the home security has been tested on Vodafone- Fiji network and Digicel Fiji Network for emergency and feedback responses for 25 samples. The experiment showed that it takes about 8-10s for the security system to respond in case of emergency. It takes about 18-22s for the occupant to switch and monitor lights and appliances and then get feedback depending upon the network traffic.

Keywords: Smart Home, SMS, Sensors, Microprocessor.

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Authors: Dr. N.H. Mvungi

Abstract:

The control of commutation of switched reluctance (SR) motor has nominally depended on a physical position detector. The physical rotor position sensor limits robustness and increases size and inertia of the SR drive system. The paper describes a method to overcome these limitations by using magnetization characteristics of the motor to indicate rotor and stator teeth overlap status. The method is using active current probing pulses of same magnitude that is used to simulate flux linkage in the winding being probed. A microprocessor is used for processing magnetization data to deduce rotor-stator teeth overlap status and hence rotor position. However, the back-of-core saturation and mutual coupling introduces overlap detection errors, hence that of commutation control. This paper presents the concept of the detection scheme and the effects of backof core saturation.

Keywords: Microprocessor control, rotor position, sensorless, switched reluctance.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

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As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Kang Huang, Wanting Zhou, Shiwei Yuan, Lei Li

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Since information technology develops rapidly, the security issue has become an increasingly critical for computer system. In particular, as cloud computing and the Internet of Things (IoT) continue to gain widespread adoption, computer systems need to new security threats and attacks. The Root of Trust (RoT) is the foundation for providing basic trusted computing, which is used to verify the security and trustworthiness of other components. Designing a reliable RoT and guaranteeing its own security are essential for improving the overall security and credibility of computer systems. In this paper, we discuss the implementation of self-security technology based on the RISC-V RoT at the hardware level. To effectively safeguard the security of the RoT, researches on security safeguard technology on the RoT have been studied. At first, a lightweight and secure boot framework is proposed as a secure mechanism. Secondly, two kinds of memory protection mechanism are built to against memory attacks. Moreover, hardware implementation of proposed method has been also investigated. A series of experiments and tests have been carried on to verify to effectiveness of the proposed method. The experimental results demonstrated that the proposed approach is effective in verifying the integrity of the RoT’s own boot rom, user instructions, and data, ensuring authenticity and enabling the secure boot of the RoT’s own system. Additionally, our approach provides memory protection against certain types of memory attacks, such as cache leaks and tampering, and ensures the security of root-of-trust sensitive information, including keys.

Keywords: Root of Trust, secure boot, memory protection, hardware security.

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Authors: S. Ganesh, J. Janani, G. Besliya Angel

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Photovoltaic (PV) energy is one of the most important renewable energy sources. Maximum Power Point Tracking (MPPT) techniques should be used in photovoltaic systems to maximize the PV panel output power by tracking continuously the maximum power point which depends on panel’s temperature and on irradiance conditions. Incremental conductance control method has been used as MPPT algorithm. The methodology is based on connecting a pulse width modulated dc/dc SEPIC converter, which is controlled by a microprocessor based unit. The SEPIC converter is one of the buck-boost converters which maintain the output voltage as constant irrespective of the solar isolation level. By adjusting the switching frequency of the converter the maximum power point has been achieved. The main difference between the method used in the proposed MPPT systems and other technique used in the past is that PV array output power is used to directly control the dc/dc converter thus reducing the complexity of the system. The resulting system has high efficiency, low cost and can be easily modified. The tracking capability has been verified experimentally with a 10 W solar panel under a controlled experimental setup. The SEPIC converter and their control strategies has been analyzed and simulated using Simulink/Matlab software.

Keywords: Maximum Power Point Tracking, Microprocessor, PV Module, SEPIC Converter.

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Authors: Rashmi Priyadarshini, S. R. N. Reddy, R. M. Mehra

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This paper presents one of the best applications of wireless sensor network for campus Monitoring. With the help of PIR sensor, temperature sensor and humidity sensor, effective utilization of energy resources has been implemented in one of rooms of Sharda University, Greater Noida, India. The RISC microcontroller is used here for analysis of output of sensors and providing proper control using ZigBee protocol. This wireless sensor module presents a tremendous power saving method for any campus

Keywords: PIC microcontroller, wireless sensor network, ZigBee.

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Authors: Zdenek Bohuslavek

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Development of microprocessor controlled sensor for measurement of wind speed and direction is the aim of this study. Electrical circuits and software were developed to the existing electromechanical part of the sensor TM-W2 becoming the properties of so-called smart sensor. The measured data about wind speed (sensitivity 0.01 m/s) and direction (0-360° by step 10°) are transmitted as 16-bit information. The connection between sensor and control unit is realized by radio communication (FM 433 MHz). Transition range is 220 m if used Quad type antenna. This concept provides substitution of actual cable systems by wireless ones.

Keywords: smart wind sensor, anemometer, wind speed, wireless communication

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Authors: Ünal Kızıl, Levent Genç, Sefa Aksu, Ahmet Tapınç

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The Figaro AM-1 sensor module which employs TGS 2600 model gas sensor in air quality assessment was used. The system was coupled with a microprocessor that enables sensor module to create warning message via telephone. This low cot sensor system’s performance was compared with a DiagNose II commercial electronic nose system. Both air quality sensor and electronic nose system employ metal oxide chemical gas sensors. In the study experimental setup, data acquisition methods for electronic nose system, and performance of the low cost air quality system were evaluated and explained.

Keywords: Air quality, electronic nose, environmental quality, gas sensor.

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

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Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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Authors: Adrian Bostan, Nicolae Tapus, Adriana Tapus

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The purpose of this research paper is to study and develop a system that is able to help identify problems and improve human rehabilitation after traumatic injuries. Traumatic injuries in human’s lower limbs can occur over a life time and can have serious side effects if they are not treated correctly. In this paper, we developed an intelligent cane (IntelliCane) so as to help individuals in their rehabilitation process and provide feedback to the users. The first stage of the paper involves an analysis of the existing systems on the market and what can be improved. The second stage presents the design of the system. The third part, which is still under development is the validation of the system in real world setups with people in need. This paper presents mainly stages one and two.

Keywords: IntelliCane, 3D printing, microprocessor, weight measurement, rehabilitation tool.

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Authors: M. S. Sreejith, Steffy Joy, Abhishesh Pal, Beom-Sahng Ryuh, V. R. Sanal Kumar

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In this paper, an attempt has been made for the design of a robotic library using an intelligent system. The robot works on the ARM microprocessor, motor driver circuit with 5 degrees of freedom with Wi-Fi and GPS based communication protocol. The authenticity of the library books is controlled by RFID. The proposed robotic library system is facilitated with embedded system and ARM. In this library issuance system, the previous potential readers’ authentic review reports have been taken into consideration for recommending suitable books to the deserving new users and the issuance of books or periodicals is based on the users’ decision. We have conjectured that the Wi-Fi based robotic library management system would allow fast transaction of books issuance and it also produces quality readers.

Keywords: GPS based based robotic library, library management system, robotic library, Wi-Fi library.

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Authors: Shuen-Tai Wang, Ying-Chuan Chen, Hsi-Ya Chang

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The rapid improvement of the microprocessor and network has made it possible for the PC cluster to compete with conventional supercomputers. Lots of high throughput type of applications can be satisfied by using the current desktop PCs, especially for those in PC classrooms, and leave the supercomputers for the demands from large scale high performance parallel computations. This paper presents our development on enabling an automated deployment mechanism for cluster computing to utilize the computing power of PCs such as reside in PC classroom. After well deployment, these PCs can be transformed into a pre-configured cluster computing resource immediately without touching the existing education/training environment installed on these PCs. Thus, the training activities will not be affected by this additional activity to harvest idle computing cycles. The time and manpower required to build and manage a computing platform in geographically distributed PC classrooms also can be reduced by this development.

Keywords: PC cluster, automated deployment, cluster computing, PC classroom.

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Authors: Ankit Mitra

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An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: Amplifier, DVB-T, LDMOS, MOSFETS.

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Authors: Shiuh-Jer Huang, Su-Shean Chen, Sheam-Chyun Lin

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Two-wheel inverted pendulum robot (TWIPR) is designed with two-hub DC motors for human riding and motion control evaluation. In order to measure the tilt angle and angular velocity of the inverted pendulum robot, accelerometer and gyroscope sensors are chosen. The mobile robot’s moving position and velocity were estimated based on DC motor built in hall sensors. The control kernel of this electric mobile robot is designed with embedded Arduino Nano microprocessor. A handle bar was designed to work as steering mechanism. The intelligent model-free fuzzy sliding mode control (FSMC) was employed as the main control algorithm for this mobile robot motion monitoring with different control purpose adjustment. The intelligent controllers were designed for balance control, and moving speed control purposes of this robot under different operation conditions and the control performance were evaluated based on experimental results.

Keywords: Balance control, speed control, intelligent controller and two wheel inverted pendulum.

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Authors: Wisam K. Hussam, Ali Alfeeli, Gergory J. Sheard

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Solar panels that use photovoltaic (PV) cells are popular for converting solar radiation into electricity. One of the major problems impacting the performance of PV panels is the overheating caused by excessive solar radiation and high ambient temperatures, which degrades the efficiency of the PV panels remarkably. To overcome this issue, an aluminum heat sink was used to dissipate unwanted heat from PV cells. The dimensions of the heat sink were determined considering the optimal fin spacing that fulfils hot climatic conditions. In this study, the effects of cooling on the efficiency and power output of a PV panel were studied experimentally. Two PV modules were used: one without and one with a heat sink. The experiments ran for 11 hours from 6:00 a.m. to 5:30 p.m. where temperature readings in the rear and front of both PV modules were recorded at an interval of 15 minutes using sensors and an Arduino microprocessor. Results are recorded for both panels simultaneously for analysis, temperate comparison, and for power and efficiency calculations. A maximum increase in the solar to electrical conversion efficiency of 35% and almost 55% in the power output were achieved with the use of a heat sink, while temperatures at the front and back of the panel were reduced by 9% and 11%, respectively.

Keywords: Photovoltaic cell, natural convection, heat sink, efficiency.

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Authors: Nawang Chhunid, Gagnesh Kumar

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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

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Authors: Sofien Chtourou, Mohamed Chtourou, Omar Hammami

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Embedded systems need to respect stringent real time constraints. Various hardware components included in such systems such as cache memories exhibit variability and therefore affect execution time. Indeed, a cache memory access from an embedded microprocessor might result in a cache hit where the data is available or a cache miss and the data need to be fetched with an additional delay from an external memory. It is therefore highly desirable to predict future memory accesses during execution in order to appropriately prefetch data without incurring delays. In this paper, we evaluate the potential of several artificial neural networks for the prediction of instruction memory addresses. Neural network have the potential to tackle the nonlinear behavior observed in memory accesses during program execution and their demonstrated numerous hardware implementation emphasize this choice over traditional forecasting techniques for their inclusion in embedded systems. However, embedded applications execute millions of instructions and therefore millions of addresses to be predicted. This very challenging problem of neural network based prediction of large time series is approached in this paper by evaluating various neural network architectures based on the recurrent neural network paradigm with pre-processing based on the Self Organizing Map (SOM) classification technique.

Keywords: Address, data set, memory, prediction, recurrentneural network.

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Authors: Robson C. Santos, Julio C. P. Ribeiro, Iorran M. de Castro, Luan C. F. Rodrigues, Sandro R. L. Silva, Diego M. Quesada

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The work aims to develop a robot in the form of autonomous vehicle to detect, inspection and mapping of underground pipelines through the ATmega328 Arduino platform. Hardware prototyping is very similar to C / C ++ language that facilitates its use in robotics open source, resembles PLC used in large industrial processes. The robot will traverse the surface independently of direct human action, in order to automate the process of detecting buried pipes, guided by electromagnetic induction. The induction comes from coils that send the signal to the Arduino microcontroller contained in that will make the difference in intensity and the treatment of the information, and then this determines actions to electrical components such as relays and motors, allowing the prototype to move on the surface and getting the necessary information. This change of direction is performed by a stepper motor with a servo motor. The robot was developed by electrical and electronic assemblies that allowed test your application. The assembly is made up of metal detector coils, circuit boards and microprocessor, which interconnected circuits previously developed can determine, process control and mechanical actions for a robot (autonomous car) that will make the detection and mapping of buried pipelines plates. This type of prototype can prevent and identifies possible landslides and they can prevent the buried pipelines suffer an external pressure on the walls with the possibility of oil leakage and thus pollute the environment.

Keywords: Robotic, metal detector, embedded system, pipeline.

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