Search results for: Hardware in Loop

Authors: H. A. Alzomor, B. K. Ouda, A. M. Eldeib

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Successful regional anesthesia depends upon precise location of the peripheral nerve or nerve plexus. Locating peripheral nerves is preferred to be done using nerve stimulation. In order to generate a nerve impulse by electrical means, a minimum threshold stimulus of current “rheobase” must be applied to the nerve. The technique depends on stimulating muscular twitching at a close distance to the nerve without actually touching it. Success rate of this operation depends on the accuracy of current intensity pulses used for stimulation .In this paper, we will discuss a circuit and algorithm for closed loop control for the current, theoretical analysis and test results is discussed and results is compared to previous techniques.

Keywords: Close Loop Control, Constant Current, Nerve Locator.

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Authors: Raied Salman, Nazar Younis

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In a none-super-competitive environment the concepts of closed system, management control remains to be the dominant guiding concept to management. The merits of closed loop have been the sources of most of the management literature and culture for many decades. It is a useful exercise to investigate and poke into the dynamics of the control loop phenomenon and draws some lessons to use for refining the practice of management. This paper examines the multitude of lessons abstracted from the behavior of the Input /output /feedback control loop model, which is the core of control theory. There are numerous lessons that can be learned from the insights this model would provide and how it parallels the management dynamics of the organization. It is assumed that an organization is basically a living system that interacts with the internal and external variables. A viable control loop is the one that reacts to the variation in the environment and provide or exert a corrective action. In managing organizations this is reflected in organizational structure and management control practices. This paper will report findings that were a result of examining several abstract scenarios that are exhibited in the design, operation, and dynamics of the control loop and how they are projected on the functioning of the organization. Valuable lessons are drawn in trying to find parallels and new paradigms, and how the control theory science is reflected in the design of the organizational structure and management practices. The paper is structured in a logical and perceptive format. Further research is needed to extend these findings.

Keywords: Management theory, control theory, feed back, input/output, strategy, change, information technology, informationsystems, IS, organizational environment, organizations, opensystems, closed systems.

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Authors: A. Pedram, M. R. Jamali, T. Pedram, S. M. Fakhraie, C. Lucas

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Local Linear Neuro-Fuzzy Models (LLNFM) like other neuro- fuzzy systems are adaptive networks and provide robust learning capabilities and are widely utilized in various applications such as pattern recognition, system identification, image processing and prediction. Local linear model tree (LOLIMOT) is a type of Takagi-Sugeno-Kang neuro fuzzy algorithm which has proven its efficiency compared with other neuro fuzzy networks in learning the nonlinear systems and pattern recognition. In this paper, a dedicated reconfigurable and parallel processing hardware for LOLIMOT algorithm and its applications are presented. This hardware realizes on-chip learning which gives it the capability to work as a standalone device in a system. The synthesis results on FPGA platforms show its potential to improve the speed at least 250 of times faster than software implemented algorithms.

Keywords: LOLIMOT, hardware, neurofuzzy systems, reconfigurable, parallel.

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Authors: Yuan-Jye Tseng, Yi-Shiuan Chen

Abstract:

In this paper, a new concept of closed-loop design for a product is presented. The closed-loop design model is developed by integrating forward design and reverse design. Based on this new concept, a closed-loop design model for sustainable manufacturing by integrated evaluation of forward design, reverse design, and green manufacturing using a fuzzy analytic network process is developed. In the design stage of a product, with a given product requirement and objective, there can be different ways to design the detailed components and specifications. Therefore, there can be different design cases to achieve the same product requirement and objective. Subsequently, in the design evaluation stage, it is required to analyze and evaluate the different design cases. The purpose of this research is to develop a model for evaluating the design cases by integrated evaluating the criteria in forward design, reverse design, and green manufacturing. A fuzzy analytic network process method is presented for integrated evaluation of the criteria in the three models. The comparison matrices for evaluating the criteria in the three groups are established. The total relational values among the three groups represent the total relational effects. In applications, a super matrix model is created and the total relational values can be used to evaluate the design cases for decision-making to select the final design case. An example product is demonstrated in this presentation. It shows that the model is useful for integrated evaluation of forward design, reverse design, and green manufacturing to achieve a closed-loop design for sustainable manufacturing objective.

Keywords: Design evaluation, forward design, reverse design, closed-loop design, supply chain management, closed-loop supply chain, fuzzy analytic network process.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: H. E. Michail, V. N. Thanasoulis, G. A. Panagiotakopoulos, A. P. Kakarountas, C. E. Goutis

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In this paper an efficient implementation of Ripemd- 160 hash function is presented. Hash functions are a special family of cryptographic algorithms, which is used in technological applications with requirements for security, confidentiality and validity. Applications like PKI, IPSec, DSA, MAC-s incorporate hash functions and are used widely today. The Ripemd-160 is emanated from the necessity for existence of very strong algorithms in cryptanalysis. The proposed hardware implementation can be synthesized easily for a variety of FPGA and ASIC technologies. Simulation results, using commercial tools, verified the efficiency of the implementation in terms of performance and throughput. Special care has been taken so that the proposed implementation doesn-t introduce extra design complexity; while in parallel functionality was kept to the required levels.

Keywords: Hardware implementation, hash functions, Ripemd-160, security.

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Authors: Karchung, S. Ruangsinchaiwanich

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This paper presents open-loop vector control method of induction motor with space vector pulse width modulation (SVPWM) technique. Normally, the closed loop speed control is preferred and is believed to be more accurate. However, it requires a position sensor to track the rotor position which is not desirable to use it for certain workspace applications. This paper exhibits the performance of three-phase induction motor with the simplest control algorithm without the use of a position sensor nor an estimation block to estimate rotor position for sensorless control. The motor stator currents are measured and are transformed to synchronously rotating (d-q-axis) frame by use of Clarke and Park transformation. The actual control happens in this frame where the measured currents are compared with the reference currents. The error signal is fed to a conventional PI controller, and the corrected d-q voltage is generated. The controller outputs are transformed back to three phase voltages and are fed to SVPWM block which generates PWM signal for the voltage source inverter. The open loop vector control model along with SVPWM algorithm is modeled in MATLAB/Simulink software and is experimented and validated in TMS320F28335 DSP board.

Keywords: Electric drive, induction motor, open-loop vector control, space vector pulse width modulation technique.

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Authors: Kumaresh Sarmah, Kandarpa Kumar Sarma

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Artificial Neural Network (ANN)s are best suited for prediction and optimization problems. Trained ANNs have found wide spread acceptance in several antenna design systems. Four parameters namely antenna radiation resistance, loss resistance, efficiency, and inductance can be used to design an antenna layout though there are several other parameters available. An ANN can be trained to provide the best and worst case precisions of an antenna design problem defined by these four parameters. This work describes the use of an ANN to generate the four mentioned parameters for a loop antenna for the specified frequency range. It also provides insights to the prediction of best and worst-case design problems observed in applications and thereby formulate a model for physical layout design of a loop antenna.

Keywords: MLP, ANN, parameter, prediction, optimization.

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Authors: Jae-Yeon Song, Seung-Yerl Lee, Kyu-Yeul Wang, Byung-Soo Kim, Sang-Seol Lee, Seong-Seob Shin, Jae-Young Choi, Chong Ho Lee, Jeahyun Park, Duck-Jin Chung

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In this paper, we propose disease diagnosis hardware architecture by using Hypernetworks technique. It can be used to diagnose 3 different diseases (SPECT Heart, Leukemia, Prostate cancer). Generally, the disparate diseases require specified diagnosis hardware model for each disease. Using similarities of three diseases diagnosis processor, we design diagnosis processor that can diagnose three different diseases. Our proposed architecture that is combining three processors to one processor can reduce hardware size without decrease of the accuracy.

Keywords: Diagnosis processor, Hypernetworks, Leukemia, Mask, Prostate cancer, SPECT Heart data

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Authors: Jae Hyung Noh, Hang Geun Jeong

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The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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Authors: Rizwan Asghar, Dake Liu

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A hardware efficient, multi mode, re-configurable architecture of interleaver/de-interleaver for multiple standards, like DVB, WiMAX and WLAN is presented. The interleavers consume a large part of silicon area when implemented by using conventional methods as they use memories to store permutation patterns. In addition, different types of interleavers in different standards cannot share the hardware due to different construction methodologies. The novelty of the work presented in this paper is threefold: 1) Mapping of vital types of interleavers including convolutional interleaver onto a single architecture with flexibility to change interleaver size; 2) Hardware complexity for channel interleaving in WiMAX is reduced by using 2-D realization of the interleaver functions; and 3) Silicon cost overheads reduced by avoiding the use of small memories. The proposed architecture consumes 0.18mm2 silicon area for 0.12μm process and can operate at a frequency of 140 MHz. The reduced complexity helps in minimizing the memory utilization, and at the same time provides strong support to on-the-fly computation of permutation patterns.

Keywords: Hardware interleaver implementation, WiMAX, DVB, block interleaver, convolutional interleaver, hardwaremultiplexing.

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Authors: Xu LiYun, Briand Florent, Fan GuoLiang

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The loop-layout design problem (LLDP) aims at optimizing the sequence of positioning of the machines around the cyclic production line. Traffic congestion is the usual criteria to minimize in this type of problem, i.e. the number of additional cycles spent by each part in the network until the completion of its required routing sequence of machines. This paper aims at applying several improvements mechanisms such as a positioned-based crossover operator for the Genetic Algorithm (GA) called a Two Points Crossover (TPC) and an offspring selection process. The performance of the improved GA is measured using well-known examples from literature and compared to other evolutionary algorithms. Good results show that GA can still be competitive for this type of problem against more recent evolutionary algorithms.

Keywords: Crossover, genetic algorithm, layout design problem, loop-layout, manufacturing optimization.

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Authors: O.M. Mohamed vall, M. Radhi

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This work presents a recursive identification algorithm. This algorithm relates to the identification of closed loop system with Variable Structure Controller. The approach suggested includes two stages. In the first stage a genetic algorithm is used to obtain the parameters of switching function which gives a control signal rich in commutations (i.e. a control signal whose spectral characteristics are closest possible to those of a white noise signal). The second stage consists in the identification of the system parameters by the instrumental variable method and using the optimal switching function parameters obtained with the genetic algorithm. In order to test the validity of this algorithm a simulation example is presented.

Keywords: Closed loop identification, variable structure controller, pseud-random binary sequence, genetic algorithms.

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Authors: Gorazd Karer

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When performing a diagnostic procedure or surgery in general anesthesia (GA), a proper introduction and dosing of anesthetic agents is one of the main tasks of the anesthesiologist. That being said, depth of anesthesia (DoA) also seems to be a suitable process for closed-loop control implementation. To implement such a system, one must be able to acquire the relevant signals online and in real-time, as well as stream the calculated control signal to the infusion pump. However, during a procedure, patient monitors and infusion pumps are purposely unable to connect to an external (possibly medically unapproved) device for safety reasons, thus preventing closed-loop control. This paper proposes a conceptual solution to the aforementioned problem. First, it presents some important aspects of contemporary clinical practice. Next, it introduces the closed-loop-control-system structure and the relevant information flow. Focusing on transferring the data from the patient to the computer, it presents a non-invasive image-based system for signal acquisition from a patient monitor for online depth-of-anesthesia assessment. Furthermore, it introduces a User-Datagram-Protocol-based (UDP-based) communication method that can be used for transmitting the calculated anesthetic inflow to the infusion pump. The proposed system is independent of medical-device manufacturer and is implemented in MATLAB-Simulink, which can be conveniently used for DoA control implementation. The proposed scheme has been tested in a simulated GA setting and is ready to be evaluated in an operating theatre. However, the proposed system is only a step towards a proper closed-loop control system for DoA, which could routinely be used in clinical practice.

Keywords: Closed-loop control, Depth of Anesthesia, DoA, optical signal acquisition, Patient State index, PSi, UDP communication protocol.

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Authors: V. H. Mankar, T. S. Das, S. K. Sarkar

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In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implementation because of its modularity, parallelism, high performance and reliability. The hardware realizable multiresolution spread spectrum watermarking techniques are very few in numbers in spite of their best ever resiliency against signal impairments. This is because of the computational cost and complexity associated with their different filter banks and lifting techniques. The concept of cellular automata theory in order to form a new transform domain technique i.e. Cellular Automata Transform (CAT) have been incorporated. Since CA provides spreading sequences having very low cross-correlation properties, the CA based pseudorandom sequence generator is considered in the present work. Considering the watermarking technique as a digital communication process, an error control coding (ECC) must be incorporated in the data hiding schemes. Besides the hardware implementation of entire CA based data hiding technique, the individual blocks of the algorithm using CA provide the best result than that of some other methods irrespective of the hardware and software technique. The Cellular Automata Transform, CA based PN sequence generator, and CA ECC are the requisite blocks that are developed not only to meet the reliable hardware requirements but also for the basic spread spectrum watermarking features. The proposed algorithm shows statistical invisibility and resiliency against various common signal-processing operations. This algorithmic design utilizes the existing allocated bandwidth in the data transmission channel in a more efficient manner.

Keywords: Cellular automata, watermarking, error control coding, PN sequence, VLSI.

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Authors: Hanaa M. Abdelgawad, Mona Safar, Ayman M. Wahba

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Real time image and video processing is a demand in many computer vision applications, e.g. video surveillance, traffic management and medical imaging. The processing of those video applications requires high computational power. Thus, the optimal solution is the collaboration of CPU and hardware accelerators. In this paper, a Canny edge detection hardware accelerator is proposed. Edge detection is one of the basic building blocks of video and image processing applications. It is a common block in the pre-processing phase of image and video processing pipeline. Our presented approach targets offloading the Canny edge detection algorithm from processing system (PS) to programmable logic (PL) taking the advantage of High Level Synthesis (HLS) tool flow to accelerate the implementation on Zynq platform. The resulting implementation enables up to a 100x performance improvement through hardware acceleration. The CPU utilization drops down and the frame rate jumps to 60 fps of 1080p full HD input video stream.

Keywords: High Level Synthesis, Canny edge detection, Hardware accelerators, and Computer Vision.

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Authors: Petri Solanti, Russell Klein

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Many designers are asking for an automated path from an abstract mathematical MATLAB model to a high-quality Register-Transfer Level (RTL) hardware description. Manual transformations of MATLAB or intermediate code are needed, when the design abstraction is changed. Design conversion is problematic as it is multidimensional and it requires many different design steps to translate the mathematical representation of the desired functionality to an efficient hardware description with the same behavior and configurability. Yet, a manual model conversion is not an insurmountable task. Using currently available design tools and an appropriate design methodology, converting a MATLAB model to efficient hardware is a reasonable effort. This paper describes a simple and flexible design methodology that was developed together with several design teams.

Keywords: Design methodology, high-level synthesis, MATLAB, verification.

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Authors: M.M. Namazi, S.M. Saghaiannejad, A. Rashidi

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In this paper by using the port-controlled Hamiltonian (PCH) systems theory, a full-order nonlinear controlled model is first developed. Then a nonlinear passivity-based robust adaptive control (PBRAC) of switched reluctance motor in the presence of external disturbances for the purpose of torque ripple reduction and characteristic improvement is presented. The proposed controller design is separated into the inner loop and the outer loop controller. In the inner loop, passivity-based control is employed by using energy shaping techniques to produce the proper switching function. The outer loop control is employed by robust adaptive controller to determine the appropriate Torque command. It can also overcome the inherent nonlinear characteristics of the system and make the whole system robust to uncertainties and bounded disturbances. A 4KW 8/6 SRM with experimental characteristics that takes magnetic saturation into account is modeled, simulation results show that the proposed scheme has good performance and practical application prospects.

Keywords: Switched Reluctance Motor, Port HamiltonianSystem, Passivity-Based Control, Torque Ripple Minimization

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Authors: Yuan-Jye Tseng, Yi-Shiuan Chen

Abstract:

The paper presented a sustainable design model for integrated evaluation of the design and supply chain of a product for the sustainable objectives. To design a product, there can be alternative ways to assign the detailed specifications to fulfill the same design objectives. In the design alternative cases, different material and manufacturing processes with various supply chain activities may be required for the production. Therefore, it is required to evaluate the different design cases based on the sustainable objectives. In this research, a closed-loop design model is developed by integrating the forward design model and reverse design model. From the supply chain point of view, the decisions in the forward design model are connected with the forward supply chain. The decisions in the reverse design model are connected with the reverse supply chain considering the sustainable objectives. The purpose of this research is to develop a mathematical model for analyzing the design cases by integrated evaluating the criteria in the closed-loop design and the closed-loop supply chain. The decision variables are built to represent the design cases of the forward design and reverse design. The cost parameters in a forward design include the costs of material and manufacturing processes. The cost parameters in a reverse design include the costs of recycling, disassembly, reusing, remanufacturing, and disposing. The mathematical model is formulated to minimize the total cost under the design constraints. In practical applications, the decisions of the mathematical model can be used for selecting a design case for the purpose of sustainable design of a product. An example product is demonstrated in the paper. The test result shows that the sustainable design model is useful for integrated evaluation of the design and the supply chain to achieve the sustainable objectives.

Keywords: Closed-loop design, closed-loop supply chain, design evaluation, mathematical model, supply chain management, sustainable design model.

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Authors: Yazan M. Alatrash, Han-ok Kang, Hyun-gi Yoon, Shen Zhang, Juhyeon Yoon

Abstract:

Flow coastdown phenomena are very important to secure nuclear fuel integrity during loss of off-site power accidents. In this study, primary coolant flow coastdown phenomena are investigated for the Jordan Research and Training Reactor (JRTR) using a simulation software package, Modular Modeling System (MMS). Two MMS models are built. The first one is a simple model to investigate the characteristics of the primary coolant pump only. The second one is a model for a simulation of the Primary Coolant System (PCS) loop, in which all the detailed design data of the JRTR PCS system are modeled, including the geometrical arrangement data. The same design data for a PCS pump are used for both models. Coastdown curves obtained from the two models are compared to study the PCS loop coolant inertia effect on a flow coastdown. Results showed that the loop coolant inertia effect is found to be small in the JRTR PCS loop, i.e., about one second increases in a coastdown half time required to halve the coolant flow rate. The effects of different flywheel inertia on the flow coastdown are also investigated. It is demonstrated that the coastdown half time increases with the flywheel inertia linearly. The designed coastdown half time is proved to be well above the design requirement for the fuel integrity.

Keywords: Flow Coastdown, Loop Coolant Inertia, Modeling, Research Reactor.

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Authors: Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan

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Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Keywords: Cross moments, Cumulants, FPGA, Hardware Implementation.

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Authors: A. Rakhmadi, M. S. M. Rahim, A. Bade, H. Haron, I. M. Amin

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In this study, a Loop Back Algorithm for component connected labeling for detecting objects in a digital image is presented. The approach is using loop back connected component labeling algorithm that helps the system to distinguish the object detected according to their label. Deferent than whole window scanning technique, this technique reduces the searching time for locating the object by focusing on the suspected object based on certain features defined. In this study, the approach was also implemented for a face detection system. Face detection system is becoming interesting research since there are many devices or systems that require detecting the face for certain purposes. The input can be from still image or videos, therefore the sub process of this system has to be simple, efficient and accurate to give a good result.

Keywords: Image processing, connected components labeling, face detection.

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Authors: Debabrata Das, Pankaj Dutta

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Along with forward supply chain organization needs to consider the impact of reverse logistics due to its economic advantage, social awareness and strict legislations. In this paper, we develop a system dynamics framework for a closed-loop supply chain with fuzzy demand and fuzzy collection rate by incorporating product exchange policy in forward channel and various recovery options in reverse channel. The uncertainty issues associated with acquisition and collection of used product have been quantified using possibility measures. In the simulation study, we analyze order variation at both retailer and distributor level and compare bullwhip effects of different logistics participants over time between the traditional forward supply chain and the closed-loop supply chain. Our results suggest that the integration of reverse logistics can reduce order variation and bullwhip effect of a closed-loop system. Finally, sensitivity analysis is performed to examine the impact of various parameters on recovery process and bullwhip effect.

Keywords: Bullwhip Effect, Fuzzy Possibility Measures, Reverse Supply Chain, System Dynamics.

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Authors: N. Hadjigeorgiou, A. C. Tsalikidou, E. Hristoforou, P. P. Sotiriadis

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During the last few decades, the continuously increasing demand for accurate and reliable magnetic measurements has paved the way for the development of different types of magnetic sensing systems as well as different measurement techniques. Sensor sensitivity and linearity, signal-to-noise ratio, measurement range, cross-talk between sensors in multi-sensor applications are only some of the aspects that have been examined in the past. In this paper, a fully analog closed loop system in order to optimize the performance of AMR sensors has been developed. The operation of the proposed system has been tested using a Helmholtz coil calibration setup in order to control both the amplitude and direction of magnetic field in the vicinity of the AMR sensor. Experimental testing indicated that improved linearity of sensor response, as well as low noise levels can be achieved, when the system is employed.

Keywords: AMR sensor, closed loop, memory effects, chopper, linearity improvement, sensitivity improvement, magnetic noise, electronic noise.

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Authors: Hyeon-Cheol Lee

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The adaptive power control of Code Division Multiple Access (CDMA) communications using Remote Radio Head (RRH) between multiple Unmanned Aerial Vehicles (UAVs) with a link-budget based Signal-to-Interference Ratio (SIR) estimate is applied to four inner loop power control algorithms. It is concluded that Base Station (BS) can calculate not only UAV distance using linearity between speed and Consecutive Transmit-Power-Control Ratio (CTR) of Adaptive Step-size Closed Loop Power Control (ASCLPC), Consecutive TPC Ratio Step-size Closed Loop Power Control (CS-CLPC), Fixed Step-size Power Control (FSPC), but also UAV position with Received Signal Strength Indicator (RSSI) ratio of RRHs.

Keywords: speed estimation, adaptive power control, link-budget, SIR, multi-bit quantizer, RRH

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Authors: M. L. Arias, J. D’Adamo, M. N. Novosad, P. A. Raffo, H. P. Burbridge, G. O. Artana

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Shale oils are highly paraffinic and, consequently, can create wax deposits that foul pipelines during transportation. Several factors must be considered when designing pipelines or treatment programs that prevent wax deposition: including chemical species in crude oils, flowrates, pipes diameters and temperature. This paper describes the wax deposition study carried out within the framework of YPF Tecnolgía S.A. (Y-TEC) flow assurance projects, as part of the process to achieve a better understanding on wax deposition issues. Laboratory experiments were performed on a medium size, 1 inch diameter, wax deposition loop of 15 meters long equipped with a solid detector system, online microscope to visualize crystals, temperature, and pressure sensors along the loop pipe. A baseline test was performed with diesel with no added paraffin or additive content. Tests were undertaken with different temperatures of circulating and cooling fluid at different flow conditions. Then, a solution formed with a paraffin incorporated to the diesel was considered. Tests varying flowrate and cooling rate were again run. Viscosity, density, WAT (Wax Appearance Temperature) with DSC (Differential Scanning Calorimetry), pour point and cold finger measurements were carried out to determine physical properties of the working fluids. The results obtained in the loop were analyzed through momentum balance and heat transfer models. To determine possible paraffin deposition scenarios temperature and pressure loop output signals were studied. They were compared with WAT static laboratory methods.

Keywords: Paraffin deposition, wax, oil pipelines, experimental pipe loop.

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Authors: Jiri Sebesta

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Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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Authors: Nathar Shah, Bu Kiat Seng

Abstract:

Mobile application development is different from regular application development due to the hardware resource limitations existed in the mobile platforms. In the mobile environment, the application needs to be optimized by the developer to produce optimal software with least overhead. This study discussed about performance optimization techniques that are employed in general application development, and how such techniques are performing on mobile platforms through some empirical evaluations on a mobile emulator, Nokia X3-02 and Nokia C5-03devices. The scope of the work is only confined to mobile platform based on Java Mobile edition architecture. The empirical results showed that techniques such as loop unrolling, dependency chain, and linearized getter and setter performed better by a factor of 3 to 7. Whereas declaration and initialization on the same line or separate line did not improve the performance.

Keywords: Optimization Techniques, Mobile Applications, Performance Evaluation, J2ME, Empirical Experiments

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Authors: Randeep Kaur, Jyoti Ohri

Abstract:

This paper proposes a new technique to design a fixed-structure robust loop shaping controller for the pneumatic servosystem. In this paper, a new method based on a particle swarm optimization (PSO) algorithm for tuning the weighting function parameters to design an H∞ controller is presented. The PSO algorithm is used to minimize the infinity norm of the transfer function of the nominal closed loop system to obtain the optimal parameters of the weighting functions. The optimal stability margin is used as an objective in PSO for selecting the optimal weighting parameters; it is shown that the proposed method can simplify the design procedure of H∞ control to obtain optimal robust controller for pneumatic servosystem. In addition, the order of the proposed controller is much lower than that of the conventional robust loop shaping controller, making it easy to implement in practical works. Also two-degree-of-freedom (2DOF) control design procedure is proposed to improve tracking performance in the face of noise and disturbance. Result of simulations demonstrates the advantages of the proposed controller in terms of simple structure and robustness against plant perturbations and disturbances.

Keywords: Robust control, Pneumatic Servosystem, PSO, H∞ control, 2DOF.

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