{"title":"High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform","authors":"Hanaa M. Abdelgawad, Mona Safar, Ayman M. Wahba","volume":97,"journal":"International Journal of Computer and Information Engineering","pagesStart":148,"pagesEnd":153,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/10000239","abstract":"
Real time image and video processing is a demand in
\r\nmany computer vision applications, e.g. video surveillance, traffic
\r\nmanagement and medical imaging. The processing of those video
\r\napplications requires high computational power. Thus, the optimal
\r\nsolution is the collaboration of CPU and hardware accelerators. In
\r\nthis paper, a Canny edge detection hardware accelerator is proposed.
\r\nEdge detection is one of the basic building blocks of video and image
\r\nprocessing applications. It is a common block in the pre-processing
\r\nphase of image and video processing pipeline. Our presented
\r\napproach targets offloading the Canny edge detection algorithm from
\r\nprocessing system (PS) to programmable logic (PL) taking the
\r\nadvantage of High Level Synthesis (HLS) tool flow to accelerate the
\r\nimplementation on Zynq platform. The resulting implementation
\r\nenables up to a 100x performance improvement through hardware
\r\nacceleration. The CPU utilization drops down and the frame rate
\r\njumps to 60 fps of 1080p full HD input video stream.<\/p>\r\n","references":"[1] Mohammadsadegh Sadri, Christian Weisy, Norbert Wehny, and Luca\r\nBenini: \"Energy and Performance Exploration of Accelerator\r\nCoherency Port Using Xilinx ZYNQ\", FPGAWorld \u201913, September 10-\r\n12, Copenhagen, and Stockholm, ACM\r\n[2] Dobai, R.; Sekanina, L.: \"Image filter evolution on the Xilinx Zynq\r\nPlatform,\" Adaptive Hardware and Systems (AHS), 2013 NASA\/ESA\r\nConference on , vol., no., pp.164,171, 24-27 June 2013\r\n[3] Russell, M.; Fischaber, S., \"OpenCV based road sign recognition on\r\nZynq,\" Industrial Informatics (INDIN), 2013 11th IEEE International\r\nConference on , vol., no., pp.596,601, 29-31 July 2013\r\n[4] Yan Han; Oruklu, E., \"Real-time traffic sign recognition based on Zynq\r\nFPGA and ARM SoCs,\" Electro\/Information Technology (EIT), 2014\r\nIEEE International Conference, pp.373,376, 5-7 June 2014\r\n[5] Josh Monson, Mike Wirthlin, Brad L Hutchings: \"Optimization\r\nTechniques for a High Level Synthesis Implementation of the Sobel\r\nFilter\"\r\n[6] Hong. Nguyen. T. K, Cecile. Belleudy1 and Tuan. V. Pham2: \"Power\r\nEvaluation of Sobel Filter on Xilinx Platform\".\r\n[7] Swapnil G. Kavitkar,Prashant L. Paikrao: \"FPGA based Image Feature\r\nExtraction Using Xilinx System Generator\", (IJCSIT) International\r\nJournal of Computer Science and Information Technologies,2014\r\n[8] Monson, J.; Wirthlin, M.; Hutchings, B.L., \"Implementing highperformance,\r\nlow-power FPGA-based optical flow accelerators in C,\"\r\nApplication-Specific Systems, Architectures and Processors (ASAP),\r\n2013 IEEE 24th International Conference, 5-7 June 2013\r\n[9] Christos Gentsos, Calliope-Louisa Sotiropoulou and Spiridon\r\nNikolaidis:\"Real- Time Canny Edge Detection Parallel Implementation\r\nfor FPGAs\"\r\n[10] Chaithra.N.M., K.V. Ramana Reddy,\u201dImplementation of Canny Edge\r\nDetection Algorithm on FPGA and displaying Image through VGA\r\nInterface\u201d, International Journal of Engineering and Advanced\r\nTechnology (IJEAT), ISSN: 2249 8958, Volume-2, Issue-6, August\r\n2013\r\n[11] Fernando Martinez Vallina, Christian Kohn, and Pallav Joshi, \u201dZynq All\r\nProgrammable SoC Sobel Filter Implementation Using the Vivado HLS\r\nTool\u201d, XAPP890 (v1.0) September 25, 2012.\r\n[12] Louise H Crockett, Ross A Elliot, Martin A Enderwitz, Robert W\r\nStewart The Zynq Book: Embedded Processing with the Arm Cortex-\r\nA9 on the Xilinx Zynq-7000 All Programmable Soc Paperback, July 14,\r\n2014\r\n[13] Kester Aernoudt, \u201dOpenCV, Zynq All Programmable SoC, and Vivado\r\nHLS\u201d,Xilinx,June, 2013\r\n[14] Xilinx,\u201dHow to Accelerate OpenCV Applications with the Zynq-7000\r\nAll Programmable SoC using Vivado HLS Video Libraries\u201d,August 28,\r\n2013\r\n[15] Xilinx: Zynq Base TRD Wiki http:\/\/www.wiki.xilinx.com\/Technical\r\n+Articles#TRD\r\n[16] UG925 (v7.0) Zynq-7000 All Programmable SoC ZC702 Base Targeted\r\nReference Design (Vivado Design Suite 2014.2) User Guide, August\r\n27,2014\r\n[17] Qian Xu, Srenivas Varadarajan, Chaitali Chakrabarti, and Lina J.\r\nKaram,\"A Distributed Canny Edge Detector: Algorithm and FPGA\r\nImplementation\", IEEE Transactions on Image Processing, Vol. 23, No.\r\n7, July 2014\r\n[18] Bernardo Reis, Paulo Borges, Luis Arthur Vasconcelos, Jo\u02dcao Marcelo\r\nTeixeira,Veronica Teichrieb, Judith Kelner,\u201d MarkerMatch: an\r\nEmbedded Augmented Reality case study\u201d, XII Symposium on Virtual\r\nand Augmented Reality, Natal, RN, Brazil - May 2010","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 97, 2015"}