Search results for: Chip Micro-Hardness

Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

Abstract:

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: Network-on-Chip, System-on-Chip, embedded systems, computer architecture.

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Authors: Jae Young Park, Soongyu Kwon, Kyu Han Kim, Hyeong Geon Lee, Jong Tae Kim

Abstract:

This paper considers the problem of finding low cost chip set for a minimum cost partitioning of a large logic circuits. Chip sets are selected from a given library. Each chip in the library has a different price, area, and I/O pin. We propose a low cost chip set selection algorithm. Inputs to the algorithm are a netlist and a chip information in the library. Output is a list of chip sets satisfied with area and maximum partitioning number and it is sorted by cost. The algorithm finds the sorted list of chip sets from minimum cost to maximum cost. We used MCNC benchmark circuits for experiments. The experimental results show that all of chip sets found satisfy the multiple partitioning constraints.

Keywords: lowest cost chip set, MCNC benchmark, multi-way partitioning.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Abstract:

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: Astro, bump cell, Calibre, flip chip, LEF, methodology, SCHEME, TCL.

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Authors: Mohammed H. Rady, Mohd Sukri Mustapa, S Shamsudin, M. A. Lajis, A. Wagiman

Abstract:

The present study is aimed at investigating microhardness and density of aluminium alloy chips when subjected to various settings of preheating temperature and preheating time. Three values of preheating temperature were taken as 450 °C, 500 °C, and 550 °C. On the other hand, three values of preheating time were chosen (1, 2, 3) hours. The influences of the process parameters (preheating temperature and time) were analyzed using Design of Experiments (DOE) approach whereby full factorial design with center point analysis was adopted. The total runs were 11 and they comprise of two factors of full factorial design with 3 center points. The responses were microhardness and density. The results showed that the density and microhardness increased with decreasing the preheating temperature. The results also found that the preheating temperature is more important to be controlled rather than the preheating time in microhardness analysis while both the preheating temperature and preheating time are important in density analysis. It can be concluded that setting temperature at 450 °C for 1 hour resulted in the optimum responses.

Keywords: AA6061, density, DOE, hot extrusion, microhardness.

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Authors: Dong Bok Lee, Min Jung Kim

Abstract:

The commercially available titanium alloy, Ti-6Al-4V, was oxynitrided in the deoxygenated nitrogen gas at high temperatures followed by cooling in oxygen-containing nitrogen in order to analyze the influence of oxynitriding parameters on the phase modification, hardness, and the microstructural evolution of the oxynitrided coating. The surface microhardness of the oxynitrided alloy increased due to the strengthening effect of the formed titanium oxynitrides, TiN_xO_y. The maximum microhardness was obtained, when TiN_xO_y had near equiatomic composition of nitrogen and oxygen. It could be attained under the optimum oxygen partial pressure and temperature-time condition.

Keywords: Oxynitriding, surface microhardness, titanium alloys, Ti-6Al-4V.

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Authors: V.Sivaraman, S. Sankaran, L. Vijayaraghavan

Abstract:

Machining through turning was carried out in a lathe to study the chip formation of Multiphase Ferrite (F-B-M) microalloyed steel. Taguchi orthogonal array was employed to perform the machining. Continuous and discontinuous chips were formed for different cutting parameters like speed, feed and depth of cut. Optical and scanning electron microscope was employed to identify the chip morphology.

Keywords: Multiphase microalloyed steel, chip formation, Taguchi technique, turning, cutting parameters

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Authors: Haiyi Zhang, Jianli Guo, Daqian Yang

Abstract:

This Classifying Bird Sounds (chip notes) project-s purpose is to reduce the unwanted noise from recorded bird sound chip notes, design a scheme to detect differences and similarities between recorded chip notes, and classify bird sound chip notes. The technologies of determining the similarities of sound waves have been used in communication, sound engineering and wireless sound applications for many years. Our research is focused on the similarity of chip notes, which are the sounds from different birds. The program we use is generated by Microsoft Cµ.

Keywords: Classify Bird Sounds, Noise Filter, High-pass, Lowpass, Band-pass, Band-stop Filter, FIR.

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Authors: Ziaddin Daie Koozekanani, Mina Zolfy Lighvan

Abstract:

One of the most challengeable issues in ESL (Electronic System Level) design is the lack of a general modeling scheme for on chip communication architecture. In this paper some of the mostly used methodologies for modeling and representation of on chip communication are investigated. Our goal is studying the existing methods to extract the requirements of a general representation scheme for communication architecture synthesis. The next step, will be introducing a modeling and representation method for being used in automatically synthesis process of on chip communication architecture.

Keywords: Communication architecture, System on Chip, Communication Modeling and Representation

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Authors: AL.AL, M. B. I. Reaz, S. M. A. Motakabber, Mohd Alauddin Mohd Ali

Abstract:

Nowadays it is a trend for electronic circuit designers to integrate all system components on a single-chip. This paper proposed the design of a single-chip proportional to absolute temperature (PTAT) sensor including a voltage reference circuit using CEDEC 0.18m CMOS Technology. It is a challenge to design asingle-chip wide range linear response temperature sensor for many applications. The channel widths between the compensation transistor and the reference transistor are critical to design the PTAT temperature sensor circuit. The designed temperature sensor shows excellent linearity between -100°C to 200° and the sensitivity is about 0.05mV/°C. The chip is designed to operate with a single voltage source of 1.6V.

Keywords: PTAT, single-chip circuit, linear temperature sensor, CMOS technology.

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Authors: E. M. Anawa, A. G. Olabi

Abstract:

The dissimilar joint between aluminum/titanium alloys (Al 6082 and Ti G2) were successfully achieved by CO2 laser welding with a single pass and without filler material using the overlap joint design. Laser welding parameters ranges combinations were experimentally determined using Taguchi approach with the objective of producing welded joint with acceptable welding profile and high quality of mechanical properties. In this study a joining of dissimilar Al 6082 / Ti G2 was resulted in three distinct regions fusion area in the weldment. These regions are studied in terms of its microstructural characteristics and microhardness which are directly affecting the welding quality. The weld metal was mainly composed of martensite alpha prime. In two different metals in the two different sides of joint HAZ, grain growth was detected. The microhardness of the joint distribution also has shown microhardness increasing in the HAZ of two base metals and a varying microhardness in fusion zone.

Keywords: Micro-hardness, Microstructure, laser welding, dissimilar jointed materials.

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Authors: I. Kurashvili, G. Darsavelidze, G. Bokuchava, A. Sichinava, I. Tabatadze

Abstract:

The impact of boron doping on the internal friction (IF) and shear modulus temperature spectra of Si_1-xGe_x(x≤0,02) monocrsytals has been investigated by reverse torsional pendulum oscillations characteristics testing. At room temperatures, microhardness and indentation modulus of the same specimens have been measured by dynamic ultra microhardness tester. It is shown that boron doping causes two kinds effect: At low boron concentration (~10¹⁵ cm^-3) significant strengthening is revealed, while at the high boron concentration (~10¹⁹ cm^-3) strengthening effect and activation characteristics of relaxation origin IF processes are reduced.

Keywords: Dislocation, internal friction, microhardness, relaxation.

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Authors: D. Czurratis, Y. Beyl, S. Zinober, R. Zengerle, F. Lärmer

Abstract:

A new concept for long-term reagent storage for Labon- a-Chip (LoC) devices is described. Here we present a polymer multilayer stack with integrated stick packs for long-term storage of several liquid reagents, which are necessary for many diagnostic applications. Stick packs are widely used in packaging industry for storing solids and liquids for long time. The storage concept fulfills two main requirements: First, a long-term storage of reagents in stick packs without significant losses and interaction with surroundings, second, on demand releasing of liquids, which is realized by pushing a membrane against the stick pack through pneumatic pressure. This concept enables long-term on-chip storage of liquid reagents at room temperature and allows an easy implementation in different LoC devices.

Keywords: Lab-on-a-Chip, long-term storage, reagent storage, stick pack.

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Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

Abstract:

High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: Integration, electrokinetic, on-chip, fluid pumping, microfluidic.

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Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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Authors: Muhammad Ali, Awais Adnan

Abstract:

Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.

Keywords: NoC, fault-tolerance, transient faults.

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Authors: Minsoo Lee, Yearn Jeong Kim, Yun-mi Kim, Sujeung Cheong, Sookyung Song

Abstract:

Bio-chips are used for experiments on genes and contain various information such as genes, samples and so on. The two-dimensional bio-chips, in which one axis represent genes and the other represent samples, are widely being used these days. Instead of experimenting with real genes which cost lots of money and much time to get the results, bio-chips are being used for biological experiments. And extracting data from the bio-chips with high accuracy and finding out the patterns or useful information from such data is very important. Bio-chip analysis systems extract data from various kinds of bio-chips and mine the data in order to get useful information. One of the commonly used methods to mine the data is classification. The algorithm that is used to classify the data can be various depending on the data types or number characteristics and so on. Considering that bio-chip data is extremely large, an algorithm that imitates the ecosystem such as the ant algorithm is suitable to use as an algorithm for classification. This paper focuses on finding the classification rules from the bio-chip data using the Ant Colony algorithm which imitates the ecosystem. The developed system takes in consideration the accuracy of the discovered rules when it applies it to the bio-chip data in order to predict the classes.

Keywords: Ant Colony System, DNA chip data, Classification.

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Authors: Sin J. Chen, Jyh J. Chen

Abstract:

This study describes a micro device integrated with multi-chamber for polymerase chain reaction (PCR) with different annealing temperatures. The device consists of the reaction polydimethylsiloxane (PDMS) chip, a cover glass chip, and is equipped with cartridge heaters, fans, and thermocouples for temperature control. In this prototype, commercial software is utilized to determine the geometric and operational parameters those are responsible for creating the denaturation, annealing, and extension temperatures within the chip. Two cartridge heaters are placed at two sides of the chip and maintained at two different temperatures to achieve a thermal gradient on the chip during the annealing step. The temperatures on the chip surface are measured via an infrared imager. Some thermocouples inserted into the reaction chambers are used to obtain the transient temperature profiles of the reaction chambers during several thermal cycles. The experimental temperatures compared to the simulated results show a similar trend. This work should be interesting to persons involved in the high-temperature based reactions and genomics or cell analysis.

Keywords: Polymerase chain reaction, thermal cycles, temperature gradient, micro-fabrication.

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Authors: Eduardo Sant'Ana da Silva, Andre Luiz Pires Guedes, Eduardo Todt

Abstract:

Independent spanning trees (ISTs) provide a number of advantages in data broadcasting. One can cite the use in fault tolerance network protocols for distributed computing and bandwidth. However, the problem of constructing multiple ISTs is considered hard for arbitrary graphs. In this paper we present an efficient algorithm to construct ISTs on hypercubes that requires minimum resources to be performed.

Keywords: Hypercube, Independent Spanning Trees, Networks On Chip, Systems On Chip.

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Authors: M. Khalid Imran, Syed Masood, Milan Brandt, Sudip Bhattacharya, Jyotirmoy Mazumder

Abstract:

In the present investigation, H13 tool steel has been deposited on copper alloy substrate using both CO2 and diode laser. A detailed parametric analysis has been carried out in order to find out optimum processing zone for coating defect free H13 tool steel on copper alloy substrate. Followed by parametric optimization, the microstructure and microhardness of the deposited clads have been evaluated. SEM micrographs revealed dendritic microstructure in both clads. However, the microhardness of CO2 laser deposited clad was much higher compared to diode laser deposited clad.

Keywords: CO2 laser, Diode laser, Direct Metal Deposition, Microstructure, Microhardness, Porosity.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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Authors: Samy E. Oraby, Ayman M. Alaskari

Abstract:

The importance of machining process in today-s industry requires the establishment of more practical approaches to clearly represent the intimate and severe contact on the tool-chipworkpiece interfaces. Mathematical models are developed using the measured force signals to relate each of the tool-chip friction components on the rake face to the operating cutting parameters in rough turning operation using multilayers coated carbide inserts. Nonlinear modeling proved to have high capability to detect the nonlinear functional variability embedded in the experimental data. While feedrate is found to be the most influential parameter on the friction coefficient and its related force components, both cutting speed and depth of cut are found to have slight influence. Greater deformed chip thickness is found to lower the value of friction coefficient as the sliding length on the tool-chip interface is reduced.

Keywords: Mathematical modeling, Cutting forces, Frictionforces, Friction coefficient and Chip ratio.

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Authors: Soroor Ghaziof, Wei Gao

Abstract:

Sol-enhanced Zn-Ni-Al2O3 nanocomposite coatings were electroplated on mild steel by our newly developed solenhanced electroplating method. In this method, transparent Al2O3 sol was added into the acidic Zn-Ni bath to produced Zn-Ni-Al2O3nanocomposite coatings. The chemical composition, microstructure and mechanical properties of the composite and alloy coatings deposited at two different agitation speed were investigated. The structure of all coatings was single γ-Ni5Zn21 phase. The composite coatings possess refined crystals with higher microhardness compared to Zn-Ni alloy coatings. The wear resistance of Zn-Ni coatings was improved significantly by incorporation of alumina nano particles into the coatings. Higher agitation speed provided more uniform coatings with smaller grain sized and slightly higher microhardness. Considering composite coatings, high agitation speeds may facilitate co-deposition of alumina in the coatings.

Keywords: Microhardness, Sol-enhanced electro plating, Wear resistance, Zn-Ni-Al2O3 composite coatings.

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Authors: Pavana Manvikar, G K Purohit

Abstract:

The functional performance of machined components, often, depends on surface topography, hardness, nature of stress and strain induced on the surface, etc. Invariably, surfaces of metallic components obtained by turning, milling, etc., consist of irregularities such as machining marks are responsible for the above. Surface finishing/coating processes used to produce improved surface quality/textures are classified as chip-removal and chip-less processes. Burnishing is chip-less cold working process carried out to improve surface finish, hardness and resistance to fatigue and corrosion; not obtainable by other surface coating and surface treatment processes. It is a very simple, but effective method which improves surface characteristics and is reported to introduce compressive stresses.

Of late, considerable attention is paid to post-machining, finishing operations, such as burnishing. During burnishing the micro-irregularities start to deform plastically, initially the crests are gradually flattened and zones of reduced deformation are formed. When all the crests are deformed, the valleys between the micro-irregularities start moving in the direction of the newly formed surface. The grain structure is then condensed, producing a smoother and harder surface with superior load-carrying and wear-resistant capabilities.

Burnishing can be performed on a lathe with a highly polished ball or roller type tool which is traversed under force over a rotating/stationary work piece. Often, several passes are used to obtain the work piece surface with the desired finish and hardness.

This paper presents the findings of an experimental investigation on the effect of ball burnishing parameters such as, burnishing speed, feed, force and number of passes; on surface roughness (Ra) and micro-hardness (Hv) of a 60/40 copper/zinc alloy, using a 2-level fractional factorial design of experiments (DoE). Mathematical models were developed to predict surface roughness and hardness generated by burnishing in terms of the above process parameters. A ball-type tool, designed and constructed from a high chrome steel material (HR_C=63 and Ra=0.012 µm), was used for burnishing of fine-turned cylindrical bars (0.68-0.78µm and 145Hv). They are given by,

 

Ra= 0.305-0.005X₁ - 0.0175X₂ + 0.0525X₄ + 0.0125X₁X₄ -0.02X₂X₄ - 0.0375X₃X₄

 

Hv=160.625 -2.37 5X₁ + 5.125X₂ + 1.875X₃ + 4.375X₄ - 1.625X₁X₄ + 4.375X₂X₄ - 2.375X₃X₄

 

High surface microhardness (175H_V) was obtained at 400rpm, 2passes, 0.05mm/rev and 15kgf., and high surface finish (0.20µm) was achieved at 30kgf, 0.1mm/rev, 112rpm and single pass. In other words, surface finish improved by 350% and microhardness improved by 21% compared to as machined conditions.

Keywords: Ball burnishing, surface roughness, micro-hardness.

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Authors: Aynur Aker, Hasan Kaya

Abstract:

In recent years, the use of the aluminum based alloys in the industry and technology are increasing. Alloying elements in aluminum have further been improving the strength and stiffness properties that provide superior compared to other metals. In this study, investigation of physical properties (microstructure, microhardness, tensile strength, electrical conductivity and thermal properties) in the Al-12.6wt.%Si-%2wt.Ni ternary alloy were investigated. Al-Si-Ni alloy was prepared in vacuum atmosphere. The samples were directionally solidified upwards with different growth rate V (8.3−165.45 μm/s) at constant temperature gradient G (7.73 K/mm). The flake spacings (λ), microhardness (HV), ultimate tensile strength (σ), electrical resistivity (ρ) and thermal properties (H, Cp, Tm) of the samples were measured. Influence of the growth rate and spacings on microhardness, ultimate tensile strength and electrical resistivity were investigated and relationships between them were obtained. According to results, λ values decrease with increasing V, but HV, σ and ρ values increase with increasing V. Variations of electrical resistivity (ρ) of solidified samples were also measured. The enthalpy of fusion (H) and specific heat (Cp) for the alloy was also determined by differential scanning calorimeter (DSC) from heating trace during the transformation from liquid to solid. The results in this work were compared with the previous similar experimental results.

Keywords: Electrical resistivity, enthalpy, microhardness, solidification, tensile stress.

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Authors: Ahmad M. Shafiee, Mehrdad Montazeri, Mahdi Nikdast

Abstract:

Every day human life experiences new equipments more automatic and with more abilities. So the need for faster processors doesn-t seem to finish. Despite new architectures and higher frequencies, a single processor is not adequate for many applications. Parallel processing and networks are previous solutions for this problem. The new solution to put a network of resources on a chip is called NOC (network on a chip). The more usual topology for NOC is mesh topology. There are several routing algorithms suitable for this topology such as XY, fully adaptive, etc. In this paper we have suggested a new algorithm named Intermittent X, Y (IX/Y). We have developed the new algorithm in simulation environment to compare delay and power consumption with elders' algorithms.

Keywords: Computer architecture, parallel computing, NOC, routing algorithm.

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Authors: Pedro Acevedo, Carlos Díaz, Mónica Vázquez, Joel Durán

Abstract:

This paper describes the design of a pulse generator based on the Programmable System-on-Chip (PSoC) module. In this module, using programmable logic is possible to implement different pulses which are required for ultrasonic applications, either in a single channel or multiple channels. This module can operate with programmable frequencies from 3-74 MHz; its programming may be versatile covering a wide range of ultrasonic applications. It is ideal for low-power ultrasonic applications where PZT or PVDF transducers are used.

Keywords: pulse generator, PVDF, Programmable System-on-Chip (PSoC), ultrasonic transducer

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Authors: G. H. Senussi

Abstract:

The present work is concerned with the effect of turning process parameters (cutting speed, feed rate, and depth of cut) and distance from the center of work piece as input variables on the chip micro-hardness as response or output. Three experiments were conducted; they were used to investigate the chip micro-hardness behavior at diameter of work piece for 30[mm], 40[mm], and 50[mm]. Response surface methodology (R.S.M) is used to determine and present the cause and effect of the relationship between true mean response and input control variables influencing the response as a two or three dimensional hyper surface. R.S.M has been used for designing a three factor with five level central composite rotatable factors design in order to construct statistical models capable of accurate prediction of responses. The results obtained showed that the application of R.S.M can predict the effect of machining parameters on chip micro-hardness. The five level factorial designs can be employed easily for developing statistical models to predict chip micro-hardness by controllable machining parameters. Results obtained showed that the combined effect of cutting speed at it?s lower level, feed rate and depth of cut at their higher values, and larger work piece diameter can result increasing chi micro-hardness.

Keywords: Machining Parameters, Chip Micro-Hardness, CNCMachining, 304-Austenic Stainless Steel.

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Authors: Suleiman M. Elhamali, K. M. Etmimi, A. Usha

Abstract:

The paper presents the results of microhardness and microstructure of low carbon steel surface melted using carbon dioxide laser with a wavelength of 10.6μm and a maximum output power of 2000W. The processing parameters such as the laser power, and the scanning rate were investigated in this study. After surface melting two distinct regions formed corresponding to the melted zone MZ, and the heat affected zone HAZ. The laser melted region displayed a cellular fine structures while the HAZ displayed martensite or bainite structure. At different processing parameters, the original microstructure of this steel (Ferrite+Pearlite) has been transformed to new phases of martensitic and bainitic structures. The fine structure and the high microhardness are evidence of the high cooling rates which follow the laser melting. The melting pool and the transformed microstructure in the laser surface melted region of carbon steel showed clear dependence on laser power and scanning rate.

Keywords: Carbon steel, laser surface melting, microstructure, microhardness.

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Authors: S. Mahdavi, S. R. Allahkaram

Abstract:

Electrodeposition is a simple and economic technique for precision coating of different shaped substrates with pure metal, alloy or composite films. Dc electrodeposition was used to produce Cr, Co-Cr and Co-Cr/TiO2 nano-composite coatings from Cr(III) based electrolytes onto 316L SS substrates. The effects of TiO2 nanoparticles concentration on co-deposition of these particles along with Cr content and microhardness of the coatings were investigated. Morphology of the Cr, Co-Cr and Co-Cr/TiO2 coatings besides their tribological behavior were studied. The results showed that increment of TiO2 nanoparticles concentration from 0 to 30 g L-1 in the bath increased their co-deposition and Cr content of the coatings from 0 to 3.5 wt.% and from 23.7 to 31.2 wt.%, respectively. Microhardness of Cr coating was about 920 Hv which was higher than Co-Cr and even Co-Cr/TiO2 films. Microhardness of Co-Cr and Co-Cr/TiO2 coatings were improved by increasing their Cr and TiO2 content. All the coatings had nodular morphology and contained microcracks. Nodules sizes and the number of microcracks in the alloy and composite coatings were lower than the Cr film. Wear results revealed that the Co-Cr/TiO2 coating had the lowest wear loss between all the samples, while the Cr film had the worst wear resistance.

Keywords: Co-Cr alloy, electrodeposition, nano-composite, tribological behavior, trivalent chromium.

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