Search results for: circuit analysis.
9068 An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads
Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza
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This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.Keywords: Divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 21299067 Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder
Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar
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The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.
Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 14429066 Effective Design Parameters on the End Effect in Single-Sided Linear Induction Motors
Authors: A. Zare Bazghaleh, M. R. Naghashan, H. Mahmoudimanesh, M. R. Meshkatoddini
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Linear induction motors are used in various industries but they have some specific phenomena which are the causes for some problems. The most important phenomenon is called end effect. End effect decreases efficiency, power factor and output force and unbalances the phase currents. This phenomenon is more important in medium and high speeds machines. In this paper a factor, EEF , is obtained by an accurate equivalent circuit model, to determine the end effect intensity. In this way, all of effective design parameters on end effect is described. Accuracy of this equivalent circuit model is evaluated by two dimensional finite-element analysis using ANSYS. The results show the accuracy of the equivalent circuit model.Keywords: Linear induction motor, end effect, equivalent circuitmodel, finite-element method.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 27939065 Electrical Equivalent Analysis of Micro Cantilever Beams for Sensing Applications
Authors: B. G. Sheeparamatti, J. S. Kadadevarmath
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Microcantilevers are the basic MEMS devices, which can be used as sensors, actuators and electronics can be easily built into them. The detection principle of microcantilever sensors is based on the measurement of change in cantilever deflection or change in its resonance frequency. The objective of this work is to explore the analogies between mechanical and electrical equivalent of microcantilever beams. Normally scientists and engineers working in MEMS use expensive software like CoventorWare, IntelliSuite, ANSYS/Multiphysics etc. This paper indicates the need of developing electrical equivalent of the MEMS structure and with that, one can have a better insight on important parameters, and their interrelation of the MEMS structure. In this work, considering the mechanical model of microcantilever, equivalent electrical circuit is drawn and using force-voltage analogy, it is analyzed with circuit simulation software. By doing so, one can gain access to powerful set of intellectual tools that have been developed for understanding electrical circuits Later the analysis is performed using ANSYS/Multiphysics - software based on finite element method (FEM). It is observed that both mechanical and electrical domain results for a rectangular microcantlevers are in agreement with each other.Keywords: Electrical equivalent circuit analogy, FEM analysis, micro cantilevers, micro sensors.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24599064 Design of 900 MHz High Gain SiGe Power Amplifier with Linearity Improved Bias Circuit
Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang
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A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.
Keywords: High gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra Series.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 9939063 Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations
Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze
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The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15529062 Transient Voltage Distribution on the Single Phase Transmission Line under Short Circuit Fault Effect
Authors: A. Kojah, A. Nacaroğlu
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Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.
Keywords: Energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 11699061 Analysis of Partially Shaded PV Modules Using Piecewise Linear Parallel Branches Model
Authors: Yaw-Juen Wang, Po-Chun Hsu
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This paper presents an equivalent circuit model based on piecewise linear parallel branches (PLPB) to study solar cell modules which are partially shaded. The PLPB model can easily be used in circuit simulation software such as the ElectroMagnetic Transients Program (EMTP). This PLPB model allows the user to simulate several different configurations of solar cells, the influence of partial shadowing on a single or multiple cells, the influence of the number of solar cells protected by a bypass diode and the effect of the cell connection configuration on partial shadowing.
Keywords: Cell Connection Configurations, EMTP, Equivalent Circuit, Partial Shading, Photovoltaic Module
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 29359060 Bridgeless Boost Power Factor Correction Rectifier with Hold-Up Time Extension Circuit
Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao
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A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15179059 A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic
Authors: Yukinari Minagi , Akinori Kanasugi
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This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15189058 Time-Domain Analysis of Pulse Parameters Effects on Crosstalk (In High Speed Circuits)
Authors: L. Tani, N. El Ouzzani
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Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.Keywords: Multiconductor transmission line, Crosstalk, Finite difference time domain (FDTD), printed-circuit board (PCB), Rise time, Statistical analysis.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 17749057 Real Time Force Sensing Mat for Human Gait Analysis
Authors: Darwin Gouwanda, S. M. N. Arosha Senanayake, M. M. Danushka Ranjana Marasinghe, Mervin Chandrapal, Jeya Mithra Kumar, Tung Mun Hon, Yulius
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This paper presents a real time force sensing instrument that is designed for human gait analysis purposes. This instrument mainly consists of three main elements: the force sensing mat, signal conditioning and switching circuit and data acquisition device. In order to control and to process the incoming signals from the force sensing mat, Force-Logger and Force-Reloader program are developed using Labview 8.0. This paper describes the architecture of the force sensing mat, signal conditioning and switching circuit and the real time streaming of the incoming data from the force sensing mat.Keywords: Force platform, Force sensing resistor, human gait analysis
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24829056 Design and Simulation of Low Noise Amplifier Circuit for 5 GHz to 6 GHz
Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari
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In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 50819055 A Single-chip Proportional to Absolute Temperature Sensor Using CMOS Technology
Authors: AL.AL, M. B. I. Reaz, S. M. A. Motakabber, Mohd Alauddin Mohd Ali
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Nowadays it is a trend for electronic circuit designers to integrate all system components on a single-chip. This paper proposed the design of a single-chip proportional to absolute temperature (PTAT) sensor including a voltage reference circuit using CEDEC 0.18m CMOS Technology. It is a challenge to design asingle-chip wide range linear response temperature sensor for many applications. The channel widths between the compensation transistor and the reference transistor are critical to design the PTAT temperature sensor circuit. The designed temperature sensor shows excellent linearity between -100°C to 200° and the sensitivity is about 0.05mV/°C. The chip is designed to operate with a single voltage source of 1.6V.Keywords: PTAT, single-chip circuit, linear temperature sensor, CMOS technology.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 34329054 Analysis and Performance Evaluation of Noise-Reduction Transformer
Authors: Toshiaki Yanada, Kazumi Ishikawa
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The present paper deals with the analysis and development of noise-reduction transformer that has a filter function for conductive noise transmission. Two types of prototype noise-reduction transformers with two different output voltages are proposed. To determine an optimum design for the noise-reduction transformer, noise attenuation characteristics are discussed based on the experiments and the equivalent circuit analysis. The analysis gives a relation between the circuit parameters and the noise attenuation. High performance step-down noise-reduction transformer for direct power supply to electronics equipment is developed. The input voltage of the transformer is 100 V and the output voltage is 5 V. Frequency characteristics of noise attenuation are discussed, and prevention of pulse noise transmission is demonstrated. Normal mode noise attenuation of this transformer is –80 dB, and common mode exceeds –90 dB. The step-down noise-reduction transformer eliminates pulse noise efficiently.
Keywords: conductive noise, EMC, EMI, noise attenuation, transformer.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 19739053 Design, Analysis and Modeling of Dual Band Microstrip Loop Antenna Using Defective Ground Plane
Authors: R. Bansal, A. Jain, M. Kumar, R. S. Meena
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Present wireless communication demands compact and intelligent devices with multitasking capabilities at affordable cost. The focus in the presented paper is on a dual band antenna for wireless communication with the capability of operating at two frequency bands with same structure. Two resonance frequencies are observed with the second operation band at 4.2GHz approximately three times the first resonance frequency at 1.5GHz. Structure is simple loop of microstrip line with characteristic impedance 50 ohms. The proposed antenna is designed using defective ground structure (DGS) and shows the nearly one third reductions in size as compared to without DGS. This antenna was simulated on electromagnetic (EM) simulation software and fabricated using microwave integrated circuit technique on RT-Duroid dielectric substrate (εr= 2.22) of thickness (H=15 mils). The designed antenna was tested on automatic network analyzer and shows the good agreement with simulated results. The proposed structure is modeled into an equivalent electrical circuit and simulated on circuit simulator. Subsequently, theoretical analysis was carried out and simulated. The simulated, measured, equivalent circuit response, and theoretical results shows good resemblance. The bands of operation draw many potential applications in today’s wireless communication.
Keywords: Defective Ground plane, Dual band, Loop Antenna, Microstrip antenna, Resonance frequency.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 37709052 Numerical Simulation of a Pressure Regulated Valve to Find Out the Characteristics of Passive Control Circuit
Authors: Binod Kumar Saha
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The objective of the present paper is a numerical analysis of the flow forces acting on spool surfaces of a pressure regulated valve. The transient, compressible and turbulent flow structures inside the valve are simulated using ANSYS FLUENT coupled with a special UDF. Here, valve inlet pressure is varied in a stepwise manner. For every value of inlet pressure, transient analysis leads to a quasi-static flow through the valve. Spool forces are calculated based on different pressures at inlet. From this information of spool forces, pressure characteristic of the passive control circuit has been derived.Keywords: Pressure Regulating Valve, Spool Opening, Spool Movement, Force Balance, CFD.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 38679051 The Application of Homotopy Method In Solving Electrical Circuit Design Problem
Authors: Talib Hashim Hasan
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This paper describes simple implementation of homotopy (also called continuation) algorithm for determining the proper resistance of the resistor to dissipate energy at a specified rate of an electric circuit. Homotopy algorithm can be considered as a developing of the classical methods in numerical computing such as Newton-Raphson and fixed point methods. In homoptopy methods, an embedding parameter is used to control the convergence. The method purposed in this work utilizes a special homotopy called Newton homotopy. Numerical example solved in MATLAB is given to show the effectiveness of the purposed methodKeywords: electrical circuit homotopy, methods, MATLAB, Newton homotopy
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 30339050 Phasor Analysis of a Synchronous Generator: A Bond Graph Approach
Authors: Israel Núñez-Hernández, Peter C. Breedveld, Paul B. T. Weustink, Gilberto Gonzalez-A
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This paper presents the use of phasor bond graphs to obtain the steady-state behavior of a synchronous generator. The phasor bond graph elements are built using 2D multibonds, which represent the real and imaginary part of the phasor. The dynamic bond graph model of a salient-pole synchronous generator is showed, and verified viz. a sudden short-circuit test. The reduction of the dynamic model into a phasor representation is described. The previous test is executed on the phasor bond graph model, and its steady-state values are compared with the dynamic response. Besides, the widely used power (torque)-angle curves are obtained by means of the phasor bond graph model, to test the usefulness of this model.
Keywords: Bond graphs, complex power, phasors, synchronous generator, short-circuit, open-circuit, power-angle curve.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 25539049 Comparative Study of Evolutionary Model and Clustering Methods in Circuit Partitioning Pertaining to VLSI Design
Authors: K. A. Sumitra Devi, N. P. Banashree, Annamma Abraham
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Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.
Keywords: VLSI, circuit partitioning, memetic algorithm, genetic algorithm.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 16409048 Analysis on Modeling and Simulink of DC Motor and its Driving System Used for Wheeled Mobile Robot
Authors: Wai Phyo Aung
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Wheeled Mobile Robots (WMRs) are built with their Wheels- drive machine, Motors. Depend on their desire design of WMR, Technicians made used of DC Motors for motion control. In this paper, the author would like to analyze how to choose DC motor to be balance with their applications of especially for WMR. Specification of DC Motor that can be used with desire WMR is to be determined by using MATLAB Simulink model. Therefore, this paper is mainly focus on software application of MATLAB and Control Technology. As the driving system of DC motor, a Peripheral Interface Controller (PIC) based control system is designed including the assembly software technology and H-bridge control circuit. This Driving system is used to drive two DC gear motors which are used to control the motion of WMR. In this analyzing process, the author mainly focus the drive system on driving two DC gear motors that will control with Differential Drive technique to the Wheeled Mobile Robot . For the design analysis of Motor Driving System, PIC16F84A is used and five inputs of sensors detected data are tested with five ON/OFF switches. The outputs of PIC are the commands to drive two DC gear motors, inputs of Hbridge circuit .In this paper, Control techniques of PIC microcontroller and H-bridge circuit, Mechanism assignments of WMR are combined and analyzed by mainly focusing with the “Modeling and Simulink of DC Motor using MATLAB".Keywords: Control System Design, DC Motors, DifferentialDrive, H-bridge control circuit, MATLAB Simulink model, Peripheral Interface Controller (PIC), Wheeled Mobile Robots.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 113049047 Simulation of Superconducting Nanowire Single-Photon Detector with Circuit Modeling
Authors: Seyed Ali Sedigh Zyabari, A. Zarifkar
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Single photon detectors have been fabricated NbN nano wire. These detectors are fabricated from high quality, ultra high vacuum sputtered NbN thin films on a sapphire substrate. In this work a typical schematic of the nanowire Single Photon Detector structure and then driving and measurement electronic circuit are shown. The response of superconducting nanowire single photon detectors during a photo detection event, is modeled by a special electrical circuits (two circuit). Finally, current through the wire is calculated by solving equations of models.Keywords: NbN, nanowire meander, superconducting single photon detector, kinetic inductance.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15039046 A Temperature-Insensitive Wide-Dynamic Range Positive/Negative Full-Wave Rectifier Based on Operational Trasconductance Amplifier using Commercially Available ICs
Authors: C. Chanapromma, T. Worachak, P. Silapan
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This paper presents positive and negative full-wave rectifier. The proposed structure is based on OTA using commercially available ICs (LT1228). The features of the proposed circuit are that: it can rectify and amplify voltage signal with controllable output magnitude via input bias current: the output voltage is free from temperature variation. The circuit description merely consists of 1 single ended and 3 fully differential OTAs. The performance of the proposed circuit are investigated though PSpice. They show that the proposed circuit can function as positive/negative full-wave rectifier, where the voltage input wide-dynamic range from -5V to 5V. Furthermore, the output voltage is slightly dependent on the temperature variations.Keywords: Full-wave rectifier, Positive/negative, OTA, Electronically controllable, Wide-dynamic range
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 18379045 Implementation of Second Order Current- Mode Quadrature Sinusoidal Oscillator with Current Controllability
Authors: Koson Pitaksuttayaprot, Winai Jaikla
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The realization of current-mode quadrature oscillators using current controlled current conveyor transconductance amplifiers (CCCCTAs) and grounded capacitors is presented. The proposed oscillators can provide 2 sinusoidal output currents with 90º phase difference. It is enabled non-interactive dual-current control for both the condition of oscillation and the frequency of oscillation. High output impedances of the configurations enable the circuit to be cascaded without additional current buffers. The use of only grounded capacitors is ideal for integration. The circuit performances are depicted through PSpice simulations, they show good agreement to theoretical anticipation.Keywords: Current-mode, Oscillator, Integrated circuit, CCCCTA.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 19079044 The Effects of a Circuit Training Program on Muscle Strength, Agility, Anaerobic Performance and Cardiovascular Endurance
Authors: Wirat Sonchan, Pratoom Moungmee, Anek Sootmongkol
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This study aimed to examine the effects of a circuit training program on muscle strength, agility, anaerobic performance and cardiovascular endurance. The study involved 24 freshmen (age 18.87+0.68 yr.) male students of the Faculty of Sport Science, Burapha University. They sample study were randomly divided into two groups: Circuit Training group (CT; n=12) and a Control group (C; n=12). Baseline data on height, weight, muscle strength (hand grip dynamometer and leg strength dynamometer), agility (agility T-Test), and anaerobic performance (Running-based Anaerobic Sprint Test) and cardiovascular endurance (20 m Endurance Shuttle Run Test) were collected. The circuit training program included one circuit of eight stations of 30/60 seconds of work/rest interval with two cycles in Week 1-4, and 60/90 seconds of work/rest interval with three cycles in Week 5-8, performed three times per week. Data were analyzed using paired t-tests and independent sample t-test. Statistically significance level was set at 0.05. The results show that after 8 weeks of a training program, muscle strength, agility, anaerobic capacity and cardiovascular endurance increased significantly in the CT Group (p < 0.05), while significant increase was not observed in the C Group (p < 0.05). The results of this study suggest that the circuit training program improved muscle strength, agility, anaerobic capacity and cardiovascular endurance of the study subjects. This program may be used as a guideline for selecting a set of exercise to improve physical fitness.
Keywords: Cardiovascular endurance, circuit training, physical fitness, anaerobic performance.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 25199043 Third Order Current-mode Quadrature Sinusoidal Oscillator with High Output Impedances
Authors: Kritphon Phanruttanachai, Winai Jaikla
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This article presents a current-mode quadrature oscillator using differential different current conveyor (DDCC) and voltage differencing transconductance amplifier (VDTA) as active elements. The proposed circuit is realized fro m a non-inverting lossless integrator and an inverting second order low-pass filter. The oscillation condition and oscillation frequency can be electronically/orthogonally controlled via input bias currents. The circuit description is very simple, consisting of merely 1 DDCC, 1 VDTA, 1 grounded resistor and 3 grounded capacitors. Using only grounded elements, the proposed circuit is then suitable for IC architecture. The proposed oscillator has high output impedance which is easy to cascade or dive the external load without the buffer devices. The PSPICE simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.76mW at ±1.25V supply voltages.Keywords: Current-mode, oscillator, integrated circuit, DDCC, VDTA
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 24079042 Real Time Multi-Sensory Force Sensing Mat for Sports Biomechanics and Human Gait Analysis
Authors: D. Gouwanda, S. M. N. A. Senanayake
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This paper presents a real time force sensing instrument that is designed for human gait analysis purposes. It is capable of recording and monitoring ground reaction forces exerted by human foot during various activities such as walking, running and jumping in real time. In overall, force sensing mat mainly consists of three elements: the force sensing mat, signal conditioning circuit and data acquisition device. Force sensing mat is the mat that contains an array of force sensing elements. To control and process the incoming signal from the force sensing mat, Force-Logger and Force-Reloader are developed using National Instrument Labview. This paper describes the architecture of the force sensing mat, signal conditioning circuit and the real time streaming of the incoming data from the force sensing mat. Additionally, a preliminary experiment dataset is presented in this paper.Keywords: Force platform, force sensing resistor, human gait analysis.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 23189041 Elegant: An Intuitive Software Tool for Interactive Learning of Power System Analysis
Authors: Eduardo N. Velloso, Fernando M. N. Dantas, Luciano S. Barros
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A common complaint from power system analysis students lies in the overly complex tools they need to learn and use just to simulate very basic systems or just to check the answers to power system calculations. The most basic power system studies are power-flow solutions and short-circuit calculations. This paper presents a simple tool with an intuitive interface to perform both these studies and assess its performance in comparison with existent commercial solutions. With this in mind, Elegant is a pure Python software tool for learning power system analysis developed for undergraduate and graduate students. It solves the power-flow problem by iterative numerical methods and calculates bolted short-circuit fault currents by modeling the network in the domain of symmetrical components. Elegant can be used with a user-friendly Graphical User Interface (GUI) and automatically generates human-readable reports of the simulation results. The tool is exemplified using a typical Brazilian regional system with 18 buses. This study performs a comparative experiment with 1 undergraduate and 4 graduate students who attempted the same problem using both Elegant and a commercial tool. It was found that Elegant significantly reduces the time and labor involved in basic power system simulations while still providing some insights into real power system designs.
Keywords: Free- and open-source software, power-flow, power system analysis, Python, short-circuit.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4579040 A New Integer Programming Formulation for the Chinese Postman Problem with Time Dependent Travel Times
Authors: Jinghao Sun, Guozhen Tan, Guangjian Hou
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The Chinese Postman Problem (CPP) is one of the classical problems in graph theory and is applicable in a wide range of fields. With the rapid development of hybrid systems and model based testing, Chinese Postman Problem with Time Dependent Travel Times (CPPTDT) becomes more realistic than the classical problems. In the literature, we have proposed the first integer programming formulation for the CPPTDT problem, namely, circuit formulation, based on which some polyhedral results are investigated and a cutting plane algorithm is also designed. However, there exists a main drawback: the circuit formulation is only available for solving the special instances with all circuits passing through the origin. Therefore, this paper proposes a new integer programming formulation for solving all the general instances of CPPTDT. Moreover, the size of the circuit formulation is too large, which is reduced dramatically here. Thus, it is possible to design more efficient algorithm for solving the CPPTDT in the future research.Keywords: Chinese Postman Problem, Time Dependent, Integer Programming, Upper Bound Analysis.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 27419039 Symmetrical Analysis of a Six-Phase Induction Machine Under Fault Conditions
Authors: E. K.Appiah, G. M'boungui, A. A. Jimoh, J. L. Munda, A.S.O. Ogunjuyigbe
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The operational behavior of a six-phase squirrel cage induction machine with faulted stator terminals is presented in this paper. The study is carried out using the derived mathematical model of the machine in the arbitrary reference frame. Tests are conducted on a 1 kW experimental machine. Steady-state and dynamic performance are analyzed for the machine unloaded and loaded conditions. The results shows that with one of the stator phases experiencing either an open- circuit or short circuit fault the machine still produces starting torque, albeit the running performance is significantly derated.Keywords: Performance, fault conditions, six-phase induction machine.
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