Search results for: Gate delay
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 730

Search results for: Gate delay

280 Low-complexity Integer Frequency Offset Synchronization for OFDMA System

Authors: Young-Jae Kim, Young-Hwan You

Abstract:

This paper presents a integer frequency offset (IFO) estimation scheme for the 3GPP long term evolution (LTE) downlink system. Firstly, the conventional joint detection method for IFO and sector cell index (CID) information is introduced. Secondly, an IFO estimation without explicit sector CID information is proposed, which can operate jointly with the proposed IFO estimation and reduce the time delay in comparison with the conventional joint method. Also, the proposed method is computationally efficient and has almost similar performance in comparison with the conventional method over the Pedestrian and Vehicular channel models.

Keywords: LTE, OFDMA, primary synchronization signal (PSS), IFO, CID

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279 Improved Stability Criteria for Neural Networks with Two Additive Time-Varying Delays

Authors: Miaomiao Yang, Shouming Zhong

Abstract:

This paper studies the problem of stability criteria for neural networks with two additive time-varying delays.A new Lyapunov-Krasovskii function is constructed and some new delay dependent stability criterias are derived in the terms of linear matrix inequalities(LMI), zero equalities and reciprocally convex approach.The several stability criterion proposed in this paper is simpler and effective. Finally,numerical examples are provided to demonstrate the feasibility and effectiveness of our results.

Keywords: Stability, Neural networks, Linear Matrix Inequalities (LMI) , Lyapunov function, Time-varying delays

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278 Digital Encoder Based Power Frequency Deviation Measurement

Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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277 Design a Three-dimensional Pursuit Guidance Law with Feedback Linearization Method

Authors: Chien-Chun Kung, Feng-Lung Chiang, Kuei-Yi Chen

Abstract:

In this paper, we will implement three-dimensional pursuit guidance law with feedback linearization control method and study the effects of parameters. First, we introduce guidance laws and equations of motion of a missile. Pursuit guidance law is our highlight. We apply feedback linearization control method to obtain the accelerations to implement pursuit guidance law. The solution makes warhead direction follow with line-of-sight. Final, the simulation results show that the exact solution derived in this paper is correct and some factors e.g. control gain, time delay, are important to implement pursuit guidance law.

Keywords: Pursuit guidance law, feedback linearization.

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276 Capacity Optimization in Cooperative Cognitive Radio Networks

Authors: Mahdi Pirmoradian, Olayinka Adigun, Christos Politis

Abstract:

Cooperative spectrum sensing is a crucial challenge in cognitive radio networks. Cooperative sensing can increase the reliability of spectrum hole detection, optimize sensing time and reduce delay in cooperative networks. In this paper, an efficient central capacity optimization algorithm is proposed to minimize cooperative sensing time in a homogenous sensor network using OR decision rule subject to the detection and false alarm probabilities constraints. The evaluation results reveal significant improvement in the sensing time and normalized capacity of the cognitive sensors.

Keywords: Cooperative networks, normalized capacity, sensing time.

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275 FPGA Based Parallel Architecture for the Computation of Third-Order Cross Moments

Authors: Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan

Abstract:

Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Keywords: Cross moments, Cumulants, FPGA, Hardware Implementation.

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274 Attentiveness of Building Commissioning in the Malaysian Construction Industry

Authors: Kho Mei Ye, Hamzah Abdul Rahman

Abstract:

This paper provides some thoughts about the lack of attentiveness of building commissioning in the construction industry and the lack of handling in project commissioning as an integral part of the project life-cycle. Many have perceived commissioning as the problem solving process of a project, rather than the start up of the equipment, or the handing over of the project to the client. Therefore, there is a lack of proper attention in the planning of commissioning as a vital part of the project life-cycle. This review paper aims to highlight the benefits of building commissioning and to propose the lacking of knowledge gap on building commissioning. Finally, this paper hopes to propose the shift of focus on this matter in future research.

Keywords: building, commissioning, construction, delay

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273 Effect of Delay on Supply Side on Market Behavior: A System Dynamic Approach

Authors: M. Khoshab, M. J. Sedigh

Abstract:

Dynamic systems, which in mathematical point of view are those governed by differential equations, are much more difficult to study and to predict their behavior in comparison with static systems which are governed by algebraic equations. Economical systems such as market are among complicated dynamic systems. This paper tries to adopt a very simple mathematical model for market and to study effect of supply and demand function on behavior of the market while the supply side experiences a lag due to production restrictions.

Keywords: Dynamic System, Lag on Supply Demand, Market Stability, Supply Demand Model.

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272 Capacity Enhancement in Wireless Networks using Directional Antennas

Authors: Sedat Atmaca, Celal Ceken, Ismail Erturk

Abstract:

One of the biggest drawbacks of the wireless environment is the limited bandwidth. However, the users sharing this limited bandwidth have been increasing considerably. SDMA technique which entails using directional antennas allows to increase the capacity of a wireless network by separating users in the medium. In this paper, it has been presented how the capacity can be enhanced while the mean delay is reduced by using directional antennas in wireless networks employing TDMA/FDD MAC. Computer modeling and simulation of the wireless system studied are realized using OPNET Modeler. Preliminary simulation results are presented and the performance of the model using directional antennas is evaluated and compared consistently with the one using omnidirectional antennas.

Keywords: Directional Antenna, TDMA, SDMA,

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271 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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270 A Methodology for Reducing the BGP Convergence Time

Authors: Eatedal A. Alabdulkreem, Hamed S. Al-Raweshidy, Maysam F. Abbod

Abstract:

Border Gateway Protocol (BGP) is the standard routing protocol between various autonomous systems (AS) in the internet. In the event of failure, a considerable delay in the BGP convergence has been shown by empirical measurements. During the convergence time the BGP will repeatedly advertise new routes to some destination and withdraw old ones until it reach a stable state. It has been found that the KEEPALIVE message timer and the HOLD time are tow parameters affecting the convergence speed. This paper aims to find the optimum value for the KEEPALIVE timer and the HOLD time that maximally reduces the convergence time without increasing the traffic. The KEEPALIVE message timer optimal value founded by this paper is 30 second instead of 60 seconds, and the optimal value for the HOLD time is 90 seconds instead of 180 seconds.

Keywords: BGP, Convergence Time, HOLD time, Keep alive.

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269 Modeling and Prediction of Zinc Extraction Efficiency from Concentrate by Operating Condition and Using Artificial Neural Networks

Authors: S. Mousavian, D. Ashouri, F. Mousavian, V. Nikkhah Rashidabad, N. Ghazinia

Abstract:

PH, temperature and time of extraction of each stage,  agitation speed and delay time between stages effect on efficiency of  zinc extraction from concentrate. In this research, efficiency of zinc  extraction was predicted as a function of mentioned variable by  artificial neural networks (ANN). ANN with different layer was  employed and the result show that the networks with 8 neurons in  hidden layer has good agreement with experimental data.

 

Keywords: Zinc extraction, Efficiency, Neural networks, Operating condition.

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268 Comparative Study of Scheduling Algorithms for LTE Networks

Authors: Samia Dardouri, Ridha Bouallegue

Abstract:

Scheduling is the process of dynamically allocating physical resources to User Equipment (UE) based on scheduling algorithms implemented at the LTE base station. Various algorithms have been proposed by network researchers as the implementation of scheduling algorithm which represents an open issue in Long Term Evolution (LTE) standard. This paper makes an attempt to study and compare the performance of PF, MLWDF and EXP/PF scheduling algorithms. The evaluation is considered for a single cell with interference scenario for different flows such as Best effort, Video and VoIP in a pedestrian and vehicular environment using the LTE-Sim network simulator. The comparative study is conducted in terms of system throughput, fairness index, delay, packet loss ratio (PLR) and total cell spectral efficiency.

Keywords: LTE, Multimedia flows, Scheduling algorithms.

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267 A Performance Analysis of Different Scheduling Schemes in WiMAX

Authors: A. Youseef

Abstract:

IEEE 802.16 (WiMAX) aims to present high speed wireless access to cover wide range coverage. The base station (BS) and the subscriber station (SS) are the main parts of WiMAX. WiMAX uses either Point-to-Multipoint (PMP) or mesh topologies. In the PMP mode, the SSs connect to the BS to gain access to the network. However, in the mesh mode, the SSs connect to each other to gain access to the BS. The main components of QoS management in the 802.16 standard are the admission control, buffer management and packet scheduling. In this paper, we use QualNet 5.0.2 to study the performance of different scheduling schemes, such as WFQ, SCFQ, RR and SP when the numbers of SSs increase. We find that when the number of SSs increases, the average jitter and average end-to-end delay is increased and the throughput is reduced.

Keywords: WiMAX, Scheduling Scheme, QoS, QualNet.

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266 Technology Trend and Level Assessment Using Patent Data for Preliminary Feasibility Study on R and D Program

Authors: Seongmin Yim

Abstract:

The Korean government has applied preliminary feasibility study for new and huge R&D programs since 2008.The study is carried out from the viewpoints of technology, policy, and Economics. Then integrate the separate analysis and finally arrive at a definite result; whether a program is feasible or unfeasible, This paper describes the concept and method of the feasibility analysis focused on technological viability assessment for technical analysis. It consists of technology trend assessment and technology level assessment. Through the analysis, we can determine the chance of schedule delay or cost overrun occurring in the proposed plan.

Keywords: Preliminary Feasibility Study, Technological viability, Technology Trend Assessment, Technology Level Assessment

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265 Existence and Global Exponential Stability of Periodic Solutions of Cellular Neural Networks with Distributed Delays and Impulses on Time Scales

Authors: Daiming Wang

Abstract:

In this paper, by using Mawhin-s continuation theorem of coincidence degree and a method based on delay differential inequality, some sufficient conditions are obtained for the existence and global exponential stability of periodic solutions of cellular neural networks with distributed delays and impulses on time scales. The results of this paper generalized previously known results.

Keywords: Periodic solutions, global exponential stability, coincidence degree, M-matrix.

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264 A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard

Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm2 and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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263 14-Bit 1MS/s Cyclic-Pipelined ADC

Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.


Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

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262 Analyzing the Impact of DCF and PCF on WLAN Network Standards 802.11a, 802.11b and 802.11g

Authors: Amandeep Singh Dhaliwal

Abstract:

Networking solutions, particularly wireless local area networks have revolutionized the technological advancement. Wireless Local Area Networks (WLANs) have gained a lot of popularity as they provide location-independent network access between computing devices. There are a number of access methods used in Wireless Networks among which DCF and PCF are the fundamental access methods. This paper emphasizes on the impact of DCF and PCF access mechanisms on the performance of the IEEE 802.11a, 802.11b and 802.11g standards. On the basis of various parameters viz. throughput, delay, load etc performance is evaluated between these three standards using above mentioned access mechanisms. Analysis revealed a superior throughput performance with low delays for 802.11g standard as compared to 802.11 a/b standard using both DCF and PCF access methods.

Keywords: DCF, IEEE, PCF, WLAN.

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261 Sampled-Data Model Predictive Tracking Control for Mobile Robot

Authors: Wookyong Kwon, Sangmoon Lee

Abstract:

In this paper, a sampled-data model predictive tracking control method is presented for mobile robots which is modeled as constrained continuous-time linear parameter varying (LPV) systems. The presented sampled-data predictive controller is designed by linear matrix inequality approach. Based on the input delay approach, a controller design condition is derived by constructing a new Lyapunov function. Finally, a numerical example is given to demonstrate the effectiveness of the presented method.

Keywords: Model predictive control, sampled-data control, linear parameter varying systems, LPV.

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260 Trial Development the Evaluation Method of Quantification the Feeling of Preventing Visibility by Front A Pillar

Authors: T. Arakawa, H. Sato

Abstract:

There are many drivers who feel right A pillar of Japanese right-hand-drive car preventing visibility on turning right or left at intersection. On the other hand, there is a report that almost pedestrian accident is caused by the delay of finding pedestrian by drivers and this is found by drivers’ eye movement. Thus, we developed the evaluation method of quantification using drivers’ eye movement data by least squares estimation and we applied this method to commercial vehicle and evaluation the visibility. It is suggested that visibility of vehicle can be quantified and estimated by linear model obtained from experimental eye fixation data and information of vehicle dimensions.

Keywords: Eye fixation, modeling, obstacle feeling, right A pillar.

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259 Tuning a Fractional Order PID Controller with Lead Compensator in Frequency Domain

Authors: Tahmine. V. Moghaddam, N. Bigdeli, K. Afshar

Abstract:

To achieve the desired specifications of gain and phase margins for plants with time-delay that stabilized with FO-PID controller a lead compensator is designed. At first the range of controlled system stability based on stability boundary criteria is determined. Using stability boundary locus method in frequency domain the fractional order controller parameters are tuned and then with drawing bode diagram in frequency domain accessing to desired gain and phase margin are shown. Numerical examples are given to illustrate the shapes of the stabilizing region and to show the design procedure.

Keywords: Fractional controller, Lead compensator, Stabilityregions, Stability boundary locus

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258 A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors

Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

Abstract:

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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257 Enhanced QoS Mechanisms for IEEE 802.11e Wireless Networks

Authors: Ho-Ting Wu, Min-Hua Yang, Kai-Wei Ke, Lei Yan

Abstract:

The quality-of-service (QoS) support for wireless LANs has been a hot research topic during the past few years. In this paper, two QoS provisioning mechanisms are proposed for the employment in 802.11e EDCA MAC scheme. First, the proposed call admission control mechanism can not only guarantee the QoS for the higher priority existing connections but also provide the minimum reserved bandwidth for traffic flows with lower priority. In addition, the adaptive contention window adjustment mechanism can adjust the maximum and minimum contention window size dynamically according to the existing connection number of each AC. The collision probability as well as the packet delay will thus be reduced effectively. Performance results via simulations have revealed the enhanced QoS property achieved by employing these two mechanisms.

Keywords: 802.11e, admission control, contention window, EDCA

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256 Modelling and Simulation of Cascaded H-Bridge Multilevel Single Source Inverter Using PSIM

Authors: Gaddafi S. Shehu, T. Yalcinoz, Abdullahi B. Kunya

Abstract:

Multilevel inverters such as flying capacitor, diodeclamped, and cascaded H-bridge inverters are very popular particularly in medium and high power applications. This paper focuses on a cascaded H-bridge module using a single direct current (DC) source in order to generate an 11-level output voltage. The noble approach reduces the number of switches and gate drivers, in comparison with a conventional method. The anticipated topology produces more accurate result with an isolation transformer at high switching frequency. Different modulation techniques can be used for the multilevel inverter, but this work features modulation techniques known as selective harmonic elimination (SHE).This modulation approach reduces the number of carriers with reduction in Switching Losses, Total Harmonic Distortion (THD), and thereby increasing Power Quality (PQ). Based on the simulation result obtained, it appears SHE has the ability to eliminate selected harmonics by chopping off the fundamental output component. The performance evaluation of the proposed cascaded multilevel inverter is performed using PSIM simulation package and THD of 0.94% is obtained.

Keywords: Cascaded H-bridge Multilevel Inverter, Power Quality, Selective Harmonic Elimination.

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255 Reducing Power in Error Correcting Code using Genetic Algorithm

Authors: Heesung Lee, Joonkyung Sung, Euntai Kim

Abstract:

This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method.

Keywords: Error correcting codes, genetic algorithm, non-linearpower optimization, Hamming code, Hsiao code.

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254 Enhanced Parallel-Connected Comb Filter Method for Multiple Pitch Estimation

Authors: Taro Matsuno, Yuta Otani, Ryo Tanaka, Kaori Ikezaki, Hitoshi Yamamoto, Masaru Fujieda, Yoshihisa Ishida

Abstract:

This paper presents an improvement method of the multiple pitch estimation algorithm using comb filters. Conventionally the pitch was estimated by using parallel -connected comb filters method (PCF). However, PCF has problems which often fail in the pitch estimation when there is the fundamental frequency of higher tone near harmonics of lower tone. Therefore the estimation is assigned to a wrong note when shared frequencies happen. This issue often occurs in estimating octave 3 or more. Proposed method, for solving the problem, estimates the pitch with every harmonic instead of every octave. As a result, our method reaches the accuracy of more than 80%.

Keywords: music transcription, pitch estimation, comb filter, fractional delay

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253 An Analysis of Global Stability of a Class of Neutral-Type Neural Systems with Time Delays

Authors: Ozlem Faydasicok, Sabri Arik

Abstract:

This paper derives some new sufficient conditions for the stability of a class of neutral-type neural networks with discrete time delays by employing a suitable Lyapunov functional. The obtained conditions can be easily verified as they can be expressed in terms of the network parameters only. It is shown that the results presented in this paper for neutral-type delayed neural networks establish a new set of stability criteria, and therefore can be considered as the alternative results to the previously published literature results. A numerical example is also given to demonstrate the applicability of our proposed stability criterion.

Keywords: Stability Analysis, Neutral-Type Neural Networks, Time Delay Systems, Lyapunov Functionals.

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252 A Novel Digital Implementation of AC Voltage Controller for Speed Control of Induction Motor

Authors: Ali M. Eltamaly, A. I. Alolah, R. Hamouda, M. Y. Abdulghany

Abstract:

In this paper a novel, simple and reliable digital firing scheme has been implemented for speed control of three-phase induction motor using ac voltage controller. The system consists of three-phase supply connected to the three-phase induction motor via three triacs and its control circuit. The ac voltage controller has three modes of operation depending on the shape of supply current. The performance of the induction motor differs in each mode where the speed is directly proportional with firing angle in two modes and inversely in the third one. So, the control system has to detect the current mode of operation to choose the correct firing angle of triacs. Three sensors are used to feed the line currents to control system to detect the mode of operation. The control strategy is implemented using a low cost Xilinx Spartan-3E field programmable gate array (FPGA) device. Three PI-controllers are designed on FPGA to control the system in the three-modes. Simulation of the system is carried out using PSIM computer program. The simulation results show stable operation for different loading conditions especially in mode 2/3. The simulation results have been compared with the experimental results from laboratory prototype.

Keywords: FPGA, Induction motor, PSIM, triac, Voltage controller.

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251 Experimental and Numerical Investigation of Flow Control Using a Novel Active Slat

Authors: Basman Elhadidi, Islam Elqatary, Osama Mohamady, Hesham Othman

Abstract:

An active slat is developed to increase the lift and delay the separation for a DU96-W180 airfoil. The active slat is a fixed slat that can be closed, fully opened or intermittently opened by a rotating vane depending on the need. Experimental results show that the active slat has reduced the mean pressure and increased the mean velocity on the suction side of the airfoil for all positive angles of attack, indicating an increase of lift. The experimental data and numerical simulations also show that the direction of actuator vane rotation can influence the mixing of the flow streams on the suction side and hence influence the aerodynamic performance.

Keywords: Active slat, flow control.

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