Search results for: Gate delay

Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

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In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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Authors: Yucai Ding, Hong Zhu, Shouming Zhong, Yuping Zhang

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This paper considers ­H∞ performance for Markovian jump systems with Time-varying delays. The systems under consideration involve disturbance signal, Markovian switching and timevarying delays. By using a new Lyapunov-Krasovskii functional and a convex optimization approach, a delay-dependent stability condition in terms of linear matrix inequality (LMI) is addressed, which guarantee asymptotical stability in mean square and a prescribed ­H∞ performance index for the considered systems. Two numerical examples are given to illustrate the effectiveness and the less conservatism of the proposed main results. All these results are expected to be of use in the study of stochastic systems with time-varying delays.

Keywords: ­H∞ performance, Markovian switching, Delaydependent stability, Linear matrix inequality (LMI)

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Authors: Kyoungjin Kim

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Nanoscale thermites such as the composite mixture of nano-sized aluminum and molybdenum trioxide powders possess several technical advantages such as much higher reaction rate and shorter ignition delay, when compared to the conventional energetic formulations made of micron-sized metal and oxidizer particles. In this study, the self-propagation of combustion wave in compacted pellets of nanoscale thermite composites is modeled and computationally investigated by utilizing the activation energy reduction of aluminum particles due to nanoscale particle sizes. The present computational model predicts the speed of combustion wave propagation which is good agreement with the corresponding experiments of thermite reaction. Also, several characteristics of thermite reaction in nanoscale composites are discussed including the ignition delay and combustion wave structures.

Keywords: Nanoparticles, Thermite reaction, Combustion wave, Numerical modeling.

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Authors: Hazem M. El-Bakry, Ahmed Atwan

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Computer networks are essential part in computerbased information systems. The performance of these networks has a great influence on the whole information system. Measuring the usability criteria and customers satisfaction on small computer network is very important. In this article, an effective approach for measuring the usability of business network in an information system is introduced. The usability process for networking provides us with a flexible and a cost-effective way to assess the usability of a network and its products. In addition, the proposed approach can be used to certify network product usability late in the development cycle. Furthermore, it can be used to help in developing usable interfaces very early in the cycle and to give a way to measure, track, and improve usability. Moreover, a new approach for fast information processing over computer networks is presented. The entire data are collected together in a long vector and then tested as a one input pattern. Proposed fast time delay neural networks (FTDNNs) use cross correlation in the frequency domain between the tested data and the input weights of neural networks. It is proved mathematically and practically that the number of computation steps required for the presented time delay neural networks is less than that needed by conventional time delay neural networks (CTDNNs). Simulation results using MATLAB confirm the theoretical computations.

Keywords: Usability Criteria, Computer Networks, Fast Information Processing, Cross Correlation, Frequency Domain.

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Authors: Khaja Kamaluddin, Muhammed Yousoof

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Available Bit Rate Service (ABR) is the lower priority service and the better service for the transmission of data. On wireline ATM networks ABR source is always getting the feedback from switches about increase or decrease of bandwidth according to the changing network conditions and minimum bandwidth is guaranteed. In wireless networks guaranteeing the minimum bandwidth is really a challenging task as the source is always in mobile and traveling from one cell to another cell. Re establishment of virtual circuits from start to end every time causes the delay in transmission. In our proposed solution we proposed the mechanism to provide more available bandwidth to the ABR source by re-usage of part of old Virtual Channels and establishing the new ones. We want the ABR source to transmit the data continuously (non-stop) inorderto avoid the delay. In worst case scenario at least minimum bandwidth is to be allocated. In order to keep the data flow continuously, priority is given to the handoff ABR call against new ABR call.

Keywords: Bandwidth allocation, Virtual Channel (VC), CBR, ABR, MCR and QOS.

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Authors: Khaled A. Madi

Abstract:

Induction motors are being used in greater numbers throughout a wide variety of industrial and commercial applications because it provides many benefits and reliable device to convert the electrical energy into mechanical motion. In some application it-s desired to control the speed of the induction motor. Because of the physics of the induction motor the preferred method of controlling its speed is to vary the frequency of the AC voltage driving the motor. In recent years, with the microcontroller incorporated into an appliance it becomes possible to use it to generate the variable frequency AC voltage to control the speed of the induction motor. This study investigates the microcontroller based variable frequency power inverter. the microcontroller is provide the variable frequency pulse width modulation (PWM) signal that control the applied voltage on the gate drive, which is provides the required PWM frequency with less harmonics at the output of the power inverter. The fully controlled bridge voltage source inverter has been implemented with semiconductors power devices isolated gate bipolar transistor (IGBT), and the PWM technique has been employed in this inverter to supply the motor with AC voltage. The proposed drive system for three & single phase power inverter is simulated using Matlab/Simulink. The Matlab Simulation Results for the proposed system were achieved with different SPWM. From the result a stable variable frequency inverter over wide range has been obtained and a good agreement has been found between the simulation and hardware of a microcontroller based single phase inverter.

Keywords: Power, inverter, PWM, microcontroller.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

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In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: Ming-Hsiang Shih, Wen-Pei Sung, Shih-Heng Tung

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The purposes of hydraulic gate are to maintain the functions of storing and draining water. It bears long-term hydraulic pressure and earthquake force and is very important for reservoir and waterpower plant. The high tensile strength of steel plate is used as constructional material of hydraulic gate. The cracks and rusts, induced by the defects of material, bad construction and seismic excitation and under water respectively, thus, the mechanics phenomena of gate with crack are probing into the cause of stress concentration, induced high crack increase rate, affect the safety and usage of hydroelectric power plant. Stress distribution analysis is a very important and essential surveying technique to analyze bi-material and singular point problems. The finite difference infinitely small element method has been demonstrated, suitable for analyzing the buckling phenomena of welding seam and steel plate with crack. Especially, this method can easily analyze the singularity of kink crack. Nevertheless, the construction form and deformation shape of some gates are three-dimensional system. Therefore, the three-dimensional Digital Image Correlation (DIC) has been developed and applied to analyze the strain variation of steel plate with crack at weld joint. The proposed Digital image correlation (DIC) technique is an only non-contact method for measuring the variation of test object. According to rapid development of digital camera, the cost of this digital image correlation technique has been reduced. Otherwise, this DIC method provides with the advantages of widely practical application of indoor test and field test without the restriction on the size of test object. Thus, the research purpose of this research is to develop and apply this technique to monitor mechanics crack variations of weld steel hydraulic gate and its conformation under action of loading. The imagines can be picked from real time monitoring process to analyze the strain change of each loading stage. The proposed 3-Dimensional digital image correlation method, developed in the study, is applied to analyze the post-buckling phenomenon and buckling tendency of welded steel plate with crack. Then, the stress intensity of 3-dimensional analysis of different materials and enhanced materials in steel plate has been analyzed in this paper. The test results show that this proposed three-dimensional DIC method can precisely detect the crack variation of welded steel plate under different loading stages. Especially, this proposed DIC method can detect and identify the crack position and the other flaws of the welded steel plate that the traditional test methods hardly detect these kind phenomena. Therefore, this proposed three-dimensional DIC method can apply to observe the mechanics phenomena of composite materials subjected to loading and operating.

Keywords: Welded steel plate, crack variation, three-dimensional Digital Image Correlation (DIC).

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Authors: Yi-Ting Mai, Chun-Chuan Yang, Cheng-Jung Wen

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IEEE 802.16 is a new wireless technology standard, it has some advantages, including wider coverage, higher bandwidth, and QoS support. As the new wireless technology for last mile solution, there are designed two models in IEEE 802.16 standard. One is PMP (point to multipoint) and the other is Mesh. In this paper we only focus on IEEE 802.16 Mesh model. According to the IEEE 802.16 standard description, Mesh model has two scheduling modes, centralized and distributed. Considering the pros and cons of the two scheduling, we present the combined scheduling QoS framework that the BS (Base Station) controls time frame scheduling and selects the shortest path from source to destination directly. On the other hand, we propose the Expedited Queue mechanism to cut down the transmission time. The EQ mechanism can reduce a lot of end-to-end delay in our QoS framework. Simulation study has shown that the average delay is smaller than contrasts. Furthermore, our proposed scheme can also achieve higher performance.

Keywords: IEEE 802.16 Mesh, Scheduling, Expedited Queue, QoS.

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Authors: B. Mahmoud, M.H. Bedoui, R. Raychev, H. Essabbah

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We present in this paper an acquisition and treatment system designed for semi-analog Gamma-camera. It consists of a nuclear medical Image Acquisition, Treatment and Display chain(IATD) ensuring the acquisition, the treatment of the signals(resulting from the Gamma-camera detection head) and the scintigraphic image construction in real time. This chain is composed by an analog treatment board and a digital treatment board. We describe the designed systems and the digital treatment algorithms in which we have improved the performance and the flexibility. The digital treatment algorithms are implemented in a specific reprogrammable circuit FPGA (Field Programmable Gate Array).interface for semi-analog cameras of Sopha Medical Vision(SMVi) by taking as example SOPHY DS7. The developed system consists of an Image Acquisition, Treatment and Display (IATD) ensuring the acquisition and the treatment of the signals resulting from the DH. The developed chain is formed by a treatment analog board and a digital treatment board designed around a DSP [2]. In this paper we have presented the architecture of a new version of our chain IATD in which the integration of the treatment algorithms is executed on an FPGA (Field Programmable Gate Array)

Keywords: Nuclear medical image, scintigraphic image, digitaltreatment, linearity, spectrometry, FPGA.

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Authors: Wenqin Wang, Shouming Zhong

Abstract:

This paper presents the robust stability criteria for uncertain genetic regulatory networks with time-varying delays. One key point of the criterion is that the decomposition of the matrix ˜D into ˜D = ˜D1 + ˜D2. This decomposition corresponds to a decomposition of the delayed terms into two groups: the stabilizing ones and the destabilizing ones. This technique enables one to take the stabilizing effect of part of the delayed terms into account. Meanwhile, by choosing an appropriate new Lyapunov functional, a new delay-dependent stability criteria is obtained and formulated in terms of linear matrix inequalities (LMIs). Finally, numerical examples are presented to illustrate the effectiveness of the theoretical results.

Keywords: Genetic regulatory network, Time-varying delay, Uncertain system, Lyapunov-Krasovskii functional

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Authors: Yoshifumi Ishizaki, Naoki Kanatani, Masaki Ito, Toshihiko Sasama, Takao Kawamura, Kazunori Sugahara

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This paper demonstrates the bus location system for the route bus through the experiment in the real environment. A bus location system is a system that provides information such as the bus delay and positions. This system uses actual services and positions data of buses, and those information should match data on the database. The system has two possible problems. One, the system could cost high in preparing devices to get bus positions. Two, it could be difficult to match services data of buses. To avoid these problems, we have developed this system at low cost and short time by using the smart phone with GPS and the bus route system. This system realizes the path planning considering bus delay and displaying position of buses on the map. The bus location system was demonstrated on route buses with smart phones for two months.

Keywords: Route Bus, Path Planning System, GPS, Smart Phone.

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Authors: V. K. Singh, P. K. Padhy

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This paper describes identification of the two poles unstable SOPDT process, especially with large time delay. A new modified relay feedback identification method for two poles unstable SOPDT process is proposed. Furthermore, for the two poles unstable SOPDT process, an additional Derivative controller is incorporated parallel with relay to relax the constraint on the ratio of delay to the unstable time constant, so that the exact model parameters of unstable processes can be identified. To cope with measurement noise in practice, a low pass filter is suggested to get denoised output signal toimprove the exactness of model parameter of unstable process. PID Lead-lag tuning formulas are derived for two poles unstable (SOPDT) processes based on IMC principle. Simulation example illustrates the effectiveness and the simplicity of the proposed identification and control method.

Keywords: IMC structure, PID Lead-lag controller, Relayfeedback, SOPDT

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Authors: Arash Moradkhani Roshandeh, Othman Che Puan

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Access Management is the proactive management of vehicular access points to land parcels adjacent to all manner of roadways. Good access management promotes safe and efficient use of the transportation network. This study attempts to utilize archived data from the University Technology of Malaysia on-campus area to assess the accuracy with which access management display some benefits. Results show that usage of access management reduces delay and fewer crashes. Clustered development can improve walking, cycling and transit travel, reduce parking requirements and improve emergency responses. Effective Access Management planning can also reduce total roadway facility costs by reducing the number of driveways and intersections. At the end after presenting recommendations some of the travel impact, and benefits that can be derived if these suggestions are implemented have been summarized with the related comments.

Keywords: Access Management, Delay, Density, Traffic Flow

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Authors: Yi Zhang, Quan Zhou, Jun Li, Yanlang Hu

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Scheduling algorithm is a key technology in satellite switching system with input-buffer. In this paper, a new scheduling algorithm and its realization are proposed. Based on Crossbar switching fabric, the algorithm adopts serial scheduling strategy and adjusts the output port arbitrating strategy for the better equity of every port. Consequently, it increases the matching probability. The algorithm can greatly reduce the scheduling delay and cell loss rate. The analysis and simulation results by OPNET show that the proposed algorithm has the better performance than others in average delay and cell loss rate, and has the equivalent complexity. On the basis of these results, the hardware realization and simulation based on FPGA are completed, which validate the feasibility of the new scheduling algorithm.

Keywords: Scheduling algorithm, input-buffer, serial scheduling, hardware design.

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Authors: Rehab Abdullah Shendi

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The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: M. Abbasi Dezfouli, S. Mazraeh, M. H. Yektaie

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Wireless sensor networks (WSN) consists of many sensor nodes that are placed on unattended environments such as military sites in order to collect important information. Implementing a secure protocol that can prevent forwarding forged data and modifying content of aggregated data and has low delay and overhead of communication, computing and storage is very important. This paper presents a new protocol for concealed data aggregation (CDA). In this protocol, the network is divided to virtual cells, nodes within each cell produce a shared key to send and receive of concealed data with each other. Considering to data aggregation in each cell is locally and implementing a secure authentication mechanism, data aggregation delay is very low and producing false data in the network by malicious nodes is not possible. To evaluate the performance of our proposed protocol, we have presented computational models that show the performance and low overhead in our protocol.

Keywords: Wireless Sensor Networks, Security, Concealed Data Aggregation.

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Authors: N. Mahendran, S. Vishwaja

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The Carry Select Adder (CSLA) is a fast adder which improves the speed of addition. From the structure of the CSLA, it is clear that there is opportunity for reducing the area. The logic operations involved in conventional CSLA and binary to excess-1 converter (BEC) based CSLA are analyzed to make a study on the data dependence and to identify redundant logic operations. In the existing adder design, the carry select (CS) operation is scheduled before the final-sum, which is different from the conventional CSLA design. In the presented scheme, Kogge stone parallel adder approach is used instead of existing adder design it will generate fast carry for intermediate stages and also improves the speed of addition. When compared to existing adder design the delay is less in the proposed adder design.

Keywords: Binary to excess-1 converter, delay, carry select adder, Kogge stone adder, speed.

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Authors: Peristera A. Baziana

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The idea of the asynchronous transmission in wavelength division multiplexing (WDM) ring MANs is studied in this paper. Especially, we present an efficient access technique to coordinate the collisions-free transmission of the variable sizes of IP traffic in WDM ring core networks. Each node is equipped with a tunable transmitter and a tunable receiver. In this way, all the wavelengths are exploited for both transmission and reception. In order to evaluate the performance measures of average throughput, queuing delay and packet dropping probability at the buffers, a simulation model that assumes symmetric access rights among the nodes is developed based on Poisson statistics. Extensive numerical results show that the proposed protocol achieves apart from high bandwidth exploitation for a wide range of offered load, fairness of queuing delay and dropping events among the different packets size categories.

Keywords: Asynchronous transmission, collision avoidance, wavelength division multiplexing.

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Authors: M. Abbasi Dezfouli, S. Mazraeh, M. H. Yektaie

Abstract:

Wireless sensor networks (WSN) consists of many sensor nodes that are placed on unattended environments such as military sites in order to collect important information. Implementing a secure protocol that can prevent forwarding forged data and modifying content of aggregated data and has low delay and overhead of communication, computing and storage is very important. This paper presents a new protocol for concealed data aggregation (CDA). In this protocol, the network is divided to virtual cells, nodes within each cell produce a shared key to send and receive of concealed data with each other. Considering to data aggregation in each cell is locally and implementing a secure authentication mechanism, data aggregation delay is very low and producing false data in the network by malicious nodes is not possible. To evaluate the performance of our proposed protocol, we have presented computational models that show the performance and low overhead in our protocol.

Keywords: Wireless Sensor Networks, Security, Concealed Data Aggregation.

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Authors: S. Chuenchooklin, T. Ichikawa, P. Mekpruksawong

Abstract:

This research was conducted in the Lower Namkam Irrigation Project situated in the Namkam River Basin in Thailand. Degradation of groundwater quality in some areas is caused by saline soil spots beneath ground surface. However, the tail regulated gate structure on the Namkam River, a lateral stream of the Mekong River. It is aimed for maintaining water level in the river at +137.5 to +138.5 m (MSL) and flow to the irrigation canals based on a gravity system since July 2009. It might leach some saline soil spots from underground to soil surface if lack of understanding of the conjunctive surface water and groundwater behaviors. This research has been conducted by continuously the observing of both shallow and deep groundwater level and quality from existing observation wells. The simulation of surface water was carried out using a hydrologic modeling system (HEC-HMS) to compute the ungauged side flow catchments as the lateral flows for the river system model (HEC-RAS). The constant water levels in the upstream of the operated gate caused a slight rising up of shallow groundwater level when compared to the water table. However, the groundwater levels in the confined aquifers remained less impacted than in the shallow aquifers but groundwater levels in late of wet season in some wells were higher than the phreatic surface. This causes salinization of the groundwater at the soil surface and might affect some crops. This research aims for the balance of water stage in the river and efficient groundwater utilization in this area.

Keywords: Surface water, groundwater observation, irrigation, water balance.

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Authors: H K Lakshminarayana, J S Bhat, H M Mahesh

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A new estimator for evolutionary spectrum (ES) based on short time Fourier transform (STFT) and modified group delay function (MGDF) by signal decomposition (SD) is proposed. The STFT due to its built-in averaging, suppresses the cross terms and the MGDF preserves the frequency resolution of the rectangular window with the reduction in the Gibbs ripple. The present work overcomes the magnitude distortion observed in multi-component non-stationary signals with STFT and MGDF estimation of ES using SD. The SD is achieved either through discrete cosine transform based harmonic wavelet transform (DCTHWT) or perfect reconstruction filter banks (PRFB). The MGDF also improves the signal to noise ratio by removing associated noise. The performance of the present method is illustrated for cross chirp and frequency shift keying (FSK) signals, which indicates that its performance is better than STFT-MGDF (STFT-GD) alone. Further its noise immunity is better than STFT. The SD based methods, however cannot bring out the frequency transition path from band to band clearly, as there will be gap in the contour plot at the transition. The PRFB based STFT-SD shows good performance than DCTHWT decomposition method for STFT-GD.

Keywords: Evolutionary Spectrum, Modified Group Delay, Discrete Cosine Transform, Harmonic Wavelet Transform, Perfect Reconstruction Filter Banks, Short Time Fourier Transform.

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Authors: Mohamed Fathy Heweage, Xiao Wen, Ayman Mokhtar, Ahmed Eldamarawy

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In this paper, we are interested in modeling, simulation, and measurement of the laser spot position with a quadrant detector. We enhance detection and tracking of semi-laser weapon decoding system based on microcontroller. The system receives the reflected pulse through quadrant detector and processes the laser pulses through a processing circuit, a microcontroller decoding laser pulse reflected by the target. The seeker accuracy will be enhanced by the decoding system, the laser detection time based on the receiving pulses number is reduced, a gate is used to limit the laser pulse width. The model is implemented based on Pulse Repetition Frequency (PRF) technique with two microcontroller units (MCU). MCU1 generates laser pulses with different codes. MCU2 decodes the laser code and locks the system at the specific code. The codes EW selected based on the two selector switches. The system is implemented and tested in Proteus ISIS software. The implementation of the full position determination circuit with the detector is produced. General system for the spot position determination was performed with the laser PRF for incident radiation and the mechanical system for adjusting system at different angles. The system test results show that the system can detect the laser code with only three received pulses based on the narrow gate signal, and good agreement between simulation and measured system performance is obtained.

Keywords: 4-quadrant detector, pulse code detection, laser guided weapons, pulse repetition frequency, ATmega 32 microcontrollers.

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Authors: Khenfer-Koummich Fatima, Mesbahi Larbi, Hendel Fatiha

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This paper presents a recognition system for isolated words like robot commands. It’s carried out by Time Delay Neural Networks; TDNN. To teleoperate a robot for specific tasks as turn, close, etc… In industrial environment and taking into account the noise coming from the machine. The choice of TDNN is based on its generalization in terms of accuracy, in more it acts as a filter that allows the passage of certain desirable frequency characteristics of speech; the goal is to determine the parameters of this filter for making an adaptable system to the variability of speech signal and to noise especially, for this the back propagation technique was used in learning phase. The approach was applied on commands pronounced in two languages separately: The French and Arabic. The results for two test bases of 300 spoken words for each one are 87%, 97.6% in neutral environment and 77.67%, 92.67% when the white Gaussian noisy was added with a SNR of 35 dB.

Keywords: Neural networks, Noise, Speech Recognition.

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Authors: Mohammed Shatnawi, Qusai Abuein, Susumu Shibusawa

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Signature amortization schemes have been introduced for authenticating multicast streams, in which, a single signature is amortized over several packets. The hash value of each packet is computed, some hash values are appended to other packets, forming what is known as hash chain. These schemes divide the stream into blocks, each block is a number of packets, the signature packet in these schemes is either the first or the last packet of the block. Amortization schemes are efficient solutions in terms of computation and communication overhead, specially in real-time environment. The main effictive factor of amortization schemes is it-s hash chain construction. Some studies show that signing the first packet of each block reduces the receiver-s delay and prevents DoS attacks, other studies show that signing the last packet reduces the sender-s delay. To our knowledge, there is no studies that show which is better, to sign the first or the last packet in terms of authentication probability and resistance to packet loss. In th is paper we will introduce another scheme for authenticating multicast streams that is robust against packet loss, reduces the overhead, and prevents the DoS attacks experienced by the receiver in the same time. Our scheme-The Multiple Connected Chain signing the First packet (MCF) is to append the hash values of specific packets to other packets,then append some hashes to the signature packet which is sent as the first packet in the block. This scheme is aspecially efficient in terms of receiver-s delay. We discuss and evaluate the performance of our proposed scheme against those that sign the last packet of the block.

Keywords: multicast stream authentication, hash chain construction, signature amortization, authentication probability.

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Authors: R. A. Isabel, E. Baburaj

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Wireless Body Area Networks (WBANs) are essential for real-time health monitoring of patients and in diagnosing of many diseases. WBANs comprise many sensors to monitor a large range of ambient conditions. Quality of Service (QoS) is a key challenge in WBAN, because the different state information of the neighboring nodes has to be monitored in an accurate manner. However, energy consumption gets increased while predicting and maintaining the exact information in highly dynamic environments. In order to reduce energy consumption and end to end delay, Markov Chain Based Quality of Service Support (MC-QoSS) method is designed in the health monitoring services of WBAN communication. The energy consumption gets reduced by forming a Markov chain with high energy nodes in the sensor networks communication path. The low energy level sensor nodes are removed using transitional probability in order to reduce end to end delay. High energy nodes are formed in the chain structure of its corresponding path to enhance communication. After choosing the communication path through high energy nodes, the packets are sent to the sink node from the source node with a higher Packet Delivery Ratio. The simulation result shows that MC-QoSS method improves the packet delivery ratio and reduces energy consumption with minimum end to end delay, compared to existing methods.

Keywords: Wireless body area networks, quality of service, Markov chain, health monitoring services.

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Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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Authors: Basma M. Mohammad El-Basioni, Sherine M. Abd El-kader, Hussein S. Eissa

Abstract:

This paper proposes an implementation for the directed diffusion paradigm aids in studying this paradigm-s operations and evaluates its behavior according to this implementation. The directed diffusion is evaluated with respect to the loss percentage, lifetime, end-to-end delay, and throughput. From these evaluations some suggestions and modifications are proposed to improve the directed diffusion behavior according to this implementation with respect to these metrics. The proposed modifications reflect the effect of local path repair by introducing a technique called Loop-free Local Path Repair (LLPR) which improves the directed diffusion behavior especially with respect to packet loss percentage by about 92.69%. Also LLPR improves the throughput and end-to-end delay by about 55.31% and 14.06% respectively, while the lifetime decreases by about 29.79%.

Keywords: Attribute-value based naming scheme, data gathering, data-centric routing, energy-efficiency, locality, wireless sensor network.

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Authors: Dinesh Kumar, Y. S. Brar, V. K. Banga

Abstract:

Multicast Network Technology has pervaded our lives-a few examples of the Networking Techniques and also for the improvement of various routing devices we use. As we know the Multicast Data is a technology offers many applications to the user such as high speed voice, high speed data services, which is presently dominated by the Normal networking and the cable system and digital subscriber line (DSL) technologies. Advantages of Multi cast Broadcast such as over other routing techniques. Usually QoS (Quality of Service) Guarantees are required in most of Multicast applications. The bandwidth-delay constrained optimization and we use a multi objective model and routing approach based on genetic algorithm that optimizes multiple QoS parameters simultaneously. The proposed approach is non-dominated routes and the performance with high efficiency of GA. Its betterment and high optimization has been verified. We have also introduced and correlate the result of multicast GA with the Broadband wireless to minimize the delay in the path.

Keywords: GA (genetic Algorithms), Quality of Service, MOGA, Steiner Tree.

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