Search results for: photonics integrated circuits (PIC)

Authors: J. Hajri, H. Hrizi, N. Sboui, H. Baudrand

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This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS.

Keywords: convergence study, HFSS, modal decomposition, SIW circuits, WCIP method

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Authors: S. Summart, C. Saetiaw, T. Thosdeekoraphat, C. Thongsopa

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This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Keywords: current-mode, quadrature oscillator, block diagram, CDTA

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Authors: Wieslaw Marszalek, Zdzislaw Trzaska

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Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed.

Keywords: mixed-mode oscillations, memristive circuits, pinched hysteresis, one-period loops, singularly perturbed circuits

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Do-Won Kim, Andy Eu Jin Lim, Raja Muthusamy Kumarasamy, Vishal Vinayak, Jacky Wang Yu-Shun, Jason Liow Tsung Yang, Patrick Lo Guo Qiang

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In this study, we demonstrate 4-channel coarse wavelength division multiplexing (CWDM) optical transceiver based on silicon photonics integrated circuits (PIC) of waveguide Ge-photodiode (Ge-PD) and Mach Zehnder (MZ)-modulator. 4-channel arrayed PICs of Ge-PD and MZ-modulator are verified to operate at 25 Gbps/ch achieving 4x25 Gbps of total data rate. 4 bare dies of single-channel commercial electronics ICs (EICs) of trans-impedance amplifier (TIA) for Ge-PD and driver IC for MZ-modulator are packaged with PIC on printed circuit board (PCB) in a chip-on-board (COB) manner. Each single-channel EIC is electrically connected to the one channel of 4-channel PICs by wire bonds to trace. The PICs have 4-channel multiplexer for MZ-modulator and 4-channel demultiplexer for Ge-PD. The 4-channel multiplexer/demultiplexer have echelle gratings for4 CWDM optic signals of which center wavelengths are 1511, 1531, 1553, and 1573 nm. Its insertion loss is around 4dB with over 15dB of extinction ratio.The dimension of 4-channel Ge-PD is 3.6x1.4x0.3mm, and its responsivity is 1A/W with dark current of less than 20 nA.Its measured 3dB bandwidth is around 20GHz. The dimension of the 4-channel MZ-modulator is 3.6x4.8x0.3mm, and its 3dB bandwidth is around 11Ghz at -2V of reverse biasing voltage. It has 2.4V•cmbyVπVL of 6V for π shift to 4 mm length modulator.5x5um of Inversed tapered mode size converter with less than 2dB of coupling loss is used for the coupling of the lensed fiber which has 5um of mode field diameter.The PCB for COB packaging and signal transmission is designed to have 6 layers in the hybrid layer structure. 0.25 mm-thick Rogers Duroid RT5880 is used as the first core dielectric layer for high-speed performance over 25 Gbps. It has 0.017 mm-thick of copper layers and its dielectric constant is 2.2and dissipation factor is 0.0009 at 10 GHz. The dimension of both single ended and differential microstrip transmission lines are calculated using full-wave electromagnetic (EM) field simulator HFSS which RF industry is using most. It showed 3dB bandwidth at around 15GHz in S-parameter measurement using network analyzer. The wire bond length for transmission line and ground connection from EIC is done to have less than 300 µm to minimize the parasitic effect to the system.Single layered capacitors (SLC) of 100pF and 1000pF are connected as close as possible to the EICs for stabilizing the DC biasing voltage by decoupling. Its signal transmission performance is under measurement at 25Gbps achieving 100Gbps by 4chx25Gbps. This work can be applied for the active optical cable (AOC) and quad small form-factor pluggable (QSFP) for high-speed optical interconnections. Its demands are quite large in data centers targeting 100 Gbps, 400 Gbps, and 1 Tbps. As the demands of high-speed AOC and QSFP for the application to intra/inter data centers increase, this silicon photonics based high-speed 4 channel CWDM scheme can have advantages not only in data throughput but also cost effectiveness since it reduces fiber cost dramatically through WDM.

Keywords: active optical cable(AOC), 4-channel coarse wavelength division multiplexing (CWDM), communication system, data center, ge-photodiode, Mach Zehnder (MZ) modulator, optical interconnections, optical transceiver, photonics integrated circuits (PIC), quad small form-factor pluggable (QSFP), silicon photonics

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Authors: Kaiwen Zheng, Wanting Zhou, Nan Tang, Lei Li, Yuanhang He

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The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs.

Keywords: hardware trojans, physical properties, machine learning, hardware security

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Authors: Md. Asaduzzaman

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A Silicon-on-insulator (SOI) perfectly vertical fibre-to-chip grating coupler is proposed and designed based on engineered subwavelength structures. The high directionality of the coupler is achieved by implementing step gratings to realize asymmetric diffraction and by applying effective index variation with auxiliary ultra-subwavelength gratings. The proposed structure is numerically analysed by using two-dimensional Finite Difference Time Domain (2D FDTD) method and achieves 96% (-0.2 dB) coupling efficiency and 39 nm 1-dB bandwidth. This highly efficient GC is necessary for applications where coupling efficiency between the optical fibre and nanophotonics waveguide is critically important, for instance, experiments of the quantum photonics integrated circuits. Such efficient and broadband perfectly vertical grating couplers are also significantly advantageous in highly dense photonic packaging.

Keywords: diffraction grating, FDTD, grating couplers, nanophotonic

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Authors: Zhengming Wu

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NanoFrazor lithography systems were developed as a first true alternative or extension to standard mask-less nanolithography methods like electron beam lithography (EBL). In contrast to EBL they are based on thermal scanning probe lithography (t-SPL). Here a heatable ultra-sharp probe tip with an apex of a few nm is used for patterning and simultaneously inspecting complex nanostructures. The heat impact from the probe on a thermal responsive resist generates those high-resolution nanostructures. The patterning depth of each individual pixel can be controlled with better than 1 nm precision using an integrated in-situ metrology method. Furthermore, the inherent imaging capability of the Nanofrazor technology allows for markerless overlay, which has been achieved with sub-5 nm accuracy as well as it supports stitching layout sections together with < 10 nm error. Pattern transfer from such resist features below 10 nm resolution were demonstrated. The technology has proven its value as an enabler of new kinds of ultra-high resolution nanodevices as well as for improving the performance of existing device concepts. The application range for this new nanolithography technique is very broad spanning from ultra-high resolution 2D and 3D patterning to chemical and physical modification of matter at the nanoscale. Nanometer-precise markerless overlay and non-invasiveness to sensitive materials are among the key strengths of the technology. However, while patterning at below 10 nm resolution is achieved, significantly increasing the patterning speed at the expense of resolution is not feasible by using the heated tip alone. Towards this end, an integrated laser write head for direct laser sublimation (DLS) of the thermal resist has been introduced for significantly faster patterning of micrometer to millimeter-scale features. Remarkably, the areas patterned by the tip and the laser are seamlessly stitched together and both processes work on the very same resist material enabling a true mix-and-match process with no developing or any other processing steps in between. The presentation will include examples for (i) high-quality metal contacting of 2D materials, (ii) tuning photonic molecules, (iii) generating nanofluidic devices and (iv) generating spintronic circuits. Some of these applications have been enabled only due to the various unique capabilities of NanoFrazor lithography like the absence of damage from a charged particle beam.

Keywords: nanofabrication, grayscale lithography, 2D materials device, nano-optics, photonics, spintronic circuits

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

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This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier

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Authors: Sam Zhang

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The landscape of Opto mechatronics is viewed along the line of light vs. matter, photonics vs. semiconductors, and optics vs. mechatronics. Optomechatronics is redefined as the integration of light and matter from the atom, device, and system to the application. The markets and megatrends in Opto mechatronics are further listed. The author then focuses on Opto mechatronic technology in the semiconductor industry as an example and reviews the practical systems, characteristics, and trends. Opto mechatronics, together with photonics and semiconductor, will continue producing the computational and smart infrastructure required for the 4th industrial revolution.

Keywords: photonics, semiconductor, optomechatronics, 4th industrial revolution

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

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This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

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In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: integrator circuits, MOS-C realization, nonlinearity cancellation, tuneable resistors

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Authors: Masaya Yoshikawa, Toshiya Asai, Ryoma Matsuhisa, Yusuke Nozaki, Kensaku Asahi

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Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources.

Keywords: tamper resistance, cryptographic circuit, hardware security evaluation, noise resources

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Authors: Juhi Faridi, Mohd. Ajmal Kafeel

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The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS.

Keywords: analog circuits, digital circuits, memristors, neuromorphic computing systems

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, M. Hanif M. Nasir

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This paper will discuss how EDA tools are integrated and automated in an Integrated Circuit Design Environment. Some of the problems face in our current environment is that users need to configure manually on the library paths, start-up files and project directories. Certain manual processes that happen between the users and applications can be automated but they must be transparent to the users. For example, the users can run the applications directly after login without knowing the library paths and start-up files locations. The solution to these problems is to automate the processes using standard configuration files which will benefit the users and EDA support. This paper will discuss how the implementation is done to automate the process using scripting languages such as Perl, Tcl, Scheme and Shell Script. These scripting tools are great assets for design engineers to build a robust and powerful design flow and this technique is widely used to integrate all the tools together.

Keywords: EDA tools, Integrated Circuits, scripting, integration, automation

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: N. Ourabia, M. Boubaker Ourabia

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An approach for modeling and numerical simulation of passive planar structures using the edge line concept is developed. With this method, we develop an efficient modeling technique for microstrip discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then, it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: optimization, CAD analysis, microwave circuits, S-parameters

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Authors: Mustafa İlhan Akbaş, Özlem Garibay, Ivan Garibay

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The economic entities in innovation ecosystems form various industry clusters, in which they compete and cooperate to survive and grow. Within a successful and stable industry cluster, the entities acquire different roles that complement each other in the system. The universities and research centers have been accepted to have a critical role in these systems for the creation and development of innovations. However, the real effect of research institutions on regional economic growth is difficult to assess. In this paper, we present our approach for the identification of the impact of research activities on the regional entrepreneurship for a specific high-tech industry: optics and photonics. The optics and photonics has been defined as an enabling industry, which combines the high-tech photonics technology with the developing optics industry. The recent literature suggests that the growth of optics and photonics firms depends on three important factors: the embedded regional specializations in the labor market, the research and development infrastructure, and a dynamic small firm network capable of absorbing new technologies, products and processes. Therefore, the role of each factor and the dynamics among them must be understood to identify the requirements of the entrepreneurship activities in optics and photonics industry. There are three main contributions of our approach. The recent studies show that the innovation in optics and photonics industry is mostly located around metropolitan areas. There are also studies mentioning the importance of research center locations and universities in the regional development of optics and photonics industry. These studies are mostly limited with the number of patents received within a short period of time or some limited survey results. Therefore the first contribution of our approach is conducting a comprehensive analysis for the state and recent history of the photonics and optics research in the US. For this purpose, both the research centers specialized in optics and photonics and the related research groups in various departments of institutions (e.g. Electrical Engineering, Materials Science) are identified and a geographical study of their locations is presented. The second contribution of the paper is the analysis of regional entrepreneurship activities in optics and photonics in recent years. We use the membership data of the International Society for Optics and Photonics (SPIE) and the regional photonics clusters to identify the optics and photonics companies in the US. Then the profiles and activities of these companies are gathered by extracting and integrating the related data from the National Establishment Time Series (NETS) database, ES-202 database and the data sets from the regional photonics clusters. The number of start-ups, their employee numbers and sales are some examples of the extracted data for the industry. Our third contribution is the utilization of collected data to investigate the impact of research institutions on the regional optics and photonics industry growth and entrepreneurship. In this analysis, the regional and periodical conditions of the overall market are taken into consideration while discovering and quantifying the statistical correlations.

Keywords: entrepreneurship, industrial clusters, optics, photonics, emerging industries, research centers

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Authors: Vanessa Funk, Steven Blum, Stephanie Cole, Jorge Maciel, Matthew Lux

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Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals.

Keywords: cell-free lysates, detection, gene circuits, in vitro

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Authors: A. Oukaira, A. Lakhssassi, O. Ettahri

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To make a good thermal management in an ABDM (Adapter Board Detector Module) card, we must first control temperature and its gradient from the first step in the design of integrated circuits ASIC of our complex system. In this paper, our main goal is to develop and validate the thermal stability in order to get an idea of the flow of heat around the ASIC in transient and thus address the thermal issues for integrated circuits at the ABDM card. However, we need heat sources simulations for ABDM card to establish its thermal mapping. This led us to perform simulations at each ASIC that will allow us to understand the thermal ABDM map and find real solutions for each one of our complex system that contains 36 ABDM map, taking into account the different layers around ASIC. To do a transient simulation under NISA, we had to build a function of power modulation in time TIMEAMP. The maximum power generated in the ASIC is 0.6 W. We divided the power uniformly in the volume of the ASIC. This power was applied for 5 seconds to visualize the evolution and distribution of heat around the ASIC. The DBC (Dirichlet Boundary conditions) method was applied around the ABDM at 25°C and just after these simulations in NISA tool we will validate them by COMSOL tool, wich is a numerical calculation software for a modular finite element for modeling a wide variety of physical phenomena characterizing a real problem. It will also be a design tool with its ability to handle 3D geometries for complex systems.

Keywords: ABDM, APD, thermal mapping, complex system

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Authors: Mir Shahriar Emami

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Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models.

Keywords: SDLC, SSDLC, software security, software process engineering, hardware systems and circuits security

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Authors: K. Shaji Mon, P. R. John Sreenidhi

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In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Roumaissa Derdour, Lebbal Mohamed Redha

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We present a study of the transmission of the all-optical logic gate using a structure connected with a triangular photonic crystal lattice that is improved. The proposed logic gate consists of a photonic crystal nano-resonator formed by changing the size of the air holes. In addition to the simplicity, the response time is very short, and the designed nano-resonator increases the bit rate of the logic gate. The two-dimensional finite difference time domain (2DFDTD) method is used to simulate the structure; the transmission obtained is about 98% with very negligible losses. The proposed photonic crystal AND logic gate is widely used in future integrated optical microelectronics.

Keywords: logic gates, photonic crystals, optical integrated circuits, resonant cavities

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Authors: Nassim Ourabia, Malika Ourabia

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A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: CAD analysis, contour integral approach, microwave circuits, s-parameters

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Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: G. N. Srinivas, K. Raju

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This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS).

Keywords: distribution system, Markov Model, reliability indices, spice simulation

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Authors: Haifeng Zhou, Tsungyang Liow, Xiaoguang Tu, Eujin Lim, Chao Li, Junfeng Song, Xianshu Luo, Ying Huang, Lianxi Jia, Lianwee Luo, Kim Dowon, Qing Fang, Mingbin Yu, Guoqiang Lo

Abstract:

Several Germanium photodetectors (PD) built on silicon micro-disks are fabricated on the standard Si photonics multiple project wafers (MPW) and demonstrated to exhibit very low dark current, satisfactory operation bandwidth and moderate responsivity. Among them, a vertical p-i-n Ge PD based on a 2.0 µm-radius micro-disk has a dark current of as low as 35 nA, compared to a conventional PD current of 1 µA with an area of 100 µm2. The operation bandwidth is around 15 GHz at a reverse bias of 1V. The responsivity is about 0.6 A/W. Microdisk is a striking planar structure in integrated optics to enhance light-matter interaction and construct various photonics devices. The disk geometries feature in strongly and circularly confining light into an ultra-small volume in the form of whispering gallery modes. A laser may benefit from a microdisk in which a single mode overlaps the gain materials both spatially and spectrally. Compared to microrings, micro-disk removes the inner boundaries to enable even better compactness, which also makes it very suitable for some scenarios that electrical connections are needed. For example, an ultra-low power (≈ fJ) athermal Si modulator has been demonstrated with a bit rate of 25Gbit/s by confining both photons and electrically-driven carriers into a microscale volume.In this work, we study Si-based PDs with Ge selectively grown on a microdisk with the radius of a few microns. The unique feature of using microdisk for Ge photodetector is that mode selection is not important. In the applications of laser or other passive optical components, microdisk must be designed very carefully to excite the fundamental mode in a microdisk in that essentially the microdisk usually supports many higher order modes in the radial directions. However, for detector applications, this is not an issue because the local light absorption is mode insensitive. Light power carried by all modes are expected to be converted into photo-current. Another benefit of using microdisk is that the power circulation inside avoids any introduction of the reflector. A complete simulation model with all involved materials taken into account is established to study the promise of microdisk structures for photodetector by using finite difference time domain (FDTD) method. By viewing from the current preliminary data, the directions to further improve the device performance are also discussed.

Keywords: integrated optical devices, silicon photonics, micro-resonator, photodetectors

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Authors: Fawzi Srairi, Abderrahmane Dib

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Recently, the desire for a self-powered micro and nanodevices has attracted a great interest of using sustainable energy sources. Further, the ultimate goal of nanogenerator is to harvest energy from the ambient environment in which a self-powered device based on these generators is needed. With the development of nanogenerator-based circuits design and optimization, the building of new device simulator is necessary for the study and the synthesis of electromechanical parameters of this type of models. In the present article, both numerical modeling and optimization of piezoelectric nanogenerator based on zinc oxide have been carried out. They aim to improve the electromechanical performances, robustness, and synthesis process for nanogenerator. The proposed model has been developed for a systematic study of the nanowire morphology parameters in stretching mode. In addition, heuristic optimization technique, namely, particle swarm optimization has been implemented for an analytic modeling and an optimization of nanogenerator-based process in stretching mode. Moreover, the obtained results have been tested and compared with conventional model where a good agreement has been obtained for excitation mode. The developed nanogenerator model can be generalized, extended and integrated into simulators devices to study nanogenerator-based circuits.

Keywords: electrical potential, heuristic algorithms, numerical modeling, nanogenerator

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

Procedia PDF Downloads 286

Authors: B. G. Abiona

Abstract:

This study compared profitability analysis of integrated and non-integrated fish farming in Ogun State, Nigeria. Primary data were collected using interview guide. Random sampling techniques was used to select 133 non-integrated fish farmers (NIFF) and 216 integrated fish farmers (IFF) (n = 349) from the study area. Data were analyzed using Chi-square, T-test and Pearson Product moment correlation. Results showed that 92.5% of NIFF was male compared to IFF (90.7%). Also, 96.8% of IFF and 79.7% of NIFF were married. The mean ages of sampled farmers were 44 years (NIFF) and 46 years (IFF) while the mean fish farming experiences were 4 years (NIFF) and 5 years (IFF). Also, the average net profit per year of integrated fish farmers was ₦162,550 compared to NIFF (₦61,638). The chi-square analyses showed that knowledge of fish farming had significant relationship with respondents sex (χ2 = 9.44, df = 2, p < 0.05), age (r = 0.20, p< 0.05) and farming experience (r = p = 0.05). Significant differences exist between integrated and non-integrated fish farming, considering their knowledge of fish farming (t = 21.5, χ = 43.01, p < 0.05). The study concluded that IFF are more profitable compared to NIFF. It was recommended that private investors and NGOs should sponsor short training and courses which will enhance efficiency of fish farming to boost productivity among fish farmers.

Keywords: profitability analysis, farms, integration

Procedia PDF Downloads 298