Search results for: high speed low power full adder

Authors: Biswarup Mukherjee, Aniruddha Ghoshal

Abstract:

In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Ch. Ashok Babu, J. V. R. Ravindra, K. Lalkishore

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Power has became a burning issue in modern VLSI design. As the technology advances especially below 45nm, technology of leakage power became a big problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder, DTMOS full adder. This paper shows different types of adders and their power consumption, area, and delay. All the experiments have been carried out using Cadence® Virtuoso® design lay out editor which shows power consumption of different types of adders.

Keywords: average power, leakage power, delay, DTMOS, PDP

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

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At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

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Authors: T. Angeline Priyanka, R. Ganesan

Abstract:

Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Anil Kumar Pandey

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Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: power integrity, power-aware signal integrity analysis, electromagnetic simulation, channel simulation

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Authors: Tayab D. Memon, Shahji Farooque, Marvi Deshi, Imtiaz Hussain Kalwar, B. S. Chowdhry

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Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this paper, an optimized adder module for ternary quantized sigma-delta modulated signal is presented. The adder is simulated using ModelSim for functional verification the area-performance of the proposed adder were obtained through synthesis in Xilinx and compared to conventional adder trees. The synthesis results show that the proposed adder tree achieves higher clock rates and lower chip area at higher inputs to the adder block; whereas conventional adder tree achieves better performance and lower chip area at lower number of inputs to the same adder block. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Keywords: short word length (SWL), DSP algorithms, FPGA, SBTFF, VHDL

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Authors: Mohammad Hedar

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This paper presents selected topics from the area of high-speed electrical machine control with a focus on loss minimization. It focuses on pulse amplitude modulation (PAM) set-up in order to minimize the inrush current peak. An overview of these machines and the control topologies that have been used with these machines are reported. The critical problem that happens when controlling a high-speed electrical motor is the high current peak in the start-up process, which will cause high power-losses. The main goal of this paper is to clarify how the inrush current peak can be minimized in the start-up process. PAM control method is proposed to use in the frequency inverter, simulation results for PAM & PWM control method, and steps to improve the PAM control are reported. The simulations were performed with data for PMSM (nominal speed: 25 000 min-1, power: 3.1 kW, load: 1.2 Nm).

Keywords: control topology, frequency inverter, high-speed electrical machines, PAM, power losses, PWM

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Authors: Vaishnavi Patil, K. M. Kurundkar

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Electrical Drives play a vital role in industry development and applications. Drives have an inevitable part in the needs of various fields such as industry, commercial, and domestic applications. The development of material technology, Power Electronics devices, and accompanying applications led to the focus of industry and researchers on high-speed electrical drives. Numerous articles charted the applications of electrical machines and various converters for high-speed applications. The choice depends on the application under study. This paper goals to highlight high-speed applications, main challenges, and some applications of electrical drives in the field.

Keywords: high-speed, electrical machines, drives, applications

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Authors: Michael C. Barbecho, Romeo B. Morcilla

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This study focused on the development of a solar powered front wheel drive electric trike for personal use and short distance travel, utilizing solar power and a variable speed transmission to adapt in places where varying road grades and unavailability of plug-in charging stations are of great problems. The actual performance of the vehicle was measured in terms of duration of charging using solar power, distance travel and battery power duration, top speed developed at full power, and load capacity. This project followed the research and development process which involved planning, designing, construction, and testing. Solar charging tests revealed that the vehicle requires 6 to 8 hours sunlight exposure to fully charge the batteries. At full charge, the vehicle can travel 35 km utilizing battery power down to 42%. Vehicle showed top speed of 25 kph at 0 to 3% road grade carrying a maximum load of 122 kg. The maximum climbing grade was 23% with the vehicle carrying a maximum load of 122 kg. Technically the project was feasible and can be a potential model for possible conversion of traditional Philippine made “pedicabs” and gasoline engine powered tricycle into modern electric vehicles. Moreover, it has several technical features and advantages over a commercialized electric vehicle such as the use solar charging system and variable speed power transmission and front drive power train for adaptability in any road gradient.

Keywords: electric vehicle, solar vehicles, front drive, solar, solar power

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Authors: S. Ozeri, D. Shmilovitz

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Micro‐Turbine Generators (MTG) are small size power plants that consist of a high speed, gas turbine driving an electrical generator. MTGs may be fueled by either natural gas or kerosene and may also use sustainable and recycled green fuels such as biomass, landfill or digester gas. The typical ratings of MTGs start from 20 kW up to 200 kW. The primary use of MTGs is for backup for sensitive load sites such as hospitals, and they are also considered a feasible power source for Distributed Generation (DG) providing on-site generation in proximity to remote loads. The MTGs have the compressor, the turbine, and the electrical generator mounted on a single shaft. For this reason, the electrical energy is generated at high frequency and is incompatible with the power grid. Therefore, MTGs must contain, in addition, a power conditioning unit to generate an AC voltage at the grid frequency. Presently, this power conditioning unit consists of a rectifier followed by a DC/AC inverter, both rated at the full MTG’s power. The losses of the power conditioning unit account to some 3-5%. Moreover, the full-power processing stage is a bulky and costly piece of equipment that also lowers the overall system reliability. In this study, we propose a new type of power conditioning stage in which only a small fraction of the power is processed. A low power converter is used only to program the rotor current (i.e. the excitation current which is substantially lower). Thus, the MTG's output voltage is shaped to the desired amplitude and frequency by proper programming of the excitation current. The control is realized by causing the rotor current to track the electrical frequency (which is related to the shaft frequency) with a difference that is exactly equal to the line frequency. Since the phasor of the rotation speed and the phasor of the rotor magnetic field are multiplied, the spectrum of the MTG generator voltage contains the sum and the difference components. The desired difference component is at the line frequency (50/60 Hz), whereas the unwanted sum component is at about twice the electrical frequency of the stator. The unwanted high frequency component can be filtered out by a low-pass filter leaving only the low-frequency output. This approach allows elimination of the large power conditioning unit incorporated in conventional MTGs. Instead, a much smaller and cheaper fractional power stage can be used. The proposed technology is also applicable to other high rotation generator sets such as aircraft power units.

Keywords: gas turbine, inverter, power multiplier, distributed generation

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Authors: Ich Long Ngo, Dinh Tai Dang, Ngoc Tu Nguyen, Minh Duc Nguyen

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This paper describes an investigation on designing and enhancing the performance of H-Darrieus wind turbine (HDWT) of 10kW at the medium wind speed. The aerodynamic characteristics of this turbine were investigated by both theoretical and numerical approaches. The optimal design procedure was first proposed to enhance the power coefficient under various effects, such as airfoil type, number of blades, solidity, aspect ratio, and tip speed ratio. As a result, the overall design of the 10kW HDWT was well achieved, and the power characteristic of this turbine was found by numerical approach. Additionally, the maximum power coefficient predicted is up to 0.41 at the tip speed ratio of 3.7 and wind speed of 8 m/s. Particularly, a generalized correlation of power coefficient with tip speed ratio and wind speed is first proposed. These results obtained are very useful for enhancing the performance of the HDWTs placed in a country with high wind power potential like Vietnam.

Keywords: computational fluid dynamics, double multiple stream tube, h-darrieus wind turbine, renewable energy

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: M. Yousefi, N. Nasirzadeh

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In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: efficiency, comparator, power, low

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Authors: S. Padmapriya, V. Lakshmi Prabha

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In this paper, an efficient reconfigurable fixed-point Least Mean Square Adaptive FIR filter is proposed. The proposed architecture has two methods of operation: one is area efficient design and the other is optimized power. Pipelining of the adder blocks and partial product generator are used to achieve low area and reversible logic is used to obtain low power design. Depending upon the input samples and filter coefficients, one of the techniques is chosen. Least-Mean-Square adaptation is performed to update the weights. The architecture is coded using Verilog and synthesized in cadence encounter 0.18μm technology. The synthesized results show that the area reduction ratio of the proposed when compared with conventional technique is about 1.2%.

Keywords: adaptive filter, carry select adder, least mean square algorithm, reversible logic

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Authors: Daniyar Seitenov, Nazim Mir-Nasiri

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Optimization of horizontal axis semi-exposed wind turbine has been performed using a shield protection that automatically protects the generator shaft at extreme wind speeds from over speeding, mechanical damage and continues generating electricity during the high wind speed conditions. A semi-exposed to wind generator has been designed and its structure has been described in this paper. The simplified point-force dynamic load model on the blades has been derived for normal and extreme wind conditions with and without shield involvement. Numerical simulation has been conducted at different values of wind speed to study the efficiency of shield application. The obtained results show that the maximum power generated by the wind turbine with shield does not exceed approximately the rated value of the generator, where shield serves as an automatic break for extreme wind speed values of 15 m/sec and above. Meantime the wind turbine without shield produced a power that is much larger than the rated value. The optimized horizontal axis semi-exposed wind turbine with shield protection is suitable for low and medium power generation when installed on the roofs of high rise buildings for harvesting wind energy. Wind shield works automatically with no power consumption. The structure of the generator with the protection, math simulation of kinematics and dynamics of power generation has been described in details in this paper.

Keywords: renewable energy, wind turbine, wind turbine optimization, high wind speed

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Authors: Bassim Shaheen Bachy, Jörg Franke

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In this study, a three dimensional numerical heat transfer model has been used to simulate the laser structuring of polymer substrate material in the Three-Dimensional Molded Interconnect Device (3D MID) which is used in the advanced multi-functional applications. A finite element method (FEM) transient thermal analysis is performed using APDL (ANSYS Parametric Design Language) provided by ANSYS. In this model, the effect of surface heat source was modeled with Gaussian distribution, also the effect of the mixed boundary conditions which consist of convection and radiation heat transfers have been considered in this analysis. The model provides a full description of the temperature distribution, as well as calculates the depth and the width of the groove upon material removal at different set of laser parameters such as laser power and laser speed. This study also includes the experimental procedure to study the effect of laser parameters on the depth and width of the removal groove metal as verification to the modeled results. Good agreement between the experimental and the model results is achieved for a wide range of laser powers. It is found that the quality of the laser structure process is affected by the laser scan speed and laser power. For a high laser structured quality, it is suggested to use laser with high speed and moderate to high laser power.

Keywords: laser structuring, simulation, finite element analysis, thermal modeling

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Authors: Mahendrapal Singh Pachlaniya, Laxmi Kumre

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The AOI (AND – OR- INVERTER) based design of XOR gate is proposed in this paper with less number of gates. This new XOR gate required four basic gates and basic gate include only AND, OR, Inverter (AOI). Conventional XOR gate required five basic gates. Ripple Carry Adder (RCA) used in parallel addition but propagation delay time is large. RCA replaced with Carry Select Adder (CSLA) to reduce propagation delay time. CSLA design with dual RCA considering carry = ‘0’ and carry = ‘1’, so it is not an area efficient adder. To make area efficient, modified CSLA is designed with single RCA considering carry = ‘0’ and another RCA considering carry = ‘1’ replaced with Binary to Excess 1 Converter (BEC). Now replacement of conventional XOR gate by new design of XOR gate in modified CSLA reduces much area compared to regular CSLA and modified CSLA.

Keywords: CSLA, BEC, XOR gate, area efficient

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Authors: Júlio Cesar Lopes de Oliveira, Carlos Henrique Gonçalves Treviso

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The shortage of the automotive market in relation to options for sources of high power car audio systems, led to development of this work. Thus, we developed a source with stabilized voltage with 4320 W effective power. Designed to the voltage of 14.4 V and a choice of two currents: 30 A load option in battery banks and 300 A at full load. This source can also be considered as a source of general use dedicated commercial with a simple control circuit in analog form based on discrete components. The assembly of power circuit uses a methodology for higher power than the initially stipulated.

Keywords: DC-DC power converters, converters, power conversion, pulse width modulation converters

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Authors: Jairo Alejandro Fernandez Ortega

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Objective: Regarding effects of training velocity on strength in the functional condition of older adults controversy exists. The purpose of this study was to examine the effects of a twelve-week strength training program (PE) performed at high speed (GAV) versus a traditionally executed program (GBV), on functional performance, maximum strength and muscle power in a group of older adult women. Methodology: 86 women aged between 60-81 years participated voluntarily in the study and were assigned randomly to the GAV (three series at 40% 1RM at maximum speed, with maximum losses of 10% speed) or to the GBV (three series with three sets at 70% of 1RM). Both groups performed three weekly trainings. The maximum strength of upper and lower limbs (1RM), prehensile strength, walking speed, maximum power, mean propulsive velocity (MPV) and functional performance (senior fitness test) were evaluated before and after the PE. Results: Significant improvements were observed (p < 0.05) in all the tests in the two groups after the twelve weeks of training. However, the results of GAV were significantly (P < 0.05) higher than those of the GBV, in the tests of agility and dynamic equilibrium, stationary walking, sitting and standing, walking speed over 4 and 6 meters, MPV and peak power. In the tests of maximum strength and prehensile force, the differences were not significant. Conclusion: Strength training performed at high speeds seems to have a better effect on functional performance and muscle power than strength training performed at low speed.

Keywords: power training, resistance exercise, aging, strength, physical performance, high-velocity, resistance training

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Authors: Fujian Wang, Shubin Ruan, Meiwei Dai

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Speed dispersion has tight relation to traffic safety. In this paper, several kinds of indicating parameters (the standard speed deviation, the coefficient of variation, the deviation of V85 and V15, the mean speed deviations, and the difference between adjacent car speeds) are applied to investigate the characteristics of speed dispersion, where V85 and V15 are 85th and 15th percentile speed, respectively. Their relationships are into full investigations and the results show that: there exists a positive relation (linear) between mean speed and the deviation of V85 and V15; while a negative relation (quadratic) between traffic flow and standard speed deviation. The mean speed deviation grows exponentially with mean speed while the absolute speed deviation between adjacent cars grows linearly with the headway. The results provide some basic information for traffic management.

Keywords: headway, indicating parameters, speed dispersion, urban expressway

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Authors: Saeed Hosseini, Ali Reza Tahavvor

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Sound processing is one the subjects that newly attracts a lot of researchers. It is efficient and usually less expensive than other methods. In this paper the flow generated sound is used to estimate the flow speed of free flows. Many sound samples are gathered. After analyzing the data, a parameter named wave power is chosen. For all samples, the wave power is calculated and averaged for each flow speed. A curve is fitted to the averaged data and a correlation between the wave power and flow speed is founded. Test data are used to validate the method and errors for all test data were under 10 percent. The speed of the flow can be estimated by calculating the wave power of the flow generated sound and using the proposed correlation.

Keywords: the flow generated sound, free stream, sound processing, speed, wave power

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Authors: Mohammadreza Heydariazad

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Productivity growth of wind energy as a clean source needed to achieve improved strategy in production and transmission and management of wind resources in order to increase quality of power and reduce costs. New technologies based on power converters that cause changing turbine speed to suit the wind speed blowing turbine improve extraction efficiency power from wind. This article introduces variable speed wind turbines and optimization of power, and presented methods to use superconducting inductor in the composition of power converter and is proposed the dc measurement for the wind farm and especially is considered techniques available to them. In fact, this article reviews mechanisms and function, changes of wind speed turbine according to speed control strategies of various types of wind turbines and examines power possible transmission and ac from producing location to suitable location for a strong connection integrating wind farm generators, without additional cost or equipment. It also covers main objectives of the dynamic control of wind turbines, and the methods of exploitation and the ways of using it that includes the unique process of these components. Effective algorithm is presented for power control in order to extract maximum active power and maintains power factor at the desired value.

Keywords: wind energy, generator, superconducting inductor, wind turbine power

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Authors: Ehsan Javanmardemamgheisi, Javad Mehr, Jason Ali-Lavroff, Damien Holloway, Michael Davis

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During the last decades, a growing interest in faster and more efficient waterborne transportation has led to the development of high-speed vessels for both commercial and military applications. To satisfy this global demand, a wide variety of arrangements of high-speed crafts have been proposed by designers. Among them, high-speed catamarans have proven themselves to be a suitable Roll-on/Roll-off configuration for carrying passengers and cargo due to widely spaced demi hulls, a wide deck zone, and a high ratio of deadweight to displacement. To improve passenger comfort and crew workability and enhance the operability and performance of high-speed catamarans, mitigating the severity of motions and structural loads using Ride Control Systems (RCS) is essential.In this paper, a set of towing tank tests was conducted on a 2.5 m scaled model of a 112 m Incat Tasmania high-speed catamaran in irregular head seas to investigate the effect of different ride control algorithms including linear and nonlinear versions of the heave control, pitch control, and local control on motion responses and passenger comfort of the full-scale ship. The RCS included a centre bow-fitted T-Foil and two transom-mounted stern tabs. All the experiments were conducted at the Australian Maritime College (AMC) towing tank at a model speed of 2.89 m/s (37 knots full scale), a modal period of 1.5 sec (10 sec full scale) and two significant wave heights of 60 mm and 90 mm, representing full-scale wave heights of 2.7 m and 4 m, respectively. Spectral analyses were performed using Welch’s power spectral density method on the vertical motion time records of the catamaran model to calculate heave and pitch Response Amplitude Operators (RAOs). Then, noting that passenger discomfort arises from vertical accelerations and that the vertical accelerations vary at different longitudinal locations within the passenger cabin due to the variations in amplitude and relative phase of the pitch and heave motions, the vertical accelerations were calculated at three longitudinal locations (LCG, T-Foil, and stern tabs). Finally, frequency-weighted Root Mean Square (RMS) vertical accelerations were calculated to estimate Motion Sickness Dose Value (MSDV) of the ship based on ISO 2631-recommendations. It was demonstrated that in small seas, implementing a nonlinear pitch control algorithm reduces the peak pitch motions by 41%, the vertical accelerations at the forward location by 46%, and motion sickness at the forward position by around 20% which provides great potential for further improvement in passenger comfort, crew workability, and operability of high-speed catamarans.

Keywords: high-speed catamarans, ride control system, response amplitude operators, vertical accelerations, motion sickness, irregular waves, towing tank tests.

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Authors: Chen Yong, Bi Wangyang, Zang Libin, Li Jinkai, Cheng Xiaowei, Liu Jinmin, Yu Miao

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New energy vehicle power transmission systems continue to develop in the direction of high torque, high speed, and high efficiency. The cooling and lubrication of the motor and the transmission system are integrated, and new requirements are placed on the lubricants for the transmission system. The effects of traditional lubricants and special lubricants for new energy vehicles on transmission efficiency were studied through experiments and simulation methods. A mathematical model of the transmission efficiency of the lubricating oil in the gearbox was established. The power loss of each part was analyzed according to the working conditions. The relationship between the speed and the characteristics of different lubricating oil products on the power loss of the stirring oil was discussed. The minimum oil film thickness was required for the life of the gearbox. The accuracy of the calculation results was verified by the transmission efficiency test conducted on the two-motor integrated test bench. The results show that the efficiency increases first and then decreases with the increase of the speed and decreases with the increase of the kinematic viscosity of the lubricant. The increase of the kinematic viscosity amplifies the transmission power loss caused by the high speed. New energy vehicle special lubricants have less attenuation of transmission efficiency in the range above mid-speed. The research results provide a theoretical basis and guidance for the evaluation and selection of transmission efficiency of gearbox lubricants for new energy vehicles.

Keywords: new energy vehicles, lubricants, transmission efficiency, kinematic viscosity, test and simulation

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Authors: M. Towhidur Rahman, Nasim Zaman Piyas, M. Sadiqul Baree, Shahnewaz Ahmed

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The design of high-speed craft has recently become one of the most active areas of naval architecture. Speed increase makes these vehicles more efficient and useful for military, economic or leisure purpose. The planing hull is designed specifically to achieve relatively high speed on the surface of the water. Speed on the water surface is closely related to the size of the vessel and the installed power. The Savitsky method was first presented in 1964 for application to non-monohedric hulls and for application to stepped hulls. This method is well known as a reliable comparative to CFD analysis of hull resistance. A computer program based on Savitsky’s method has been developed using MATLAB. The power of high-speed vessels has been computed in this research. At first, the program reads some principal parameters such as displacement, LCG, Speed, Deadrise angle, inclination of thrust line with respect to keel line etc. and calculates the resistance of the hull using empirical planning equations of Savitsky. However, some functions used in the empirical equations are available only in the graphical form, which is not suitable for the automatic computation. We use digital plotting system to extract data from nomogram. As a result, value of wetted length-beam ratio and trim angle can be determined directly from the input of initial variables, which makes the power calculation automated without manually plotting of secondary variables such as p/b and other coefficients and the regression equations of those functions are derived by using data from different charts. Finally, the trim angle, mean wetted length-beam ratio, frictional coefficient, resistance, and power are computed and compared with the results of Savitsky and good agreement has been observed.

Keywords: nomogram, planing hull, principal parameters, regression

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Authors: Andri Setiyoso, Agus Purwadi, Nanda Avianto Wicaksono

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This paper present about induction generator design for 100kW power output capacity. Induction machine had been chosen because of the capability for energy conversion from electric energy to mechanical energy and vise-versa with operation on variable speed condition. Stator Controlled Induction Generator (SCIG) was applied as wind power plant in Desa Taman Jaya, Sukabumi, Indonesia. Generator was designed to generate power 100 kW with wind speed at 12 m/s and survival condition at speed 21 m/s.

Keywords: wind energy, induction generator, Stator Controlled Induction Generator (SCIG), variable speed generator

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