Search results for: ASIC (application specific integrated circuit)

Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) is developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: biomedical sensor, decimation filter, radio frequency integrated circuit (RFIC) baseband, temperature sensor

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

Abstract:

In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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Authors: A. Oukaira, A. Lakhssassi, O. Ettahri

Abstract:

To make a good thermal management in an ABDM (Adapter Board Detector Module) card, we must first control temperature and its gradient from the first step in the design of integrated circuits ASIC of our complex system. In this paper, our main goal is to develop and validate the thermal stability in order to get an idea of the flow of heat around the ASIC in transient and thus address the thermal issues for integrated circuits at the ABDM card. However, we need heat sources simulations for ABDM card to establish its thermal mapping. This led us to perform simulations at each ASIC that will allow us to understand the thermal ABDM map and find real solutions for each one of our complex system that contains 36 ABDM map, taking into account the different layers around ASIC. To do a transient simulation under NISA, we had to build a function of power modulation in time TIMEAMP. The maximum power generated in the ASIC is 0.6 W. We divided the power uniformly in the volume of the ASIC. This power was applied for 5 seconds to visualize the evolution and distribution of heat around the ASIC. The DBC (Dirichlet Boundary conditions) method was applied around the ABDM at 25°C and just after these simulations in NISA tool we will validate them by COMSOL tool, wich is a numerical calculation software for a modular finite element for modeling a wide variety of physical phenomena characterizing a real problem. It will also be a design tool with its ability to handle 3D geometries for complex systems.

Keywords: ABDM, APD, thermal mapping, complex system

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Authors: A. E. El-Henawey, A. A. El-Kouny, M. M. Abd –El-Halim

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Moving target indication (MTI) which is an anti-clutter technique that limits the display of clutter echoes. It uses the radar received information primarily to display moving targets only. The purpose of MTI is to discriminate moving targets from a background of clutter or slowly-moving chaff particles as shown in this paper. Processing system in these radars is so massive and complex; since it is supposed to perform a great amount of processing in very short time, in most radar applications the response of a single canceler is not acceptable since it does not have a wide notch in the stop-band. A double-delay canceler is an MTI delay-line canceler employing the two-delay-line configuration to improve the performance by widening the clutter-rejection notches, as compared with single-delay cancelers. This canceler is also called a double canceler, dual-delay canceler, or three-pulse canceler. In this paper, a double delay line canceler is chosen for study due to its simplicity in both concept and implementation. Discussing the implementation of a simple digital moving target indicator (DMTI) using FPGA which has distinct advantages compared to other application specific integrated circuit (ASIC) for the purposes of this work. The FPGA provides flexibility and stability which are important factors in the radar application.

Keywords: FPGA, MTI, double delay line canceler, Doppler Shift

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Authors: Samai'la Abdullahi

Abstract:

A graph is a pair of two set and so that a graph is a pictorial representation of a system using two basic element nodes and edges. A node is represented by a circle (either hallo shade) and edge is represented by a line segment connecting two nodes together. In this paper, we present a circuit network in the concept of graph theory application and also circuit models of graph are represented in logical connection method were we formulate matrix method of adjacency and incidence of matrix and application of truth table.

Keywords: euler circuit and path, graph representation of circuit networks, representation of graph models, representation of circuit network using logical truth table

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Authors: Debabrata Das

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This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

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Authors: Ararat Khachatryan, Davit Mirzoyan

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In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

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This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

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Authors: Wei Feilong

Abstract:

In this study, an local invariant generalized Houghtransform (LI-GHT) method is proposed for integrated circuit (IC) visual positioning. The original generalized Hough transform (GHT) is robust to external noise; however, it is not suitable for visual positioning of IC chips due to the four-dimensionality (4D) of parameter space which leads to the substantial storage requirement and high computational complexity. The proposed LI-GHT method can reduce the dimensionality of parameter space to 2D thanks to the rotational invariance of local invariant geometric feature and it can estimate the accuracy position and rotation angle of IC chips in real-time under noise and blur influence. The experiment results show that the proposed LI-GHT can estimate position and rotation angle of IC chips with high accuracy and fast speed. The proposed LI-GHT algorithm was implemented in IC visual positioning system of radio frequency identification (RFID) packaging equipment.

Keywords: Integrated Circuit Visual Positioning, Generalized Hough Transform, Local invariant Generalized Hough Transform, ICpacking equipment

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Authors: Wenxuan Li, Lei Li, Jin Li, Yuanhang He

Abstract:

This paper designed a secure chip for IoT communication security integrated with the PUF-based firmware protection scheme. Then, the Xilinx Kintex-7 and STM-32 were used for the prototype verification. Firmware protection worked well on FPGA and embedded platforms. For the ASIC implementation of the PUF module, contact PUF is chosen. The post-processing method and its improvement are analyzed with emphasis. This paper proposed a more efficient post-processing method for contact PUF named SXOR, which has practical value for realizing lightweight security modules in IoT devices. The analysis was carried out under the hypothesis that the contact holes are independent and combine the existing data in the open literature. The post-processing effects of SXOR and XOR are basically the same under the condition that the proposed post-processing circuit occupies only 50.6% of the area of XOR. The average Hamming weight of the PUF output bit sequence obtained by the proposed post-processing method is 0.499735, and the average Hamming weight obtained by the XOR-based post-processing method is 0.499999.

Keywords: PUF, IoT, authentication, secure communication, encryption, XOR

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, M. Hanif M. Nasir

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This paper will discuss how EDA tools are integrated and automated in an Integrated Circuit Design Environment. Some of the problems face in our current environment is that users need to configure manually on the library paths, start-up files and project directories. Certain manual processes that happen between the users and applications can be automated but they must be transparent to the users. For example, the users can run the applications directly after login without knowing the library paths and start-up files locations. The solution to these problems is to automate the processes using standard configuration files which will benefit the users and EDA support. This paper will discuss how the implementation is done to automate the process using scripting languages such as Perl, Tcl, Scheme and Shell Script. These scripting tools are great assets for design engineers to build a robust and powerful design flow and this technique is widely used to integrate all the tools together.

Keywords: EDA tools, Integrated Circuits, scripting, integration, automation

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Authors: Amit Kumar Sinha

Abstract:

A coal preparation plant typically operates with multiple beneficiation circuits to process individual size fractions of coal obtained from mine so that the targeted overall plant efficiency in terms of yield and ash is achieved. Conventional coal beneficiation plant in India or overseas operates generally in two methods of processing; coarse beneficiation with treatment in dense medium cyclones or in baths and fines beneficiation with treatment in flotation cell. This paper seeks to address the proven application of intermediate circuit along with coarse and fines circuit in Jamadoba New Coal Preparation Plant of capacity 2 Mt/y to treat -0.5 mm+0.25 mm size particles in reflux classifier. Previously this size of particles was treated directly in Flotation cell which had operational and metallurgical limitations which will be discussed in brief in this paper. The paper also details test work results performed on the representative samples of TSL coal washeries to determine the top size of intermediate and fines circuit and discusses about the overlapping process of intermediate circuit and how it is process wise suitable to beneficiate misplaced particles from coarse circuit and fines circuit. This paper also compares the separation efficiency (Ep) of various intermediate circuit process equipment and tries to validate the use of reflux classifier over fine coal DMC or spirals. An overview of Modern coal preparation plant treating Indian coal especially Washery Grade IV coal with reference to Jamadoba New Coal Preparation Plant which was commissioned in 2018 with basis of selection of equipment and plant profile, application of reflux classifier in intermediate circuit and process design criteria is also outlined in this paper.

Keywords: intermediate circuit, overlapping process, reflux classifier

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Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

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Authors: John Lachapelle

Abstract:

Introduction: Neural stimulation is increasingly targeted toward treatment of back pain, PTSD, Parkinson’s disease, and for sensory perception. Sensory recording during stimulation is important in order to examine neural response to stimulation. Most neural amplifiers (headstages) focus on noise efficiency factor (NEF). Conversely, neural headstages need to handle artifacts from several sources including power lines, movement (EMG), and neural stimulation itself. In this work a layered approach to artifact rejection is used to reduce corruption of the neural ENG signal by 60dBv, resulting in recovery of sensory signals in rats and primates that would previously not be possible. Methods: The approach combines analog techniques to reduce and handle unwanted signal amplitudes. The methods include optimized (1) sensory electrode placement, (2) amplifier configuration, and (3) artifact blanking when necessary. The techniques together are like concentric moats protecting a castle; only the wanted neural signal can penetrate. There are two conditions in which the headstage operates: unwanted artifact < 50mV, linear operation, and artifact > 50mV, fast-settle gain reduction signal limiting (covered in more detail in a separate paper). Unwanted Signals at the headstage input: Consider: (a) EMG signals are by nature < 10mV. (b) 60 Hz power line signals may be > 50mV with poor electrode cable conditions; with careful routing much of the signal is common to both reference and active electrode and rejected in the differential amplifier with <50mV remaining. (c) An unwanted (to the neural recorder) stimulation signal is attenuated from stimulation to sensory electrode. The voltage seen at the sensory electrode can be modeled Φ_m=I_o/4πσr. For a 1 mA stimulation signal, with 1 cm spacing between electrodes, the signal is <20mV at the headstage. Headstage ASIC design: The front end ASIC design is designed to produce < 1% THD at 50mV input; 50 times higher than typical headstage ASICs, with no increase in noise floor. This requires careful balance of amplifier stages in the headstage ASIC, as well as consideration of the electrodes effect on noise. The ASIC is designed to allow extremely small signal extraction on low impedance (< 10kohm) electrodes with configuration of the headstage ASIC noise floor to < 700nV/rt-Hz. Smaller high impedance electrodes (> 100kohm) are typically located closer to neural sources and transduce higher amplitude signals (> 10uV); the ASIC low-power mode conserves power with 2uV/rt-Hz noise. Findings: The enhanced neural processing ASIC has been compared with a commercial neural recording amplifier IC. Chronically implanted primates at MGH demonstrated the presence of commercial neural amplifier saturation as a result of large environmental artifacts. The enhanced artifact suppression headstage ASIC, in the same setup, was able to recover and process the wanted neural signal separately from the suppressed unwanted artifacts. Separately, the enhanced artifact suppression headstage ASIC was able to separate sensory neural signals from unwanted artifacts in mouse-implanted peripheral intrafascicular electrodes. Conclusion: Optimizing headstage ASICs allow observation of neural signals in the presence of large artifacts that will be present in real-life implanted applications, and are targeted toward human implantation in the DARPA HAPTIX program.

Keywords: ASIC, biosensors, biomedical signal processing, biomedical sensors

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Authors: Wenmin Qu

Abstract:

A capacitance level sensor with a segmented film electrode and a thin-film volume flow sensor with an innovative by-pass sleeve is presented as industrial products for the application in a harsh environment. The working principle of such sensors is well known; however, the traditional sensors show some limitations for certain industrial measurements. The two sensors presented in this paper overcome this limitation and enlarge the application spectrum. The problem is analyzed, and the solution is given. The emphasis of the paper is on developing the problem-solving concepts and the realization of the corresponding measuring circuits. These should give advice and encouragement, how we can still develop electronic measuring products in an almost saturated market.

Keywords: by-pass sleeve, charge transfer circuit, fixed ΔT circuit, harsh environment, industrial application, segmented electrode

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Authors: Ahmed Nouainia, Mohamed Hajji, Taoufik Aguili

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In this paper, an electromagnetic analysis is presented for describing the influence of shielding in a rectangular waveguide. A hybridization based on the method of moments combined to the generalized equivalent circuit MoM-GEC is used to model the problem. This is validated by applying the MoM-GEC hybridization to investigate a diffraction structure. It consists of electromagnetic diffraction by an iris in a rectangular waveguide. Numerical results are shown and discussed and a comparison with FEM and Marcuvitz methods is achieved.

Keywords: method MoM-GEC, waveguide, shielding, equivalent circuit

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Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

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The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

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Authors: Ali Mustafa Elshawesh, Mohamed Abdulali

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The paper presents an approach to dimension circuit switched networks and find the relationship between the parameters of the circuit switched networks on the condition of specific probability of call blocking. Our work is creating a Simulation code based on Erlang (B) formula to draw graphs which show two curves for each graph; one of simulation and the other of calculated. These curves represent the relationships between average number of calls and average call duration with the probability of call blocking. This simulation code facilitates to select the appropriate parameters for circuit switched networks.

Keywords: Erlang B formula, call blocking, telephone system dimension, Markov model, link capacity

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

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This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: boost converter, current sensing, power-on protection, step-up converter, soft-start

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Authors: F. Boudet, V. Galano, D. Gmira, L. Munoz, A. Reina

Abstract:

Commodities pricing needs a specific approach as they are often linked to each other and so are expectedly doing their prices. They are called co-integrated when at least one stationary linear combination exists between them. Though widespread in economic literature, and even if many equilibrium relations and co-movements exist in the economy, this principle of co-movement is not developed in derivatives field. The present study focuses on the following problem: How can the price of a forward agreement on a commodity be simulated, when it is co-integrated with other ones? Theoretical analysis is developed from Gibson-Schwartz model and an analytical solution is given for short maturities contracts and under risk-neutral conditions. The application has been made to crude oil and heating oil energy commodities and result confirms the applicability of proposed method.

Keywords: co-integration, commodities, forward pricing, Gibson-Schwartz

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Authors: Keiju Matsui, Mikio Yasubayashi, Masayoshi Umeno

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Consumption of energy is increasing every year, and yet does not the decline at all. The main energy source is fossil fuels such as petroleum and natural gas. Since it is the finite resources, they will be exhausted someday. Moreover, to make the fossil fuel an energy source causes an environment problem. In such way, one solution of the problems is the solar battery that is remarkable as one of the alternative energies. Under such circumstances, in this paper, we propose a novel maximum power control circuit for photovoltaic power generation system with simple and fast-response operation. In addition to an application to the solar battery, since this control system is possible to operate with simple circuit and fast-response, the polar value control like the maximum or the minimum value tracking for general application could be easily realized.

Keywords: maximum power control, inter-connection, photovoltaic power generation, PI controller, multiplier, exclusive-or, power system

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Authors: Hoda Abugharsa

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In this paper we propose to design a sorter circuit using insertion sorting algorithm. The circuit will be designed using Algorithmic State Machines (ASM) method. That means converting the insertion sorting flowchart into an ASM chart. Then the ASM chart will be used to design the sorter circuit and the control unit.

Keywords: insert sorting algorithm, ASM chart, sorter circuit, state machine, control unit

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Authors: Pedro Luis Ferrer Penalver, Edmundo da Silva Braga

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In this paper, the performance of a simple surge protection for a direct current circuit was simulated. The protection circuit was developed from modified electric macro models of a gas discharge tube and a transient voltage suppressor diode. Moreover, a combination wave generator circuit was used as source of energy surges. The simulations showed that the circuit presented ensures immunity corresponding with test level IV of the IEC 61000-4-5:2014 international standard. The developed circuit can be modified to meet the requirements of any other equipment to be protected. Similarly, the parameters of the combination wave generator can be changed to provide different surge amplitudes.

Keywords: combination wave generator, IEC 61000-4-5, Pspice simulation, surge protection

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Authors: Iyad A. A. Abusahloub

Abstract:

This research aimed to measure the level of perception and application of Integrated Talent Management according to IBM standards, by the upper and middle categories in Palestinian government institutions in Gaza, using a descriptive-analytical method. Using a questionnaire based on the standards of the IBM Institute for Business Value, the researcher added a second section to measure the perception of integrated talent management, the sample was 248 managers. The SPSS package was used for statistical analysis. The results showed that government institutions in Gaza apply Integrated Talent Management according to IBM standards at a medium degree did not exceed 59.8%, there is weakness in the perception of integrated talent management at the level of 53.6%, and there is a strong correlation between (Integrated Talent Management) and (the perception of the integrated talent management) amounted to 92.9%, and 88.9% of the change in the perception of the integrated talent management is by (motivate and develop, deploy and manage, connect and enable, and transform and sustain) talents, and 11.1% is by other factors. Conclusion: This study concluded that the integrated talent management model presented by IBM with its six dimensions is an effective model to reach your awareness and understanding of talent management, especially that it must rely on at least four basic dimensions out of the six dimensions: 1- Stimulating and developing talent. 2- Organizing and managing talent. 3- Connecting with talent and empowering it. 4- Succession and sustainability of talent. Therefore, this study recommends the adoption of the integrated talent management model provided by IBM to any organization across the world, regardless of its specialization or size, to reach talent sustainability.

Keywords: HR, talent, talent management, IBM

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Authors: Arijit Basuray

Abstract:

It is well known that if an electrical insulation system is stressed under high voltage then discharge may occur in various form and if the system is made of composite dielectric having interfaces of materials having different dielectric constant discharge may occur due to gross mismatch of dielectric constant causing intense local field in the interfaces. Here author has studied, firstly, behavior of discharges in gaseous dielectric circuit under AC and DC voltages. A gaseous dielectric circuit is made such that a pair of electrode of typical geometry is used to make the discharges occur under application of AC and DC voltages. Later on, composite insulation system with air gap is also studied. Discharge response of the dielectric circuit is measured across a typically designed impedance. The time evolution of the discharge characteristics showed some interesting chaotic behavior. Author here proposed some analysis of such behavior of the discharge pattern and discussed about the possibility of presence of such discharge circuit in lumped electric circuit.

Keywords: electrical insulation system, EIS, composite dielectric, discharge, chaos

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Authors: Shengqi Yu, Jinwei Zhao

Abstract:

This paper presents a kind of analog circuit based temperature control system, which is mainly composed by threshold control signal circuit, synchronization signal circuit and trigger pulse circuit. Firstly, the temperature feedback signal function is realized by temperature sensor TS503F3950E. Secondly, the main control circuit forms the cycle controlled pulse signal to control the thyristor switching model. Finally two reverse paralleled thyristors regulate the output power by their switching state. In the consequence, this is a modernized and energy-saving domestic electric heating system.

Keywords: time base circuit, automatic control, zero-crossing trigger, temperature control

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Authors: Florian Kleber, Martin Kampel

Abstract:

The increasing demand of gallium, indium and rare-earth elements for the production of electronics, e.g. solid state-lighting, photovoltaics, integrated circuits, and liquid crystal displays, will exceed the world-wide supply according to current forecasts. Recycling systems to reclaim these materials are not yet in place, which challenges the sustainability of these technologies. This paper proposes a multispectral imaging system as a basis for a vision based recognition system for valuable components of electronics waste. Multispectral images intend to enhance the contrast of images of printed circuit boards (single components, as well as labels) for further analysis, such as optical character recognition and entire printed circuit board recognition. The results show that a higher contrast is achieved in the near infrared compared to ultraviolet and visible light.

Keywords: electronics waste, multispectral imaging, printed circuit boards, rare-earth elements

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Authors: Kaiwen Zheng, Wanting Zhou, Nan Tang, Lei Li, Yuanhang He

Abstract:

The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs.

Keywords: hardware trojans, physical properties, machine learning, hardware security

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