Search results for: flip flops

Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: Parisi L., Hamili D., Azlan N.

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The aim of this study was to design and simulate a particular type of Asynchronous State Machine (ASM), namely a ‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz. The design task involved two main stages: firstly, designing a 4-bit binary counter using J-K flip flops as the timing signal and subsequently, attaining the digital logic by deploying ASM design process. The TLC was designed such that it showed a sequence of three different colours, i.e. red, yellow and green, corresponding to set thresholds by deploying the least number of AND, OR and NOT gates possible. The software Multisim was deployed to design such circuit and simulate it for circuit troubleshooting in order for it to display the output sequence of the three different colours on the traffic light in the correct order. A clock signal, an asynchronous 4-bit binary counter that was designed through the use of J-K flip flops along with an ASM were used to complete this sequence, which was programmed to be repeated indefinitely. Eventually, the circuit was debugged and optimized, thus displaying the correct waveforms of the three outputs through the logic analyzer. However, hazards occurred when the frequency was increased to 10 MHz. This was attributed to delays in the feedback being too high.

Keywords: asynchronous state machine, traffic light controller, circuit design, digital electronics

Procedia PDF Downloads 402

Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

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This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: methodology, flip chip, bump cell, LEF, astro, calibre, SCHEME, TCL

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

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A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: Majid Galoie, Khodadad Safavi, Abdolreza Karami Nejad, Reza Roshan

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Scour downstream of a flip bucket in a plunge pool is caused by impingement of water jet force. In order to reduce this force and consequently reduce scour hole depth, flip buckets may equip by dents. The minimum scour hole depth might be occurred by optimization of dents (number, shape, placement) on flip buckets. In this study, a comprehensive physical model has been developed and various options for dents have been investigated. The experimental data for each dent option such as scour hole depth, angle of impingement jet, piezometric pressure in tail-water and jet trajectory have been measured for various discharges. Finally, the best option can be found by analysis of the experimental results which has been expressed in this paper.

Keywords: scouring process, plunge pool, scour hole depth, physical model, flip bucket

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: K. D. Chandrasekhar, H. C. Wu, D. J. Hsieh, B. J. Song, J. -Y. Lin, J. L. Her, L. Z. Deng, M. Gooch, C. W. Chu, H. D. Yang

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Stress-mediated coupling of electrical and magnetic dipoles in a single phase multiferroic is rare. Pb₂MnO₄ belong to multi-piezo crystal class with the space group P⁻42₁

Keywords: multiferroic, multipiezo, Pb₂MnO₄, spin-flip

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Authors: Vishal Pareek, Shubham Gupta, Sushil Chandra Jain

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With increasing high-speed computation demand the power consumption, heat dissipation and chip size issues are posing challenges for logic design with conventional technologies. Recovery of bit loss and bit errors is other issues that require reversibility and fault tolerance in the computation. The reversible computing is emerging as an alternative to conventional technologies to overcome the above problems and helpful in a diverse area such as low-power design, nanotechnology, quantum computing. Bit loss issue can be solved through unique input-output mapping which require reversibility and bit error issue require the capability of fault tolerance in design. In order to incorporate reversibility a number of combinational reversible logic based circuits have been developed. However, very few sequential reversible circuits have been reported in the literature. To make the circuit fault tolerant, a number of fault model and test approaches have been proposed for reversible logic. In this paper, we have attempted to incorporate fault tolerance in sequential reversible building blocks such as D flip-flop, T flip-flop, JK flip-flop, R-S flip-flop, Master-Slave D flip-flop, and double edge triggered D flip-flop by making them parity preserving. The importance of this proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault and single bit fault. In our opinion our design of reversible building blocks is superior to existing designs in term of quantum cost, hardware complexity, constant input, garbage output, number of gates and design of online testable D flip-flop have been proposed for the first time. We hope our work can be extended for building complex reversible sequential circuits.

Keywords: parity preserving gate, quantum computing, fault tolerance, flip-flop, sequential reversible logic

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Authors: Rajesh Mehra

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In this paper an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with MATLAB and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications.

Keywords: butterworth, DSP, IIR, MAC, FPGA

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Authors: Rajesh Mehra, Bharti Thakur

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In this paper, an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with Matlab and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications.

Keywords: Butterworth filter, DSP, IIR, MAC, FPGA

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Authors: Anil Kawan, Soon Jae Yu, Jong Min Park

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GaN-based 365 nm wavelength ultraviolet (UV) light emitting diodes (LED) have various applications: curing, molding, purification, deodorization, and disinfection etc. However, their usage is limited by very low output power, because of the light absorption in the GaN layers. In this study, we demonstrate a method utilizing removal of 365 nm absorption layer buffer GaN and thinning the n-type GaN so as to improve the light extraction efficiency of the GaN-based 365 nm UV LED. The UV flip chip LEDs of chip size 1.3 mm x 1.3 mm were fabricated using GaN epilayers on a sapphire substrate. Via-hole n-type contacts and highly reflective Ag metal were used for efficient light extraction. LED wafer was aligned and bonded to AlN carrier wafer. To improve the extraction efficiency of the flip chip LED, sapphire substrate and absorption layer buffer GaN were removed by using laser lift-off and dry etching, respectively. To further increase the extraction efficiency of the LED, exposed n-type GaN thickness was reduced by using inductively coupled plasma etching.

Keywords: extraction efficiency, light emitting diodes, n-GaN thinning, ultraviolet

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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Authors: Huang Bai-Cheng

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When deploying the Oriented Fast and Rotated Binary Robust Independent Elementary Feature (BRIEF) (ORB) extraction algorithm on field-programmable gate arrays (FPGA), the access of global storage for 31×31 pixel patches of the features has become the bottleneck of the system efficiency. Therefore, a feature zone strategy has been proposed. Zones are searched as features are detected. Pixels around the feature zones are extracted from global memory and distributed into patches corresponding to feature coordinates. The proposed FPGA structure is targeted on a Xilinx FPGA development board of Zynq UltraScale+ series, and multiple datasets are tested. Compared with the streaming pixel patch extraction method, the proposed architecture obtains at least two times acceleration consuming extra 3.82% Flip-Flops (FFs) and 7.78% Look-Up Tables (LUTs). Compared with the non-streaming one, the proposed architecture saves 22.3% LUT and 1.82% FF, causing a latency of only 0.2ms and a drop in frame rate for 1. Compared with the related works, the proposed strategy and hardware architecture have the superiority of keeping a balance between FPGA resources and performance.

Keywords: feature extraction, real-time, ORB, FPGA implementation

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Authors: Dipti Parida, Atasi Mohanty

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The focus of this research is to examine the interaction effect of flipped teaching and traditional teaching mode across two different medium (English and Odia) of instructional groups. Both Science and History subjects were taken to be taught in the Class- VIII in two different instructional mode/s. In total, 180 students of Class-VIII of both Odia and English medium schools were taken as the samples of this study; 90 participants (each group) were from both English and Odia medium schools ; 45 participants of each of these two groups were again assigned either to flip or traditional teaching method. We have two independent variables and each independent variable with two levels. Medium and mode of instruction are the two independent variables. Medium of instruction has two levels of Odia medium and English medium groups. The mode of instruction has also two levels of flip and traditional teaching method. Here we get 4 different groups, such as Odia medium students with traditional mode of teaching (O.M.T), Odia medium students with flipped mode of teaching (O.M.F), English medium students with traditional mode of teaching (E.M.T) and English medium students with flipped mode of teaching (E.M.F). Before the instructional administration, these four groups were given a test on the concerned topic to be taught. Based on this result, a one-way ANOVA was computed and the obtained result showed that these four groups don’t differ significantly from each other at the beginning. Then they were taught the concerned topic either in traditional or flip mode of teaching method. After that a 2×2×2 repeated measures ANOVA was done to analyze the group differences as well as the learning outcome before and after the teaching. The result table also shows that in post-test the learning outcome is highest in case of English medium students with flip mode of instruction. From the statistical analysis it is clear that the flipped mode of teaching is as effective for Odia medium students as it is for English medium students.

Keywords: medium of instruction, mode of instruction, test mode, vernacular medium

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Authors: Lana Horvat Dmitrović

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The main purpose of this paper is to study the box dimension as fractal property of bifurcations of discrete dynamical systems in higher dimensions. The paper contains the fractal analysis of the orbits near the hyperbolic and non-hyperbolic fixed points in discrete dynamical systems. It is already known that in one-dimensional case the orbit near the hyperbolic fixed point has the box dimension equal to zero. On the other hand, the orbit near the non-hyperbolic fixed point has strictly positive box dimension which is connected to the non-degeneracy condition of certain bifurcation. One of the main results in this paper is the generalisation of results about box dimension near the hyperbolic and non-hyperbolic fixed points to higher dimensions. In the process of determining box dimension, the restriction of systems to stable, unstable and center manifolds, Lipschitz property of box dimension and the notion of projective box dimension are used. The analysis of the bifurcations in higher dimensions with one multiplier on the unit circle is done by using the normal forms on one-dimensional center manifolds. This specific change in box dimension of an orbit at the moment of bifurcation has already been explored for some bifurcations in one and two dimensions. It was shown that specific values of box dimension are connected to appropriate bifurcations such as fold, flip, cusp or Neimark-Sacker bifurcation. This paper further explores this connection of box dimension as fractal property to some specific bifurcations in higher dimensions, such as fold-flip and flip-Neimark-Sacker. Furthermore, the application of the results to the unit time map of continuous dynamical system near hyperbolic and non-hyperbolic singularities is presented. In that way, box dimensions which are specific for certain bifurcations of continuous systems can be obtained. The approach to bifurcation analysis by using the box dimension as specific fractal property of orbits can lead to better understanding of bifurcation phenomenon. It could also be useful in detecting the existence or nonexistence of bifurcations of discrete and continuous dynamical systems.

Keywords: bifurcation, box dimension, invariant manifold, orbit near fixed point

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Authors: Edmond Jaro Malihan

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This study aimed to develop and propose Project Financial Literacy Information Program (FLIP) for the Schools Division of Quezon to improve the financial management skills of Supreme Student Government (SSG) officers across different school sizes. This employed a descriptive research design covering the participation of 424 selected SSG officers using purposive sampling procedures from the SDO-Quezon. The consultation was held with DepEd officials, budget officers, and financial advisors to validate the design of the self-made questionnaires in which the computed mean was verbally interpreted using the four-point Likert scale. The data gathered were presented and analyzed using weighted arithmetic mean and ANOVA test. Based on the findings, generally, SSG officers in the SDO-Quezon possess high financial management skills in terms of budget preparation, resource mobilization, and auditing and evaluation. The size of schools has no significant difference and does not contribute to the financial management skills of SSG officers, which they apply in implementing their mandated programs, projects, and activities (PPAs). The Project Financial Literacy Information Program (FLIP) was developed considering their general level of financial management skills and the launched PPAs by the organization. The project covered the suggested training program vital in conducting the Virtual Division Training on Financial Management Skills of the SSG officers.

Keywords: financial management skills, SSG officers, school size, financial literacy information program

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Authors: Hamid Yasinian

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Random epistemologies and hash tables have garnered minimal interest from both security experts and experts in the last several years. In fact, few information theorists would disagree with the evaluation of expert systems. In our research, we discover how flip-flop gates can be applied to the study of superpages. Though such a hypothesis at first glance seems perverse, it is derived from known results.

Keywords: synthesis, multi-processors, interactive model, moor’s law

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Authors: Evan Lowhorn, Rocio Alba-Flores

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The purpose of this work is to develop a method for classifying hand signals and using the output in a drone control algorithm. To achieve this, methods based on Convolutional Neural Networks (CNN) were applied. CNN's are a subset of deep learning, which allows grid-like inputs to be processed and passed through a neural network to be trained for classification. This type of neural network allows for classification via imaging, which is less intrusive than previous methods using biosensors, such as EMG sensors. Classification CNN's operate purely from the pixel values in an image; therefore they can be used without additional exteroceptive sensors. A development bench was constructed using a desktop computer connected to a high-definition webcam mounted on a scissor arm. This allowed the camera to be pointed downwards at the desk to provide a constant solid background for the dataset and a clear detection area for the user. A MATLAB script was created to automate dataset image capture at the development bench and save the images to the desktop. This allowed the user to create their own dataset of 12,000 images within three hours. These images were evenly distributed among seven classes. The defined classes include forward, backward, left, right, idle, and land. The drone has a popular flip function which was also included as an additional class. To simplify control, the corresponding hand signals chosen were the numerical hand signs for one through five for movements, a fist for land, and the universal “ok” sign for the flip command. Transfer learning with PyTorch (Python) was performed using a pre-trained 18-layer residual learning network (ResNet-18) to retrain the network for custom classification. An algorithm was created to interpret the classification and send encoded messages to a Ryze Tello drone over its 2.4 GHz Wi-Fi connection. The drone’s movements were performed in half-meter distance increments at a constant speed. When combined with the drone control algorithm, the classification performed as desired with negligible latency when compared to the delay in the drone’s movement commands.

Keywords: classification, computer vision, convolutional neural networks, drone control

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Authors: Eleni Akritopoulou, Katerina Topouzoglou

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The last 20 years marine debris has been identified as one of the main marine pollution sources caused by anthropogenic activities. Plastics has reached the farthest marine areas of the planet affecting all marine trophic levels including the, recently discovered, amphipoda Eurythenes plasticus inhabiting Mariana Trench to large cetaceans, marine reptiles and sea birds causing immunodeficiency disorders, deteriorating health and death overtime. For the time period 2016-20, in the framework of the national initiative ‘Keep Aegean Blue”, All for Blue team has been collecting marine debris (coastline and underwater) following a modified in situ MEDSEALITTER monitoring protocol from eight Greek islands. After collection, marine debris was weighted, sorted and categorised according to material; plastic (PL), glass (G), metal (M), wood (W), rubber (R), cloth (CL), paper (P), mixed (MX). The goal of the project included the documentation of marine debris sources, human trends, waste management and public marine environmental awareness. Waste management was focused on plastics recycling and utilisation into daily useful products. This research is focused on the island of Mykonos due to its continuous touristic activity and lack of scientific information. In overall, a field work area of 1.832.856 m2 was cleaned up yielding 5092 kg of marine debris. The preliminary results indicated PL as main source of marine debris (62,8%) followed by M (15,5%), GL (13,2%) and MX (2,8%). Main items found were fishing tools (lines, nets), disposable cutlery, cups and straws, cigarette butts, flip flops and other items like plastic boat compartments. In collaboration with a local company for plastic management and the Circular Economy and Eco Innovation Institute (Sweden), all plastic debris was recycled. Granulation process was applied transforming plastic into building materials used for refugees’ houses, litter bins bought by municipalities and schools and, other items like shower components. In terms of volunteering and attendance in public awareness seminars, there was a raise of interest by 63% from different age ranges and professions. Regardless, the research being fairly new for Mykonos island and logistics issues potentially affected systemic sampling, it appeared that plastic debris is the main littering source attributed, possibly to the intense touristic activity of the island all year around. However, marine environmental awareness activities were pointed out to be an effective tool in forming public perception against marine debris and, alter the daily habits of local society. Since the beginning of this project, three new local environmental teams were formed against marine pollution supported by the local authorities and stakeholders. The continuous need and request for the production of items made by recycled marine debris appeared to be beneficial socio-economically to the local community and actions are taken to expand the project nationally. Finally, as an ongoing project and whilst, new scientific information is collected, further funding and research is needed.

Keywords: Greece, marine debris, marine environmental awareness, Mykonos island, plastics debris, plastic granulation, recycled plastic, tourism, waste management

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Authors: Jumin Zhao, Na Li, Dengao Li, Yujuan Yan

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As the rapid rise of the networking industry, the shortage of Internet of Things (IoT) talented people greatly stimulates the majority of colleges to speed up the pace of professional networking reform. Caused by the construction of the original specialty, many problems appear such as the vague specialty, the mixed theoretical, the poor practical ability and the different goal. To solve the issues above, we build a ‘theory-practice-theory-improvement’ four-step model of school-enterprise integration of personnel training. Besides, we integrate the advanced teaching philosophy: flip class and Mu class, making IoT teaching more professional and the ability of students more comprehensive.

Keywords: IoT, theory-practice-theory-promotion, major construction, school-enterprise cooperation

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Authors: Majid Galoie, Khodadad Safavi, Abdolreza Karami Nejad, Reza Roshan

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In this study, a comprehensive scouring model has been developed in order to evaluate the accuracy of various empirical relationships which were suggested for prediction of scour hole depth in plunge pools by Martins, Mason, Chian and Veronese. For this reason, scour hole depths caused by free falling jets from a flip bucket to a plunge pool were investigated. In this study various discharges, angles, scouring times, etc. have been considered. The final results demonstrated that the all mentioned empirical formulas, except Mason formula, were reasonably agreement with the experimental data.

Keywords: scour hole depth, plunge pool, physical model, reliability assessment

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Authors: Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu

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This paper proposed a high resolution Vernier Delay Line (VDL) measurement circuit with coarse and fine detection mechanism, which improved the trade-off problem between high resolution and less delay cells in traditional VDL circuits. And the measuring time of proposed measurement circuit is also under the high resolution requests. At first, the testing range of input signal which proposed high resolution delay line is detected by coarse detection VDL. Moreover, the delayed input signal is transmitted to fine detection VDL for measuring value with better accuracy. This paper is implemented at 0.18μm process, operating frequency is 100 MHz, and the resolution achieved 2.0 ps with only 16-stage delay cells. The test range is 170ps wide, and 17% stages saved compare with traditional single delay line circuit.

Keywords: vernier delay line, D-type flip-flop, DFF, metastable phenomenon

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Authors: Debjit Dutta, P. Roy, O. Panella

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In recent years, non Hermitian interaction in non relativistic as well as relativistic quantum mechanics have been examined from various aspect. We can observe interesting fact that for such systems a class of potentials, namely the PT symmetric and η-pseudo Hermitian admit real eigenvalues despite being non Hermitian and analogues of those system have been experimentally verified. Point to be noted that relativistic non Hermitian (PT symmetric) interactions can be realized in optical structures and also there exists photonic realization of the (1 + 1) dimensional Dirac oscillator. We have thoroughly studied generalized Dirac oscillators with non Hermitian interactions in (1 + 1) dimensions. To be more specific, we have examined η pseudo Hermitian interactions within the framework of generalized Dirac oscillator in (1 + 1) dimensions. In particular, we have obtained a class of interactions which are η-pseudo Hermitian and the metric operator η could have been also found explicitly. It is possible to have exact solutions of the generalized Dirac oscillator for some choices of the interactions. Subsequently we have employed the mapping between the generalized Dirac oscillator and the Jaynes Cummings (JC) model by spin flip to obtain a class of exactly solvable non Hermitian JC as well as anti Jaynes Cummings (AJC) type models.

Keywords: Dirac oscillator, non-Hermitian quantum system, Hermitian, relativistic

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Authors: Chukwukelue Uzodinma Umenyilorah

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The advent of the New Media as enabled by information and communication technology from the 19th through the 21st century has no doubt taken its toll on all fronts of human existence; especially in Africa. Apart from shortening the distance between all parts of the world, technology and the new media has also succeeded in making the world a global village. Hence, it is now easy to relay live audio and visual signals across the length and breadth of the world in real time. People now contract and execute businesses across countries, conferences are held and ideas are shared with a simple push of a button. Likewise, political leaders and diplomats are now just a click away from reaching those important decisions that take their country’s fortunes to the next level. On the flip side, ICT and the New Media have also contributed in no small measure in aiding global terrorism and general insecurity around the world. More interesting is the fact that as developing economies, African countries have massively embraced the information technology and this has helped them in keeping up with the trends in the polity of other model democracies around the world. This paper is therefore designed to determine the how much effect ICT and the New Media has exerted on the economic, social and political lives of African. Nigeria shall be used as a case in point for the purpose of this paper.

Keywords: Africa, ICT, new media, Nigeria

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Authors: Santiago Moll Lopez, Erica Vega Fleitas, Dolors Rosello Ferragud, Luis Manuel Sanchez Ruiz, Jose Antonio Moraño Fernandez

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Game-based learning (GBL) is becoming popular in education. Learning through games offers students a motivating experience related to the social aspect of games. Among the significant positive outcomes are promoting positive emotions and collaboration, improving the assimilation of concepts, and creating an attractive and dynamic environment standout. This work presents a study of the design and implementation of games created with RPG Maker MZ software with a Sci-Fi storytelling environment for developing specific and transversal skills in a Mathematics subject at the Beng in Aerospace Engineering. Games were applied during regular classes and as a part of a Flip-Teaching methodology to increase the motivation and the assimilation of mathematical concepts in an engaging way. The key features of the games were the introduction of avatar design and the promotion of collaboration among students. Students' opinions and grades obtained in the activities and exams showed increased motivation and a significant improvement in their performance compared with other groups or past students' performances.

Keywords: game-based learning, rol games, mathematics, science fiction

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Authors: Sopheak Sorn, Kwok Yip Szeto

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Reliability is one of the important measures of how well the system meets its design objective, and mathematically is the probability that a complex system will perform satisfactorily. When the system is described by a network of N components (nodes) and their L connection (links), the reliability of the system becomes a network design problem that is an NP-hard combinatorial optimization problem. In this paper, we address the network design problem for a random point set’s pattern in two dimensions. We make use of a Voronoi construction with each cell containing exactly one point in the point pattern and compute the reliability of the Voronoi’s dual, i.e. the Delaunay graph. We further investigate the communicability of the Delaunay network. We find that there is a positive correlation and a negative correlation between the homogeneity of a Delaunay's degree distribution with its reliability and its communicability respectively. Based on the correlations, we alter the communicability and the reliability by performing random edge flips, which preserve the number of links and nodes in the network but can increase the communicability in a Delaunay network at the cost of its reliability. This transformation is later used to optimize a Delaunay network with the optimum geometric mean between communicability and reliability. We also discuss the importance of the edge flips in the evolution of real soap froth in two dimensions.

Keywords: Communicability, Delaunay triangulation, Edge Flip, Reliability, Two dimensional network, Voronio

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Authors: Liu Yi Hui, Lin Yu Fang, Chiu Fan Yun

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In preparation for the coming super-aged society in Taiwan, the Ministry of Labor announced the Middle-aged and Elderly Employment Promotion Act in 2019, dedicating a chapter to expressly prohibiting age discrimination. This study aimed to enhance understanding of workplace ageism by collecting data through in-depth interviews. The findings can be summarized as follows: 1. Elderly employment in Taiwan and its three underlying motivations: Mainly in economic, social, and psychological needs. Economically, elders opt to continue working beyond the traditional retirement age because of financial shocks, a lack of financial planning, and being the breadwinner of the family. Socially and psychologically, they continue working to have a more diversified retirement life and find a new purpose in life. 2. Ageism on the re-employment of elders: On the ground, senior workers may face the age-based stereotype that their work performance is inferior and a broader social environment that is ostensibly friendly but essentially hostile. 3. Possible ways to facilitate elderly employment in terms of empowerment: By developing and empowering seniors with new skills or abilities for re-employment and strengthening their problem-solving skills in the face of new things through training programs, we can not only build the confidence and substantial abilities of senior workers in the workplace but also flip the social stereotype about age.

Keywords: senior-friendly workplaces, elderly employment, empowerment, ageism

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Authors: Zikora K. G. Anyaegbunam, Annabel A. Nnawuihe, Ngozi J. Anyaegbunam, Emmanuel A. Eze

Abstract:

The discovery and production of new antibiotics is unavoidable in the fight against drug-resistant bacteria. However, this is only part of the problem; we have never really had medications that could completely eradicate an infection. All pathogens create a limited number of dormant persister cells that are resistant to antibiotic treatment. When the concentration of antibiotics decreases, surviving persisters repopulate the population, resulting in a recurrent chronic infection. Bacterial populations have an alternative survival strategy to withstand harsh conditions or antibiotic exposure, in addition to the well-known methods of antibiotic resistance and biofilm formation. Persister cells are a limited subset of transiently antibiotic-tolerant phenotypic variations capable of surviving high-dose antibiotic therapy. Persisters that flip back to a normal phenotype can restart growth when antibiotic pressure drops, assuring the bacterial population's survival. Persister cells have been found in every major pathogen, and they play a role in antibiotic tolerance in biofilms as well as the recalcitrance of chronic infections. Persister cells has been implicated to play a role in the establishment of antibiotic resistance, according to growing research. Thusthe need to basically elucidate the biology of persisters and how they are linked to antibiotic resistance, and as well it's link to diseases.

Keywords: persister cells, phenotypic variations, repopulation, mobile genetic transfers, antibiotic resistance

Procedia PDF Downloads 175

Authors: D. Li

Abstract:

Optical thin films are used in a wide variety of optical components and there are many software tools programmed for advancing multilayer thin film design. The available software packages for designing the thin film structure may not provide optimum designs. Normally, almost all current software programs obtain their final designs either from optimizing a starting guess or by technique, which may or may not involve a pseudorandom process, that give different answers every time, depending upon the initial conditions. With the increasing power of personal computers, functional methods in optimization and synthesis of optical multilayer systems have been developed such as DGL Optimization, Simulated Annealing, Genetic Algorithms, Needle Optimization, Inductive Optimization and Flip-Flop Optimization. Among these, DGL Optimization has proved its efficiency in optical thin film designs. The application of the DGL optimization technique to the design of optical coating is presented. A DGL optimization technique is provided, and its main features are discussed. Guidelines on the application of the DGL optimization technique to various types of design problems are given. The innovative global optimization strategies used in a software tool, OnlyFilm, to optimize multilayer thin film designs through different filter designs are outlined. OnlyFilm is a powerful, versatile, and user-friendly thin film software on the market, which combines optimization and synthesis design capabilities with powerful analytical tools for optical thin film designers. It is also the only thin film design software that offers a true global optimization function.

Keywords: optical coatings, optimization, design software, thin film design

Procedia PDF Downloads 283

Authors: Derya Yucel, Nigar Angın, Dürdane Mart, Meltem Turkeri, Volkan Catalkaya, Celal Yucel

Abstract:

Chickpea (Cicer arietinum L.) with high protein content is a vital food, especially in under-developed and developing countries for the people who do not consume enough meat due to low-income level. The objective of the proposed study is to evaluate growing, yield and yield components of chickpea genotypes under Mediterranean condition so determine tolerance of chickpea genotypes against drought and heat stress. For this purpose, a total of 34 chickpea genotypes were used as material. The experiment was conducted according to factorial randomized complete block design with 3 reps at the Eastern Mediterranean Research Institute, Adana, TURKEY for 2014-15 growing season under three different growing conditions (Winter sowing, irrigated-late sowing and non-irrigated- late sowing). According to results of this experiment, vegetative period, flowering time, poding time, maturity time, plant height, height of first pod, seed yield and 100 seed weight were ranged between 68.33 to 78.77 days, 94.22 to 85.00 days, 94.11 to 106.44 days, 198.56 to 214.44 days, 37.18 to 64.89 cm, 18.33 to 34.83 cm, 417.1 to 1746.4 kg/ha and 14.02 to 45.02 g, respectively. Among the chickpea genotypes, the Aksu, Arda, Çakır, F4 09 (X 05 TH 21-16189), FLIP 03-108 were least affected by drought and heat stress. Therefore, these genotypes can be used as sources of drought and heat tolerance in further breeding programme for evolving the drought and heat tolerant genotypes in chickpea.

Keywords: chickpea, drought stress, heat stress, yield

Procedia PDF Downloads 190