Search results for: CMOS (complementary metal oxide semiconductor)

Authors: J. S. Kim

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This paper presents a 0.13-µm Complementary Metal-Oxide Semiconductor (CMOS) vector modulator for beamforming system. The vector modulator features a 360° phase and gain range of -10 dB to 10 dB with a root mean square phase and amplitude error of only 2.2° and 0.45 dB, respectively. These features make it a suitable for wireless backhaul system in the 5 GHz industrial, scientific, and medical (ISM) bands. It draws a current of 20.4 mA from a 1.2 V supply. The total chip size is 1.87x1.34 mm².

Keywords: CMOS, vector modulator, beamforming, 802.11ac

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Authors: Nissar Mohammad Karim, Norhayati Soin

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To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, Sol-Gel, precursor aging, aging

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Authors: Nissar Mohammad Karim, Norhayati Soin

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To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, sol-gel, precursor ageing, metallurgical and materials engineering

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

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This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS process sensor, PVT sensor, threshold extractor circuit, Vth extractor circuit

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Authors: Min-Hao Wang, Shih-Chih Chen

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Recently, the merits such as simple structure, low power consumption, and compatibility with complementary metal oxide semiconductor (CMOS) process give an advantage of resistive random access memory (RRAM) as a promising candidate for the next generation memory， hafnium dioxide (HfO2) has been widely studied as an oxide layer material, but the use of copper (Cu) as both top and bottom electrodes has rarely been studied. In this study, radio frequency sputtering was used to deposit the intermediate layer HfO₂, and electron beam evaporation was used. For the upper and lower electrodes (cu), using different AR: O ratios, we found that the control of the metal filament will make the filament widely distributed, causing the current to rise to the limit current during Reset. However, if the flow ratio is controlled well, the ON/OFF ratio can reach 104, and the set voltage is controlled below 3v.

Keywords: RRAM, metal filament, HfO₂, Cu electrode

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Authors: Se-Mi Lim, Won-Jae Jung, Jin-Sup Kim, Jun-Seok Park, Hyung-Il Chae

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This paper presents a current-mode vertical hall device (VHD) structure using metal layers in a CMOS process. The proposed metal layer based vertical hall device (MLVHD) utilizes vertical connection among metal layers (from M1 to the top metal) to facilitate hall effect. The vertical metal structure unit flows a bias current Ibias from top to bottom, and an external magnetic field changes the current distribution by Lorentz force. The asymmetric current distribution can be detected by two differential-mode current outputs on each side at the bottom (M1), and each output sinks Ibias/2 ± Ihall. A single vertical metal structure generates only a small amount of hall effect of Ihall due to the short length from M1 to the top metal as well as the low conductivity of the metal, and a series connection between thousands of vertical structure units can solve the problem by providing NxIhall. The series connection between two units is another vertical metal structure flowing current in the opposite direction, and generates negative hall effect. To mitigate the negative hall effect from the series connection, the differential current outputs at the bottom (M1) from one unit merges on the top metal level of the other unit. The proposed MLVHD is simulated in a 3-dimensional model simulator in COMSOL Multiphysics, with 0.35 μm CMOS process parameters. The simulated MLVHD unit size is (W) 10 μm × (L) 6 μm × (D) 10 μm. In this paper, we use an MLVHD with 10 units; the overall hall device size is (W) 10 μm × (L)78 μm × (D) 10 μm. The COMSOL simulation result is as following: the maximum hall current is approximately 2 μA with a 12 μA bias current and 100mT magnetic field; This work was supported by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIP) (No.R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device).

Keywords: CMOS, vertical hall device, current mode, COMSOL

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: T. Angeline Priyanka, R. Ganesan

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Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Su Yin Chiam, Qing Xin Zhang, Jaehoon Chung

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Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have obtained increased attention in the biosensor community because CMOS technology provides cost-effective and high-performance signal processing at a mass-production level. In order to supply biological samples and reagents effectively to the sensing elements, there are increasing demands for seamless integration of microfluidic components on the fabricated CMOS wafers by post-processing. Although the PDMS microfluidic channels replicated from separately prepared silicon mold can be typically aligned and bonded onto the CMOS wafers, it remains challenging owing the inherently limited aligning accuracy ( > ± 10 μm) between the two layers. Here we present a new post-processing method to create three-dimensional microfluidic components using two different polarities of photoresists, an epoxy-based negative SU-8 photoresist and positive SPR220-7 photoresist. The positive photoresist serves as a sacrificial layer and the negative photoresist was utilized as a structural material to generate three-dimensional structures. Because both photoresists are patterned using a standard photolithography technology, the dimensions of the structures can be effectively controlled as well as the alignment accuracy, moreover, is dramatically improved (< ± 2 μm) and appropriately can be adopted as an alternative post-processing method. To validate the proposed processing method, we applied this technique to build cell-trapping structures. The SU8 photoresist was mainly used to generate structures and the SPR photoresist was used as a sacrificial layer to generate sub-channel in the SU8, allowing fluid to pass through. The sub-channel generated by etching the sacrificial layer works as a cell-capturing site. The well-controlled dimensions enabled single-cell capturing on each site and high-accuracy alignment made cells trapped exactly on the sensing units of CMOS biosensors.

Keywords: SU-8, microfluidic, MEMS, microfabrication

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Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

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In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

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Authors: Davit Mirzoyan, Ararat Khachatryan

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A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: detection, monitoring, process corner, process variation

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

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Authors: Zhipeng Dong, Jing Guo

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Graphene-semiconductor contacts have been extensively studied recently, both as a stand-alone diode device for potential applications in photodetectors and solar cells, and as a building block to vertical transistors. Graphene is a two-dimensional nanomaterial with vanishing density-of-states at the Dirac point, which differs from conventional metal. In this work, image-charge-induced barrier lowering (BL) in graphene-semiconductor contacts is studied and compared to that in metal Schottky contacts. The results show that despite of being a semimetal with vanishing density-of-states at the Dirac point, the image-charge-induced BL is significant. The BL value can be over 50% of that of metal contacts even in an intrinsic graphene contacted to an organic semiconductor, and it increases as the graphene doping increases. The dependences of the BL on the electric field and semiconductor dielectric constant are examined, and an empirical expression for estimating the image-charge-induced BL in graphene-semiconductor contacts is provided.

Keywords: graphene, semiconductor materials, schottky barrier, image charge, contacts

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Authors: Marcin Tadla, Robert Rusinek, Jolanta Wawrzyniak, Marzena Gawrysiak-Witulska, Agnieszka Nawrocka, Marek Gancarz

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Rapeseeds were evaluated and classified by the static-headspace sampling method using electronic noses during the 25 days spoilage period. The Cyranose 320 comprising 32 polymer-composite sensors and VCA (Volatile Compound Analyzer - made in Institute of Agrophysics) built of 8 metal-oxide semiconductor (MOS) sensors were used to obtain sensor response (∆R/R). Each sample of spoiled material was divided into three parts and the degree of spoilage was measured four ways: determination of ergosterol content (ERG), colony forming units (CFU) and measurement with both e-noses. The study showed that both devices responsive to changes in the fungal microflora. Cyranose and VCA registered the change of domination microflora of fungi. After 7 days of storage, typical fungi for soil disappeared and appeared typical for storeroom was observed. In both cases, response ∆R/R decreased to the end of experiment, while ERG and JTK increased. The research was supported by the National Centre for Research and Development (NCBR), Grant No. PBS2/A8/22/2013.

Keywords: electronic nose, fungal microflora, metal-oxide sensor, polymer-composite sensors

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Authors: Pejman Hosseinioun, Abolghasem Ghasempour, Elham Gholami, Hamed Sarbazi

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Considering the development in global semiconductor technology, it is anticipated that gadgets such as diodes and resonant transistor tunnels (RTD/RTT), Single electron transistors (SET) and quantum cellular automata (QCA) will substitute CMOS (Complementary Metallic Oxide Semiconductor) gadgets in many applications. Unfortunately, these new technologies cannot disembark the common Boolean logic efficiently and are only appropriate for liminal logic. Therefor there is no doubt that with the development of these new gadgets it is necessary to find new MacDraw technologies which are compatible with them. Resonant transistor tunnels (RTD/RTT) and circuit MacDraw with enhanced computing abilities are candida for accumulating Nano criterion in the future. Quantum cellular automata (QCA) are also advent Nano technological gadgets for electrical circuits. Advantages of these gadgets such as higher speed, smaller dimensions, and lower consumption loss are of great consideration. QCA are basic gadgets in manufacturing gates, fuses and memories. Regarding the complex Nano criterion physical entity, circuit designers can focus on logical and constructional design to decrease complication in MacDraw. Moreover Single electron technology (SET) is another noteworthy gadget considered in Nano technology. This article is a survey in future of Nano technology in digital MacDraw.

Keywords: nano technology, resonant transistor tunnels, quantum cellular automata, semiconductor

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Authors: Kusuma Urs M. B., Navakant Bhat, Vinayak B. Kamble

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Metal oxide semiconductors (MOS) are known to be excellent candidates for solid-state gas sensor devices. However, in spite of high sensitivities, their high operating temperatures and lack of selectivity is a big concern limiting their practical applications. A lot of research has been devoted so far to enhance their sensitivity and selectivity, often empirically. Some of the promising routes to achieve the same are reducing dimensionality and formation of heterostructures. These heterostructures offer improved sensitivity, selectivity even at relatively low operating temperatures compared to bare metal oxides. Thus, a combination of n-type and p-type metal oxides leads to the formation of p-n junction at the interface resulting in the diffusion of the carriers across the barrier along with the surface adsorption. In order to achieve this and to study their sensing mechanism, we have designed and lithographically fabricated a suspended nanobeam of NiO, which is a p-type semiconductor. The response of the same has been studied for various gases and is found to exhibit selective response towards hydrogen gas at room temperature. Further, the same has been radially coated with TiO₂ shell of varying thicknesses, in order to study the effect of radial p-n junction thus formed. Subsequently, efforts have been made to study the effect of shell thickness on the space charge region and to shed some light on the basic mechanism involved in gas sensing of MOS sensors.

Keywords: gas sensing, heterostructure, metal oxide semiconductor, space charge region

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Goban Kumar Panneer Selvam

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In past years, there is lots of death caused due to harmful gases. So its very important to monitor harmful gases for human safety, and semiconductor material play important role in producing effective gas sensors.A novel solvothermal synthesis method based on sol-gel processing was prepared to deposit tin oxide thin films on glass substrate at high temperature for gas sensing application. The structure and morphology of tin oxide were analyzed by X-ray diffraction (XRD), Fourier transforms infrared spectroscopy (FTIR) and scanning electron microscopy (SEM). The SEM analysis of how spheres shape in tin oxide nanoparticles. The structure characterization of tin oxide studied by X-ray diffraction shows 8.95 nm (calculated by sheers equation). The UV visible spectroscopy indicated a maximum absorption band shown at 390 nm. Further dope tin oxide with selected metals to attain maximum sensitivity using dip coating technique with different immersion and sensing characterization are measured.

Keywords: tin oxide, gas sensor, chlorine free, sensitivity, crystalline size

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Authors: M. Kessi

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We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: power efficiency, static power consumption, dynamic power consumption, CMOS

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Authors: Abdulnasser S. Saleh

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The importance of metal-semiconductor interfaces comes from the fact that most electronic devices are interconnected using metallic wiring that forms metal–semiconductor contacts. The properties of these contacts can vary considerably depending on the nature of the interface with the semiconductor. Variable-energy positron annihilation spectroscopy has been applied to study interfaces in Al/Si, Au/Si, and Au/GaAs structures. A computational modeling by ROYPROF program is used to analyze Doppler broadening results in order to determine kinds of regions that positrons are likely to sample. In all fittings, the interfaces are found 1 nm thick and act as an absorbing sink for positrons diffusing towards them and may be regarded as highly defective. Internal electric fields were found to influence positrons diffusing to the interfaces and unable to force them cross to the other side. The materials positron affinities are considered in understanding such motion. The results of these theoretical fittings have clearly demonstrated the sensitivity of interfaces in any fitting attempts of analyzing positron spectroscopy data and gave valuable information about metal-semiconductor interfaces.

Keywords: interfaces, semiconductor, positron, defects

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Authors: Chyuan Haur Kao, Hsiang Chen, Yu Sheng Tsai, Chen Hao Hung, Yu Shan Lee

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Dielectric electrolyte-insulator-semiconductor sensing membranes-based biosensors have been intensively investigated because of their simple fabrication, low cost, and fast response. However, to enhance their sensing performance, it is worthwhile to explore alternative materials, distinct processes, and novel treatments. An ISFET can be viewed as a variation of MOSFET with the dielectric oxide layer as the sensing membrane. Then, modulation on the work function of the gate caused by electrolytes in various ion concentrations could be used to calculate the ion concentrations. Recently, owing to the advancement of CMOS technology, some high dielectric materials substrates as the sensing membranes of electrolyte-insulator-semiconductor (EIS) structures. The EIS with a stacked-layer of SiO₂ layer between the sensing membrane and the silicon substrate exhibited a high pH sensitivity and good long-term stability. IGZO is a wide-bandgap (~3.15eV) semiconductor of the III-VI semiconductor group with several preferable properties, including good transparency, high electron mobility, wide band gap, and comparable with CMOS technology. IGZO was sputtered by reactive radio frequency (RF) on a p-type silicon wafer with various gas ratios of Ar:O₂ and was treated with rapid thermal annealing in O₂ ambient. The sensing performance, including sensitivity, hysteresis, and drift rate was measured and XRD, XPS, and AFM analyses were also used to study the material properties of the IGZO membrane. Moreover, IGZO was used as a sensing membrane in dielectric EIS bio-sensor structures. In addition to traditional pH sensing capability, detection for concentrations of Na+, K+, urea, glucose, and creatinine was performed. Moreover, post rapid thermal annealing (RTA) treatment was confirmed to improve the material properties and enhance the multi-analyte sensing capability for various ions or chemicals in solutions. In this study, the IGZO sensing membrane with annealing in O₂ ambient exhibited a higher sensitivity, higher linearity, higher H+ selectivity, lower hysteresis voltage and lower drift rate. Results indicate that the IGZO dielectric sensing membrane on the EIS structure is promising for future bio-medical device applications.

Keywords: dielectric sensing membrane, IGZO, hydrogen ion, plasma, rapid thermal annealing

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Authors: Deepika Sharma, Bal Krishan

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In this paper, the structure of N-channel VDMOS was designed and analyzed using Silvaco TCAD tools by varying N+ source doping concentration, P-Body doping concentration, gate oxide thickness and the diffuse time. VDMOS is considered to be ideal power switches due to its high input impedance and fast switching speed. The performance of the device was analyzed from the Ids vs Vgs curve. The electrical characteristics such as threshold voltage, gate oxide thickness and breakdown voltage for the proposed device structures were extarcted. Effect of epitaxial layer on various parameters is also observed.

Keywords: on-resistance, threshold voltage, epitaxial layer, breakdown voltage

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Authors: Zekun Lin, Xun Li

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Silicon photonics has gained much interest and extensive research for a promising aspect for fabricating compact, high-speed and low-cost photonic devices compatible with complementary metal-oxide-semiconductor (CMOS) process. Despite the remarkable progress made on the development of silicon photonics, high-performance, cost-effective, and reliable silicon laser sources are still missing. In this work, we present a 1550 nm III-V/silicon laser design with stable single-mode lasing property and robust and high-efficiency vertical coupling. The InP cavity consists of two uniform Bragg grating sections at sides for mode selection and feedback, as well as a central second-order grating for surface emission. A grating coupler is etched on the SOI waveguide by which the light coupling between the parallel III-V and SOI is reached vertically rather than by evanescent wave coupling. Laser characteristic is simulated and optimized by the traveling-wave model (TWM) and a Green’s function analysis as well as a 2D finite difference time domain (FDTD) method for the coupling process. The simulation results show that single-mode lasing with SMSR better than 48dB is achievable, and the threshold current is less than 15mA with a slope efficiency of around 0.13W/A. The coupling efficiency is larger than 42% and possesses a high tolerance with less than 10% reduction for 10 um horizontal or 15 um vertical dislocation. The design can be realized by standard flip-chip bonding techniques without co-fabrication of III-V and silicon or precise alignment.

Keywords: III-V/silicon integration, silicon photonics, single mode laser, vertical coupling

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Authors: Amir Shariffar, Haider Salman, Tanveer Siddique, Omar Manasreh

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According to the recent studies on metal-oxide memristors, researchers tend to improve the stability, endurance, and uniformity of resistive switching (RS) behavior in memristors. Specifically, the main challenge is to prevent abrupt ruptures in the memristor’s filament during the RS process. To address this problem, we are proposing a low-cost hybrid structure of metal oxide quantum dots (QDs) and thin films to control the formation of filaments in memristors. We aim to use metal oxide quantum dots because of their unique electronic properties and quantum confinement, which may improve the resistive switching behavior. QDs have discrete energy spectra due to electron confinement in three-dimensional space. Because of Coulomb repulsion between electrons, only a few free electrons are contained in a quantum dot. This fact might guide the growth direction for the conducting filaments in the metal oxide memristor. As a result, it is expected that QDs can improve the endurance and uniformity of RS behavior in memristors. Moreover, we use a hybrid structure of intrinsic n-type quantum dots and p-type thin films to introduce a potential barrier at the junction that can smooth the transition between high and low resistance states. A bottom-up approach is used for fabricating the proposed memristor using different types of metal-oxide QDs and thin films. We synthesize QDs including, zinc oxide, molybdenum trioxide, and nickel oxide combined with spin-coated thin films of titanium dioxide, copper oxide, and hafnium dioxide. We employ fluorine-doped tin oxide (FTO) coated glass as the substrate for deposition and bottom electrode. Then, the active layer composed of one type of quantum dots, and the opposite type of thin films is spin-coated onto the FTO. Lastly, circular gold electrodes are deposited with a shadow mask by using electron-beam (e-beam) evaporation at room temperature. The fabricated devices are characterized using a probe station with a semiconductor parameter analyzer. The current-voltage (I-V) characterization is analyzed for each device to determine the conduction mechanism. We evaluate the memristor’s performance in terms of stability, endurance, and retention time to identify the optimal memristive structure. Finally, we assess the proposed hypothesis before we proceed to the optimization process for fabricating the memristor.

Keywords: memristor, quantum dot, resistive switching, thin film

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Authors: Vaia N. Koukou, Niki D. Martini, George P. Fountos, Christos M. Michail, Athanasios Bakas, Ioannis S. Kandarakis, George C. Nikiforidis

Abstract:

Various substitute materials of calcifications are used in phantom measurements and simulation studies in mammography. These include calcium carbonate, calcium oxalate, hydroxyapatite and aluminum. The aim of this study is to compare the contrast-to-noise ratio (CNR) values of the different calcification types using the dual energy method. The constructed calcification phantom consisted of three different calcification types and thicknesses: hydroxyapatite, calcite and calcium oxalate of 100, 200, 300 thicknesses. The breast tissue equivalent materials were polyethylene and polymethyl methacrylate slabs simulating adipose tissue and glandular tissue, respectively. The total thickness was 4.2 cm with 50% fixed glandularity. The low- (LE) and high-energy (HE) images were obtained from a tungsten anode using 40 kV filtered with 0.1 mm cadmium and 70 kV filtered with 1 mm copper, respectively. A high resolution complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) X-ray detector was used. The total mean glandular dose (MGD) and entrance surface dose (ESD) from the LE and HE images were constrained to typical levels (MGD=1.62 mGy and ESD=1.92 mGy). On average, the CNR of hydroxyapatite calcifications was 1.4 times that of calcite calcifications and 2.5 times that of calcium oxalate calcifications. The higher CNR values of hydroxyapatite are attributed to its attenuation properties compared to the other calcification materials, leading to higher contrast in the dual energy image. This work was supported by Grant Ε.040 from the Research Committee of the University of Patras (Programme K. Karatheodori).

Keywords: calcification materials, CNR, dual energy, X-rays

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Authors: Loai Ben Naji, Osama M. Ibrahim, Khaled J. Al-Fadhalah

Abstract:

The objective of this paper is to investigate the formation and adhesion of a protective aluminum-oxide (Al₂O₃, alumina) layer on the surface of Iron-Chromium-Aluminum Alloy (Fe-Cr-Al) sintered-metal-fibers. The oxide-scale layer was developed via multi-stage thermal oxidation at 930 ^oC for 1 hour, followed by 1 hour at 960 ^oC, and finally at 990 ^oC for 2 hours. Scanning Electron Microscope (SEM) images show that the multi-stage thermal oxidation resulted in the formation of predominantly Al₂O₃ platelets-like and whiskers. SEM images also reveal non-uniform oxide-scale growth on the surface of the fibers. Furthermore, peeling/spalling of the alumina protective layer occurred after minimum handling, which indicates weak adhesion forces between the protective layer and the base metal alloy.  Energy Dispersive Spectroscopy (EDS) analysis of the heat-treated Fe-Cr-Al sintered-metal-fibers confirmed the high aluminum content on the surface of the protective layer, and the low aluminum content on the exposed base metal alloy surface. In conclusion, the failure of the oxide-scale protective layer exposes the base metal alloy to further oxidation, and the fragile non-uniform oxide-scale is not suitable as a support for catalysts.

Keywords: high-temperature oxidation, iron-chromium-aluminum alloy, alumina protective layer, sintered-metal-fibers

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Authors: S. Singh, P. Patel, D. Kachhadiya, Swapnil Dharaskar

Abstract:

The research objective is to integrate nanoparticles into fuels- i.e. diesel, biodiesel, biodiesel blended with diesel, plastic derived fuels, etc. to increase the fuel efficiency. The metal oxide nanoparticles will reduce the carbon monoxide emissions by donating oxygen atoms from their lattices to catalyze the combustion reactions and to aid complete combustion; due to this, there will be an increase in the calorific value of the blend (fuel + metal nanoparticles). Aluminium oxide and cobalt oxide nanoparticles have been synthesized by sol-gel method. The characterization was done by Fourier Transform Infrared Spectroscopy (FTIR), X-Ray Diffraction (XRD), Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDS). The size of the particles was determined by XRD to be 28.6 nm and 28.06 nm for aluminium oxide and cobalt oxide nanoparticles respectively. Different concentration blends- 50, 100, 150 ppm were prepared by adding the required weight of metal oxides in 1 liter of diesel and sonicating for 30 minutes at 500W. The blend properties- calorific value, viscosity, and flash point were determined by bomb calorimeter, Brookfield viscometer and pensky-martin apparatus. For the aluminum oxide blended diesel, there was a maximum increase of 5.544% in the calorific value, but at the same time, there was an increase in the flash point from 43°C to 58.5°C and an increase in the viscosity from 2.45 cP to 3.25 cP. On the other hand, for the cobalt oxide blended diesel there was a maximum increase of 2.012% in the calorific value while the flash point increased from 43°C to 51.5°C and the viscosity increased from 2.45 cP to 2.94 cP. There was a linear increase in the calorific value, viscosity and flash point when the concentration of the metal oxide nanoparticles in the blend was increased. For the 50 ppm Al₂O₃ and 50 ppm Co₃O₄ blend the increasing the calorific value was 1.228 %, and the viscosity changed from 2.45 cP to 2.64 cP and the flash point increased from 43°C to 50.5°C. Clearly the aluminium oxide nanoparticles increase the calorific value but at the cost of flash point and viscosity, thus it is better to use the 50 ppm aluminium oxide, and 50 ppm cobalt oxide blended diesel.

Keywords: aluminium oxide nanoparticles, cobalt oxide nanoparticles, fuel additives, fuel characteristics

Procedia PDF Downloads 283