Search results for: spintronic circuits

Authors: Shittu Akinpelu, Issac Popoola

Abstract:

The compound NbRhGe has been predicted to be a semiconductor with excellent mechanical properties. It is an indirect band gap material. The potential of NbRhGe for non-volatile data storage via element addition is being studied using the Density Functional Theory (DFT). Preliminary results on the electronic and magnetic properties are suggestive for their application in spintronic.

Keywords: half-metals, Heusler compound, semiconductor, spintronic

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Authors: Saurabh Basu, Sudin Ganguly

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Conductance in graphene nanoribbons (GNR) in presence of magnetic (for example, Iron) and non-magnetic (for example, Gold) adatoms are explored theoretically within a Kane-Mele model for their possible spintronic applications and topologically non-trivial properties. In our work, we have considered the magnetic adatoms to induce a Rashba spin-orbit coupling (RSOC) and an exchange bias field, while the non-magnetic ones induce an RSOC and an intrinsic spin-orbit (SO) coupling. Even though RSOC is present in both, they, however, represent very different physical situations, where the magnetic adatoms do not preserve the time reversal symmetry, while the non-magnetic case does. This has important implications on the topological properties. For example, the non-magnetic adatoms, for moderately strong values of SO, the GNR denotes a quantum spin Hall insulator as evident from a 2e²/h plateau in the longitudinal conductance and presence of distinct conducting edge states with an insulating bulk. Since the edge states are protected by time reversal symmetry, the magnetic adatoms in GNR yield trivial insulators and do not possess any non-trivial topological property. However, they have greater utility than the non-magnetic adatoms from the point of view of spintronic applications. Owing to the broken spatial symmetry induced by the presence of adatoms of either type, all the x, y and z components of the spin-polarized conductance become non-zero (only the y-component survives in pristine Graphene owing to a mirror symmetry present there) and hence become suitable for spintronic applications. However, the values of the spin polarized conductances are at least two orders of magnitude larger in the case of magnetic adatoms than their non-magnetic counterpart, thereby ensuring more efficient spintronic applications. Further the applications are tunable by altering the adatom densities.

Keywords: magnetic and non-magnetic adatoms, quantum spin hall phase, spintronic applications, spin polarized conductance, time reversal symmetry

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Authors: Wieslaw Marszalek, Zdzislaw Trzaska

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Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed.

Keywords: mixed-mode oscillations, memristive circuits, pinched hysteresis, one-period loops, singularly perturbed circuits

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Authors: Zhengming Wu

Abstract:

NanoFrazor lithography systems were developed as a first true alternative or extension to standard mask-less nanolithography methods like electron beam lithography (EBL). In contrast to EBL they are based on thermal scanning probe lithography (t-SPL). Here a heatable ultra-sharp probe tip with an apex of a few nm is used for patterning and simultaneously inspecting complex nanostructures. The heat impact from the probe on a thermal responsive resist generates those high-resolution nanostructures. The patterning depth of each individual pixel can be controlled with better than 1 nm precision using an integrated in-situ metrology method. Furthermore, the inherent imaging capability of the Nanofrazor technology allows for markerless overlay, which has been achieved with sub-5 nm accuracy as well as it supports stitching layout sections together with < 10 nm error. Pattern transfer from such resist features below 10 nm resolution were demonstrated. The technology has proven its value as an enabler of new kinds of ultra-high resolution nanodevices as well as for improving the performance of existing device concepts. The application range for this new nanolithography technique is very broad spanning from ultra-high resolution 2D and 3D patterning to chemical and physical modification of matter at the nanoscale. Nanometer-precise markerless overlay and non-invasiveness to sensitive materials are among the key strengths of the technology. However, while patterning at below 10 nm resolution is achieved, significantly increasing the patterning speed at the expense of resolution is not feasible by using the heated tip alone. Towards this end, an integrated laser write head for direct laser sublimation (DLS) of the thermal resist has been introduced for significantly faster patterning of micrometer to millimeter-scale features. Remarkably, the areas patterned by the tip and the laser are seamlessly stitched together and both processes work on the very same resist material enabling a true mix-and-match process with no developing or any other processing steps in between. The presentation will include examples for (i) high-quality metal contacting of 2D materials, (ii) tuning photonic molecules, (iii) generating nanofluidic devices and (iv) generating spintronic circuits. Some of these applications have been enabled only due to the various unique capabilities of NanoFrazor lithography like the absence of damage from a charged particle beam.

Keywords: nanofabrication, grayscale lithography, 2D materials device, nano-optics, photonics, spintronic circuits

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Authors: S. Bentata, W. Benstaali, A. Abbad, H. A. Bentounes, B. Bouadjemi

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The full potential linear augmented plane wave (FPLAPW) based on density-functional theory (DFT) is employed to study the electronic, magnetic and optical properties of some transition metals doped ZnSe. Calculations are carried out by varying the doped atoms. Four 3D transition elements were used as a dopant: Cr, Mn, Co and Cu in order to induce spin polarization. Our results show that, Mn and Cu-doped ZnSe could be used in spintronic devices only if additional dopants are introduced, on the contrary, transition elements showing delocalized quality such as Cr, and Co doped ZnSe might be promising candidates for application in spintronic.

Keywords: spin-up, spin-down, magnetic properties, transition metal, composite materials

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Authors: J. Hajri, H. Hrizi, N. Sboui, H. Baudrand

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This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS.

Keywords: convergence study, HFSS, modal decomposition, SIW circuits, WCIP method

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

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This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

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This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

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In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: integrator circuits, MOS-C realization, nonlinearity cancellation, tuneable resistors

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Authors: Masaya Yoshikawa, Toshiya Asai, Ryoma Matsuhisa, Yusuke Nozaki, Kensaku Asahi

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Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources.

Keywords: tamper resistance, cryptographic circuit, hardware security evaluation, noise resources

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Authors: Juhi Faridi, Mohd. Ajmal Kafeel

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The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS.

Keywords: analog circuits, digital circuits, memristors, neuromorphic computing systems

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Authors: N. Ourabia, M. Boubaker Ourabia

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An approach for modeling and numerical simulation of passive planar structures using the edge line concept is developed. With this method, we develop an efficient modeling technique for microstrip discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then, it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: optimization, CAD analysis, microwave circuits, S-parameters

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Authors: Vanessa Funk, Steven Blum, Stephanie Cole, Jorge Maciel, Matthew Lux

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Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals.

Keywords: cell-free lysates, detection, gene circuits, in vitro

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Authors: S. Summart, C. Saetiaw, T. Thosdeekoraphat, C. Thongsopa

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This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Keywords: current-mode, quadrature oscillator, block diagram, CDTA

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Authors: Mir Shahriar Emami

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Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models.

Keywords: SDLC, SSDLC, software security, software process engineering, hardware systems and circuits security

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Authors: Ravinder Dachepalli, Naveena Gadwala, K. Vani

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Nd and Er substituted bismuth nano crystalline multifunctional materials were prepared by citrate gel autocombution technique. The structural characterization was carried out by XRD and SEM. Electrical properties such are electrical conductivity and dielectric properties have been measured. Plots of electrical conductivity versus temperature increases with increasing temperature and shown a transition near Curie temperature. Dielectric properties such are dielectric constant and dielectric loss tangent have been measured from 20Hz to 2 MHz at room temperature. Plots of dielectric constant versus frequency show a normal dielectric behaviour of multifunctional materials. Temperature dependence of magnetic properties of Bi-Nd and Bi-Er multi-functional materials were carried out by using Vibrating sample magnetometer (VSM). The magnetization as a function of an applied field ±100 Oe was carried out at 3K and 360 K. Zero field Cooled (ZFC) and Field Cooled (FC) magnetization measurements under an applied field of 100Oe a in the temperature range of 5-375K. The observed results can be explained for spintronic devices.

Keywords: Bi-Nd and Bi-Er Multifunctional Materia, Citrate Gel Auto combustion Technique, FC-ZFC magnetization, Dielectric constant

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Authors: Karkour Selma

Abstract:

We conducted first principles full potential calculations using the Wien2k code to explore the structural, electronic, magnetic, and optical properties of SiNi₂O₄, a cubic normal spinel oxide. Our calculations, based on the GGA-PBEsol of the generalized gradient approximation, revealed several key findings. The spinel oxides exhibited a stable cubic structure in the ferromagnetic phase and showed 100% spin polarization. We determined the equilibrium lattice constant and internal parameter values. In terms of the electronic properties, we observed a direct bandgap of 2.68 eV for the spin-up configuration, while the spin-down configuration exhibited an indirect bandgap of 0.82 eV. Additionally, we calculated the total density of states and partial densities for each atom, finding a magnetic moment spin density of states of 8.0 μB per formula unit. The optical properties have been calculated. The real, Ԑ₁(ω) and the imaginary, Ԑ₂(ω) parts of the complex dielectric constants, refractivity, reflection and energy loss when light scattered from the material. The absorption region spanned from 1.5 eV to 14 eV, with significant intensity. The calculated results confirm the suitability of this material for optical and spintronic devices application.

Keywords: DFT, spintronic, GGA, spinel

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Authors: Nassim Ourabia, Malika Ourabia

Abstract:

A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: CAD analysis, contour integral approach, microwave circuits, s-parameters

Procedia PDF Downloads 472

Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: G. N. Srinivas, K. Raju

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This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS).

Keywords: distribution system, Markov Model, reliability indices, spice simulation

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Authors: S. Nqayi

Abstract:

Understanding the structural, electronic, and magnetic properties of nanomaterials is essential for developing next-generation electronic and spintronic devices, contributing to the progress of nanoscience and nanotechnology applications. Multiferroic materials, with intimately coupled ferroic-order parameters, are widely considered to breed fascinating physical properties and provide unique opportunities for the development of next-generation devices, like multistate non-volatile memory. In this study, we are set to investigate the structural, electronic, and magnetic properties of the frustrated Feᴵᴵ/Smⱽᴵ sublattice in relation to the widely studied perovskites for spintronics applications. The atomic composition, microstructure, crystallography, magnetization, thermal, and dielectric properties of a pyrochlore Sm₂Fe₂O₇ system synthesized using sol-gel methods are currently being investigated. Precursor powders were dissolved in citric acid monohydrate to obtain a solution. The obtained solution was stirred and heated using a magnetic stirrer to obtain the gel phase. Then, the gel was dried at 200°C to remove water and organic compounds and form an orange powder. The X-ray diffraction analysis confirms that the structure crystallized as a pyrochlore structure with a tetragonal F4mm (107) symmetry. The presence of Fe³⁺/Fe⁴⁺ mixed states is also revealed by XPS analysis.

Keywords: nanostructures, multiferroic materials, pyrochlores, spintronics

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: B. Bouadjemi, S. Bentata, A. Abbad, W.Benstaali

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The full-potential linearized augmented plane wave method (FP-LAPW) within the Generalized Gradient Approximation (GGA) is used to calculate the magnetic and optical properties of quaternary GaFeMnN. The results show that the compound becomes magnetic and half metallic and there is an apparition of peaks at low frequencies for the optical properties.

Keywords: optical properties, DFT, Spintronic, wave

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Authors: Lokes Parvatha Kumaran S., Sakthi Jay Mahenthar C., Sathyaprakash P., Jayakumar V., Shobanadevi A.

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With the evolution of technology, the need to solve complex computational problems like machine learning and deep learning has shot up. But even the most powerful classical supercomputers find it difficult to execute these tasks. With the recent development of quantum computing, researchers and tech-giants strive for new quantum circuits for machine learning tasks, as present works on Quantum Machine Learning (QML) ensure less memory consumption and reduced model parameters. But it is strenuous to simulate classical deep learning models on existing quantum computing platforms due to the inflexibility of deep quantum circuits. As a consequence, it is essential to design viable quantum algorithms for QML for noisy intermediate-scale quantum (NISQ) devices. The proposed work aims to explore Variational Quantum Circuits (VQC) for Deep Reinforcement Learning by remodeling the experience replay and target network into a representation of VQC. In addition, to reduce the number of model parameters, quantum information encoding schemes are used to achieve better results than the classical neural networks. VQCs are employed to approximate the deep Q-value function for decision-making and policy-selection reinforcement learning with experience replay and the target network.

Keywords: quantum computing, quantum machine learning, variational quantum circuit, deep reinforcement learning, quantum information encoding scheme

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Authors: Zhangquan Zhou, Guilin Qi

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Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes.

Keywords: ontology materialization, parallel reasoning, datalog, Boolean circuit

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Jalal M. Abdallah

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This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer.

Keywords: frequency response analysis (FRA), measurements, transfer function, transformer

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Authors: Kaiwen Zheng, Wanting Zhou, Nan Tang, Lei Li, Yuanhang He

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The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs.

Keywords: hardware trojans, physical properties, machine learning, hardware security

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Authors: Arabi Abderrazak, Bourouba Nacerdine, Ayad Mouloud, Belaout Abdeslam

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In this paper, a new test technique of analog circuits using time mode simulation is proposed for the single catastrophic faults detection in analog circuits. This test process is performed to overcome the problem of catastrophic faults being escaped in a DC mode test applied to the inverter amplifier in previous research works. The circuit under test is a second-order low pass filter constructed around this type of amplifier but performing a function that differs from that of the previous test. The test approach performed in this work is based on two key- elements where the first one concerns the unique square pulse signal selected as an input vector test signal to stimulate the fault effect at the circuit output response. The second element is the filter response conversion to a square pulses sequence obtained from an analog comparator. This signal conversion is achieved through a fixed reference threshold voltage of this comparison circuit. The measurement of the three first response signal pulses durations is regarded as fault effect detection parameter on one hand, and as a fault signature helping to hence fully establish an analog circuit fault diagnosis on another hand. The results obtained so far are very promising since the approach has lifted up the fault coverage ratio in both modes to over 90% and has revealed the harmful side of faults that has been masked in a DC mode test.

Keywords: analog circuits, analog faults diagnosis, catastrophic faults, fault detection

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Authors: Azizi Cherifa, O. Benzaoui

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The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

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