Search results for: metal-oxide-semiconductor field-effect transistor (MOSFET)

Authors: Suruchi Saini, Hitender Kumar Tyagi

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With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: M. Abouelatta, A. Shaker, M. El-Banna, G. T. Sayah, C. Gontrand, A. Zekry

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In this paper, a methodology for physically modeling the intrinsic MOS part and the drift region of the n-channel Laterally Double-diffused MOSFET (LDMOS) is presented. The basic physical effects like velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are taken into consideration. The analytical model is implemented using MATLAB. A comparison of the simulations from technology computer aided design (TCAD) and that from the proposed analytical model, at room temperature, shows a satisfactory accuracy which is less than 5% for the whole voltage domain.

Keywords: LDMOS, MATLAB, RESURF, modeling, TCAD

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Authors: Samson Mil'shtein, Dhawal Asthana, Benjamin Sullivan

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The wide energy gap of GaN is the major parameter justifying the design and fabrication of high-power electronic components made of this material. However, the existence of a piezo-electrics in nature sheet charge at the AlGaN/GaN interface complicates the control of carrier injection into the intrinsic channel of GaN HEMTs (High Electron Mobility Transistors). As a result, most of the transistors created as R&D prototypes and all of the designs used for mass production are D-mode devices which introduce challenges in the design of integrated circuits. This research presents the design and modeling of an E-mode GaN HEMT with a very low turn-on voltage. The proposed device includes two critical elements allowing the transistor to achieve zero conductance across the channel when Vg = 0V. This is accomplished through the inclusion of an extremely thin, 2.5nm intrinsic Ga₀.₇₄Al₀.₂₆N spacer layer. The added spacer layer does not create piezoelectric strain but rather elastically follows the variations of the crystal structure of the adjacent GaN channel. The second important factor is the design of a gate metal with a high work function. The use of a metal gate with a work function (Ni in this research) greater than 5.3eV positioned on top of n-type doped (Nd=10¹⁷cm⁻³) Ga₀.₇₄Al₀.₂₆N creates the necessary built-in potential, which controls the injection of electrons into the intrinsic channel as the gate voltage is increased. The 5µm long transistor with a 0.18µm long gate and a channel width of 30µm operate at Vd=10V. At Vg =1V, the device reaches the maximum drain current of 0.6mA, which indicates a high current density. The presented device is operational at frequencies greater than 10GHz and exhibits a stable transconductance over the full range of operational gate voltages.

Keywords: compound semiconductors, device modeling, enhancement mode HEMT, gallium nitride

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Authors: Rajesh Agarwal

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Carrier mobility at the organic/insulator interface is essential to the performance of organic thin film transistors (OTFT). The present work describes estimation of field dependent mobility (FDM) parameters and the threshold voltage of an OTFT using a simple, easy to fabricate two terminal asymmetric capacitive test structure using admittance measurements. Conventionally, transfer characteristics are used to estimate the threshold voltage in an OTFT with field independent mobility (FIDM). Yet, this technique breaks down to give accurate results for devices with high contact resistance and having field dependent mobility. In this work, a new technique is presented for characterization of long channel organic capacitor (LCOC). The proposed technique helps in the accurate estimation of mobility enhancement factor (γ), the threshold voltage (V_th) and band mobility (µ₀) using capacitance-voltage (C-V) measurement in OTFT. This technique also helps to get rid of making short channel OTFT or metal-insulator-metal (MIM) structures for making C-V measurements. To understand the behavior of devices and ease of analysis, transmission line compact model is developed. The 2-D numerical simulation was carried out to illustrate the correctness of the model. Results show that proposed technique estimates device parameters accurately even in the presence of contact resistance and field dependent mobility. Pentacene/Poly (4-vinyl phenol) based top contact bottom-gate OTFT’s are fabricated to illustrate the operation and advantages of the proposed technique. Small signal of frequency varying from 1 kHz to 5 kHz and gate potential ranging from +40 V to -40 V have been applied to the devices for measurement.

Keywords: capacitance, mobility, organic, thin film transistor

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Authors: Meng-Jie Hsiao, Cam Nguyen

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Wide-band devices in Ku band (12-18 GHz) and K band (18-27 GHz) have received significant attention for high-data-rate communications and high-resolution sensing. Especially, devices operating around 24 GHz is attractive due to the 24-GHz unlicensed applications. One of the most important components in RF systems is power amplifier (PA). Various PAs have been developed in the Ku and K bands on GaAs, InP, and silicon (Si) processes. Although the PAs using GaAs or InP process could have better power handling and efficiency than those realized on Si, it is very hard to integrate the entire system on the same substrate for GaAs or InP. Si, on the other hand, facilitates single-chip systems. Hence, good PAs on Si substrate are desirable. Especially, Si-based PA having good linearity is necessary for next generation communication protocols implemented on Si. We report a 16.5 to 25.5 GHz Si-based PA having flat saturated power of 19.5 ± 1.5 dBm, output 1-dB power compression (OP1dB) of 16.5 ± 1.5 dBm, and 15-23 % power added efficiency (PAE). The PA consists of a drive amplifier, two main amplifiers, and lump-element Wilkinson power divider and combiner designed and fabricated in TowerJazz 0.18µm SiGe BiCMOS process having unity power gain frequency (fMAX) of more than 250 GHz. The PA is realized as a cascode amplifier implementing both heterojunction bipolar transistor (HBT) and n-channel metal–oxide–semiconductor field-effect transistor (NMOS) devices for gain, frequency response, and linearity consideration. Particularly, a body-floating technique is utilized for the NMOS devices to improve the voltage swing and eliminate parasitic capacitances. The developed PA has measured flat gain of 20 ± 1.5 dB across 16.5-25.5 GHz. At 24 GHz, the saturated power, OP1dB, and maximum PAE are 20.8 dBm, 18.1 dBm, and 23%, respectively. Its high performance makes it attractive for use in Ku/K-band, especially 24 GHz, communication and radar systems. This paper was made possible by NPRP grant # 6-241-2-102 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.

Keywords: power amplifiers, amplifiers, communication systems, radar systems

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Authors: Rahil Samani, Saeed Soleimani, Ehsan Adib, Majid Pahlevani

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This paper presents an inverting high step-up DC/DC converter. Basically, this high step-up DC/DC converter is an appealing interface for solar applications. The proposed topology takes advantage of using coupled inductors. Due to the leakage inductances of these coupled inductors, the power MOSFET has the zero current switching (ZCS) condition, which results in decreased switching losses. This will substantially improve the overall efficiency of the power converter. Furthermore, employing coupled inductors has led to a higher voltage gain. Theoretical analysis and experimental results of a 100W 20V/220V prototype are presented to verify the superior performance of the proposed DC/DC converter.

Keywords: coupled inductors, high step-up DC/DC converter, zero-current switching, Cuk converter, SEPIC converter

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Authors: Nagaraju Jarugu, B. R. Narendra

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This paper focused on boost rectification by Single Phase Matrix Converter with fewer numbers of switches. The conventional matrix converter consists of 4 bidirectional switches, i.e. 8 set of IGBT/MOSFET with anti-parallel diodes. In this proposed matrix converter, only six switches are used. The switch commutation arrangements are also carried out in this work. The SPMC topology has many advantages as a minimal passive device use. It is very flexible and it can be used as a lot of converters. The gate pulses to the switches are provided by the PWM techniques. The duty ratio of the switches based on Pulse Width Modulation (PWM) technique was used to produce the output waveform of the circuit, simply by turning ON and OFF the switches. The simulation results using MATLAB/Simulink were provided to validate the feasibility of this proposed method.

Keywords: single phase matrix converter, reduced switches, AC voltage regulators, boost rectifier operation

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Authors: Jae-Chang Kwak, Yong-Seo Koo

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The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: S. Slimani, B. Djellouli

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Novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials like Ge is a very promising material due to its high mobility and is being considered to replace Si in the channel to achieve higher drive currents and switching speeds .Various approaches to circumvent the scaling limits to benchmark the performance of nanoscale MOSFETS with different channel materials, the optimized structure is simulated within nextnano in order to highlight the quantum effects on DG MOSFETs when Si is replaced by Ge and SiO2 is replaced by ZrO2 and HfO2as the gate dielectric. The results have shown that Ge MOSFET have the highest mobility and high permittivity oxides serve to maintain high drive current. The simulations show significant improvements compared with DGMOSFET using SiO2 gate dielectric and Si channel.

Keywords: high mobility, high-k, quantum effects, SOI-DGMOSFET

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Authors: Lenon M. Pereira, Helen J. Khoury, Marcos E. A. Andrade, Dean L. Cutajar, Vinicius S. M. Barros, Anatoly B. Rozenfeld

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With the increase of beam widths and the advent of multiple-slice and helical scanners, concerns related to the current dose measurement protocols and instrumentation in computed tomography (CT) have arisen. The current methodology of dose evaluation, which is based on the measurement of the integral of a single slice dose profile using a 100 mm long cylinder ionization chamber (Ca,100 and CPPMA, 100), has been shown to be inadequate for wide beams as it does not collect enough of the scatter-tails to make an accurate measurement. In addition, a long ionization chamber does not offer a good representation of the dose profile when tube current modulation is used. An alternative approach has been suggested by translating smaller detectors through the beam plane and assessing the accumulated dose trough the integral of the dose profile, which can be done for any arbitrary length in phantoms or in the air. For this purpose, a MOSFET dosimeter of small dosimetric volume was used. One of its recently designed versions is known as the MOSkin, which is developed by the Centre for Medical Radiation Physics at the University of Wollongong, and measures the radiation dose at a water equivalent depth of 0.07 mm, allowing the evaluation of skin dose when placed at the surface, or internal point doses when placed within a phantom. Thus, the aim of this research was to characterize the response of the MOSkin dosimeter for X-ray CT beams and to evaluate its application for the accumulated dose assessment. Initially, tests using an industrial x-ray unit were carried out at the Laboratory of Ionization Radiation Metrology (LMRI) of Federal University of Pernambuco, in order to investigate the sensitivity, energy dependence, angular dependence, and reproducibility of the dose response for the device for the standard radiation qualities RQT 8, RQT 9 and RQT 10. Finally, the MOSkin was used for the accumulated dose evaluation of scans using a Philips Brilliance 6 CT unit, with comparisons made between the CPPMA,100 value assessed with a pencil ionization chamber (PTW Freiburg TW 30009). Both dosimeters were placed in the center of a PMMA head phantom (diameter of 16 cm) and exposed in the axial mode with collimation of 9 mm, 250 mAs and 120 kV. The results have shown that the MOSkin response was linear with doses in the CT range and reproducible (98.52%). The sensitivity for a single MOSkin in mV/cGy was as follows: 9.208, 7.691 and 6.723 for the RQT 8, RQT 9 and RQT 10 beams qualities respectively. The energy dependence varied up to a factor of ±1.19 among those energies and angular dependence was not greater than 7.78% within the angle range from 0 to 90 degrees. The accumulated dose and the CPMMA, 100 value were 3,97 and 3,79 cGy respectively, which were statistically equivalent within the 95% confidence level. The MOSkin was shown to be a good alternative for CT dose profile measurements and more than adequate to provide accumulated dose assessments for CT procedures.

Keywords: computed tomography dosimetry, MOSFET, MOSkin, semiconductor dosimetry

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Authors: Lekshmi Vijayan, K. Shreekrishna Kumar

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We demonstrated an organic field effect transistor based photodetector using phthalocyanine as the active material that exhibited high photosensitivity under varying light wavelengths. The thermally grown SiO₂ layer on silicon wafer act as a substrate. The critical parameters, such as photosensitivity, responsivity and detectivity, are comparatively high and were 3.09, 0.98AW⁻¹ and 4.86 × 10¹⁰ Jones, respectively, under a bias of 5 V and a monochromatic illumination intensity of 4mW cm⁻². The photodetector has a linear I-V curve with a low dark current. On comparing photoresponse of copper phthalocyanine at four different wavelengths, 560 nm shows better photoresponse and the highest value of photosensitivity is also obtained.

Keywords: photodetector, responsivity, photosensitivity, detectivity

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm

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Authors: A.N. Moulay Khatir, A. Guen-Bouazza, B. Bouazza

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SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator to investigate the influence of fins number on corner effect by analyzing its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current for SOI-single-fin FET, three-fin and five-fin, and we provide a comparison with a Trigate SOI Multi-FinFET structure.

Keywords: SOI, FinFET, corner effect, dual-gate, tri-gate, Multi-Fin FET

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Authors: Samaniego Campoverde José Enrique, Rosero Muñoz Jorge Enrique, Luzcando Narea Lorena Elizabeth

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This paper presents a practical and theoretical model for the operation of the Tesla coil using digital signal processing. The research is based on the analysis of ten scientific papers exploring the development and operation of the Tesla coil. Starting from the Testa coil, several modifications were carried out on the Tesla coil, with the aim of amplifying the digital signal by making use of digital signal processing. To achieve this, an amplifier with a transistor and digital filters provided by MATLAB software were used, which were chosen according to the characteristics of the signals in question.

Keywords: tesla coil, digital signal process, equalizer, graphical environment

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Authors: Anwar H. Jarndal, Ahmed S. Elwakil

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In this paper, a fraction-order model for pad parasitic effect of GaN HEMT on Si substrate is developed and validated. Open de-embedding structure is used to characterize and de-embed substrate loading parasitic effects. Unbiased device measurements are implemented to extract parasitic inductances and resistances. The model shows very good simulation for S-parameter measurements under different bias conditions. It has been found that this approach can improve the simulation of intrinsic part of the transistor, which is very important for small- and large-signal modeling process.

Keywords: fractional-order modeling, GaNHEMT, si-substrate, open de-embedding structure

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Authors: Mourad Hrizi

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In this paper, we study the inverse problem of reconstructing an interior interface D appearing in the elliptic partial differential equation: Δu+χ(D)u=0 from the knowledge of the boundary measurements. This problem arises from a semiconductor transistor model. We propose a new shape reconstruction procedure that is based on the Kohn-Vogelius formulation and the topological sensitivity method. The inverse problem is formulated as a topology optimization one. A topological sensitivity analysis is derived from a function. The unknown subdomain D is reconstructed using a level-set curve of the topological gradient. Finally, we give several examples to show the viability of our proposed method.

Keywords: inverse problem, topological optimization, topological gradient, Kohn-Vogelius formulation

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Authors: Mehdi Saeidmanesh, Razali Ismail

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Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: graphene nanoribbon, field effect transistors, short channel effects, channel length modulation

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Authors: N. Massoum, B. Bouazza

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In this paper, we have developed a numerical simulation model to describe the electrical properties of GaInP MESFET with submicron gate (Lg = 0.5 µm). This model takes into account the three-dimensional (3D) distribution of the load in the short channel and the law effect of mobility as a function of electric field. Simulation software based on a stochastic method such as Monte Carlo has been established. The results are discussed and compared with those of the experiment. The result suggests experimentally that, in a very small gate length in our devices (smaller than 40 nm), short-channel tunneling explains the degradation of transistor performance, which was previously enhanced by velocity overshoot.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, simulation software

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Authors: A. boursali, A. Guen Bouazza, M. Khaouani, Z. Kourdi, B. Bouazza

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This paper presents the design, development and characterization of the devices simulation for X-Band Radar applications. The effect of an InAlN/GaN structure on the RF performance High Electron Mobility Transistor (HEMT) device. Systematic investigations on the small signal as well as power performance as functions of the drain biases are presented. Were improved for X-band applications. The Power Added Efficiency (PAE) was achieved over 23% for X-band. The developed devices combine two InAlN/GaN HEMTs of 30nm gate periphery and exhibited the output power of over 50W. An InAlN/GaN HEMT with 30nm gate periphery was developed and exhibited the output power of over 120W.

Keywords: InAlN/GaN, HEMT, RF analyses, PAE, X-Band, radar

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Authors: A. N. Moulai Khatir

Abstract:

SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number.

Keywords: SOI, finFET, corner effect, dual-gate, tri-gate, BOX, multi-finFET

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Authors: Mohsen Khaledian, Razali Ismail, Mehdi Saeidmanesh, Mahdiar Hosseinghadiry

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A semi-analytical model for impact ionization coefficient of graphene nanoribbon (GNR) is presented. The model is derived by calculating probability of electrons reaching ionization threshold energy Et and the distance traveled by electron gaining Et. In addition, ionization threshold energy is semi-analytically modeled for GNR. We justify our assumptions using analytic modeling and comparison with simulation results. Gaussian simulator together with analytical modeling is used in order to calculate ionization threshold energy and Kinetic Monte Carlo is employed to calculate ionization coefficient and verify the analytical results. Finally, the profile of ionization is presented using the proposed models and simulation and the results are compared with that of silicon.

Keywords: nanostructures, electronic transport, semiconductor modeling, systems engineering

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Authors: Abdalla Mohamed Eblabla

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Due to the high increase and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E, and F are the main techniques for realizing power amplifiers. An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), gallium nitride (GaN), Agilent’s Advanced Design System (ADS), lumped elements

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET

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Authors: Kiran Jose, Anjana J. G., Venu Anand, Aswathi R. Nair

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This work investigates the change in structural, optical, and electrical properties of Zinc Oxynitride (ZnON) thin film when annealed in different atmospheres. ZnON film is prepared by reactively sputtering the Zinc target using argon, oxygen, and nitrogen. The deposited film is annealed for one hour at 3250C in the Vaccum condition and Nitrogen and oxygen atmospheres. XRD and Raman spectroscopy is used to study the structural properties of samples. The current conduction mechanism is examined by extracting voltage versus current characteristics on a logarithmic scale, and the optical response is quantified by analyzing persistent photoconductivity (PPC) behavior. This study proposes the optimum annealing atmosphere for ZnON thin film for a better transistor and photosensor application.

Keywords: Zinc oxynitride, thin film, annealing, DC sputtering

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Authors: L. Ashok Kumar, N. Sujith Kumar

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Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: grid-connected, photovoltaic (PV) systems, transformerless inverter, stray capacitance, common-mode, leakage current, pulse width modulation (PWM)

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Authors: Yu-Hsien Lin, Yu-Ru Lin, Yung-Chun Wu

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This work demonstrates the ultra-thin poly-Si (polycrystalline Silicon) nanowire junctionless thin film transistors (NWs JL-TFT) with nickel silicide contact. For nickel silicide film, this work designs to use two-step annealing to form ultra-thin, uniform and low sheet resistance (Rs) Ni silicide film. The NWs JL-TFT with nickel silicide contact exhibits the good electrical properties, including high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this work also compares the electrical characteristics of NWs JL-TFT with nickel silicide and non-silicide contact. Nickel silicide techniques are widely used for high-performance devices as the device scaling due to the source/drain sheet resistance issue. Therefore, the self-aligned silicide (salicide) technique is presented to reduce the series resistance of the device. Nickel silicide has several advantages including low-temperature process, low silicon consumption, no bridging failure property, smaller mechanical stress, and smaller contact resistance. The junctionless thin-film transistor (JL-TFT) is fabricated simply by heavily doping the channel and source/drain (S/D) regions simultaneously. Owing to the special doping profile, JL-TFT has some advantages such as lower thermal the budget which can integrate with high-k/metal-gate easier than conventional MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), longer effective channel length than conventional MOSFETs, and avoidance of complicated source/drain engineering. To solve JL-TFT has turn-off problem, JL-TFT needs ultra-thin body (UTB) structure to reach fully depleted channel region in off-state. On the other hand, the drive current (Iᴅ) is declined as transistor features are scaled. Therefore, this work demonstrates ultra thin poly-Si nanowire junctionless thin film transistors with nickel silicide contact. This work investigates the low-temperature formation of nickel silicide layer by physical-chemical deposition (PVD) of a 15nm Ni layer on the poly-Si substrate. Notably, this work designs to use two-step annealing to form ultrathin, uniform and low sheet resistance (Rs) Ni silicide film. The first step was promoted Ni diffusion through a thin interfacial amorphous layer. Then, the unreacted metal was lifted off after the first step. The second step was annealing for lower sheet resistance and firmly merged the phase.The ultra-thin poly-Si nanowire junctionless thin film transistors NWs JL-TFT with nickel silicide contact is demonstrated, which reveals high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In silicide film analysis, the second step of annealing was applied to form lower sheet resistance and firmly merge the phase silicide film. In short, the NWs JL-TFT with nickel silicide contact has exhibited a competitive short-channel behavior and improved drive current.

Keywords: poly-Si, nanowire, junctionless, thin-film transistors, nickel silicide

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Authors: T. Bielewicz, S. Dogan, C. Klinke

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Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

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Authors: Sonia Vanessa Campos Moreira

Abstract:

The aim of this research is the production and mechanical properties of Alkali-Activated Inorganic Binders (AAIB) made from The Basic Oxygen Furnace Slag (BOF Slag) and Thin Film Transistor Liquid Crystal Display (TFT-LCD), glass powder (waste and industrial by-products). Many factors have an influence on the production of AAIB like the glass powder finesses, the alkaline equivalent content (AE %), water binder ratios (w/b ratios) and the differences curing process. The findings show different behavior in the AAIB related to the factors mentioned, the best results are given with a glass powder fineness of 4,500 cm²/g, w/b=0.30, a curing temperature of 70 ℃, curing duration of 4 days and an aging duration of 14 days results in the highest compressive strength of 18.51 MPa.

Keywords: alkaline activators, BOF slag, glass powder fineness, TFT-LCD, w/b ratios

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

Abstract:

The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, GaInP

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