Search results for: transconductance

Authors: Rana Mahmoud

Abstract:

This study represents a systematic study of the Operational Transconductance Amplifiers capacitance (OTA-C) filters or as it is often called Gm-C filters. OTA-C filters have been paid a great attention for the last decades. As Gm-C filters operate in an open loop topology, this makes them flexible to perform in low and high frequencies. As such, Gm-C filters can be used in various wireless communication applications. Another property of Gm-C filters is its electronic tunability, thus different filter frequency characteristics can be obtained without changing the inductance and resistance values. This can be achieved by an OTA (Operational Transconductance Amplifier) and a capacitor. By tuning the OTA transconductance, the cut-off frequency will be tuned and different frequency responses are achieved. Different high-order analog filters can be design using Gm-C filters including low pass, high pass and band pass filters. 1st and 2nd order low pass, high pass and band pass filters are presented in this paper.

Keywords: Gm-C, filters, low-pass, high-pass, band-pass

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Authors: Dheeraj Sharma, Santosh Kumar Vishvakarma

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We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product.

Keywords: Gate-All-Around MOSFET, GAA, output resistance, transconductance generation factor, intrinsic gain, cutoff frequency, fT

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Authors: Naima Guenifi, Shiromani Balmukund Rahi, Amina Bechka

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Tunnel FET is one of the most suitable alternatives FET devices for conventional CMOS technology for low-power electronics and applications. Due to its lower subthreshold swing (SS) value, it is a strong follower of low power applications. It is a quantum FET device that follows the band to band (B2B) tunneling transport phenomena of charge carriers. Due to band to band tunneling, tunnel FET is suffering from a lower switching current than conventional metal-oxide-semiconductor field-effect transistor (MOSFET). For improvement of device features and limitations, the newly invented negative capacitance concept of ferroelectric material is implemented in conventional Tunnel FET structure popularly known as NC TFET. The present research work has implemented the idea of high-k gate dielectric added with ferroelectric material on double gate Tunnel FET for implementation of negative capacitance. It has been observed that the idea of negative capacitance further improves device features like SS value. It helps to reduce power dissipation and switching energy. An extensive investigation for circularity uses for digital, analog/RF and linearity features of double gate NCTFET have been adopted here for research work. Several essential designs paraments for analog/RF and linearity parameters like transconductance(gm), transconductance generation factor (gm/IDS), its high-order derivatives (gm2, gm3), cut-off frequency (fT), gain-bandwidth product (GBW), transconductance generation factor (gm/IDS) has been investigated for low power RF applications. The VIP₂, VIP₃, IMD₃, IIP₃, distortion characteristics (HD2, HD3), 1-dB, the compression point, delay and power delay product performance have also been thoroughly studied.

Keywords: analog/digital, ferroelectric, linearity, negative capacitance, Tunnel FET, transconductance

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Authors: D. J. Dahigaonkar, D. G. Wakde

Abstract:

The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper.

Keywords: Operational Transconductance Amplifier, Total Harmonic Distortions, low voltage/low power, power dissipation

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Authors: Suruchi Saini, Hitender Kumar Tyagi

Abstract:

With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: S. Summart, C. Saetiaw, T. Thosdeekoraphat, C. Thongsopa

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This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Keywords: current-mode, quadrature oscillator, block diagram, CDTA

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Authors: Zakarya Kourdi, Mohammed Khaouani, Benyounes Bouazza, Ahlam Guen-Bouazza, Amine Boursali

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In this paper, we have evaluated the thermal effect for high electron mobility transistors (HEMTs) heterostructure InAlN/GaN with a gate length 30nm high-performance. It also shows the analysis and simulated these devices, and how can be used in different application. The simulator Tcad-Silvaco software has used for predictive results good for the DC, AC and RF characteristic, Devices offered max drain current 0.67A; transconductance is 720 mS/mm the unilateral power gain of 180 dB. A cutoff frequency of 385 GHz, and max frequency 810 GHz These results confirm the feasibility of using HEMTs with InAlN/GaN in high power amplifiers, as well as thermal places.

Keywords: HEMT, Thermal Effect, Silvaco, InAlN/GaN

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

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This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: boost converter, current sensing, power-on protection, step-up converter, soft-start

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: A. Boursali, A. Guen-Bouazza

Abstract:

We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

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Authors: Z. Kourdi, B. Bouazza, M. Khaouani, A. Guen-Bouazza, Z. Djennati, A. Boursali

Abstract:

We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/mm, a peak extrinsic transconductance of 590 mS/mm at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, Silvaco, field plate, genetic algorithm, quantum

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Authors: Ajay Kumar, Neha Gupta

Abstract:

This work presents the sensitivity assessment of Gallium Nitride (GaN) material-based FinFET by dielectric modulation in the nanocavity gap for label-free biosensing applications. The significant deflection is observed in the electrical characteristics such as drain current (ID), transconductance (gm), surface potential, energy band profile, electric field, sub-threshold slope (SS), and threshold voltage (Vth) in the presence of biomolecules owing to GaN material. Further, the device sensitivity is evaluated to identify the effectiveness of the proposed biosensor and its capability to detect the biomolecules with high precision or accuracy. Higher sensitivity is observed for Gelatin (k=12) in terms of on-current (SION), threshold voltage (SVth), and switching ratio (SSR) by 104.88%, 82.12%, and 119.73%, respectively. This work is performed using a powerful tool 3D Sentaurus TCAD using a well-calibrated structure. All the results pave the way for GaN-FinFET as a viable candidate for label-free dielectric modulated biosensor applications.

Keywords: biosensor, biomolecules, FinFET, sensitivity

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Authors: Lakrim Abderrazak, Tahri Driss

Abstract:

This paper presents a new behavioural electrothermal model of power Silicon Carbide (SiC) MOSFET under SPICE. This model is based on the MOS model level 1 of SPICE, in which phenomena such as Drain Leakage Current IDSS, On-State Resistance RDSon, gate Threshold voltage VGSth, the transconductance (gfs), I-V Characteristics Body diode, temperature-dependent and self-heating are included and represented using behavioural blocks ABM (Analog Behavioural Models) of Spice library. This ultimately makes this model flexible and easily can be integrated into the various Spice -based simulation softwares. The internal junction temperature of the component is calculated on the basis of the thermal model through the electric power dissipated inside and its thermal impedance in the form of the localized Foster canonical network. The model parameters are extracted from manufacturers' data (curves data sheets) using polynomial interpolation with the method of simulated annealing (S A) and weighted least squares (WLS). This model takes into account the various important phenomena within transistor. The effectiveness of the presented model has been verified by Spice simulation results and as well as by data measurement for SiC MOS transistor C2M0025120D CREE (1200V, 90A).

Keywords: SiC power MOSFET, DC electro-thermal model, ABM Spice library, SPICE modelling, behavioural model, C2M0025120D CREE.

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Authors: M. Kessi

Abstract:

We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

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Authors: Samson Mil'shtein, Dhawal Asthana, Benjamin Sullivan

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The wide energy gap of GaN is the major parameter justifying the design and fabrication of high-power electronic components made of this material. However, the existence of a piezo-electrics in nature sheet charge at the AlGaN/GaN interface complicates the control of carrier injection into the intrinsic channel of GaN HEMTs (High Electron Mobility Transistors). As a result, most of the transistors created as R&D prototypes and all of the designs used for mass production are D-mode devices which introduce challenges in the design of integrated circuits. This research presents the design and modeling of an E-mode GaN HEMT with a very low turn-on voltage. The proposed device includes two critical elements allowing the transistor to achieve zero conductance across the channel when Vg = 0V. This is accomplished through the inclusion of an extremely thin, 2.5nm intrinsic Ga₀.₇₄Al₀.₂₆N spacer layer. The added spacer layer does not create piezoelectric strain but rather elastically follows the variations of the crystal structure of the adjacent GaN channel. The second important factor is the design of a gate metal with a high work function. The use of a metal gate with a work function (Ni in this research) greater than 5.3eV positioned on top of n-type doped (Nd=10¹⁷cm⁻³) Ga₀.₇₄Al₀.₂₆N creates the necessary built-in potential, which controls the injection of electrons into the intrinsic channel as the gate voltage is increased. The 5µm long transistor with a 0.18µm long gate and a channel width of 30µm operate at Vd=10V. At Vg =1V, the device reaches the maximum drain current of 0.6mA, which indicates a high current density. The presented device is operational at frequencies greater than 10GHz and exhibits a stable transconductance over the full range of operational gate voltages.

Keywords: compound semiconductors, device modeling, enhancement mode HEMT, gallium nitride

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