Search results for: dual material gate

Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET

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Authors: Porag Jyoti Ligira, Gargi Khanna

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The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthreshold slope of ~60 mV/decade can be achieved by using highk dielectric. The effects of variation of spacer length and material on the electrical characteristic of BPJLT are also investigated in the paper. The ION / IOFF ratio improvement is of the order of 107 and the OFF current reduction of 10-4 is obtained by using gate dielectric of HfO2 instead of SiO2.

Keywords: spacer, BPJLT, high-k, double gate

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Authors: Mahendrapal Singh Pachlaniya, Laxmi Kumre

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The AOI (AND – OR- INVERTER) based design of XOR gate is proposed in this paper with less number of gates. This new XOR gate required four basic gates and basic gate include only AND, OR, Inverter (AOI). Conventional XOR gate required five basic gates. Ripple Carry Adder (RCA) used in parallel addition but propagation delay time is large. RCA replaced with Carry Select Adder (CSLA) to reduce propagation delay time. CSLA design with dual RCA considering carry = ‘0’ and carry = ‘1’, so it is not an area efficient adder. To make area efficient, modified CSLA is designed with single RCA considering carry = ‘0’ and another RCA considering carry = ‘1’ replaced with Binary to Excess 1 Converter (BEC). Now replacement of conventional XOR gate by new design of XOR gate in modified CSLA reduces much area compared to regular CSLA and modified CSLA.

Keywords: CSLA, BEC, XOR gate, area efficient

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Authors: Fatima Zohra Rahou, A.Guen Bouazza, B. Bouazza

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SOI TRI GATE FinFET transistors have emerged as novel devices due to its simple architecture and better performance: better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. As the oxide thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the SiO2 gate oxide with a high-κ material allows increased gate capacitance without the associated leakage effects. In this paper, SOI TRI-GATE FinFET structure with use of high K dielectric materials (HfO2) and SiO2 dielectric are simulated using the 3-D device simulator Devedit and Atlas of TCAD Silvaco. The simulated results exhibits significant improvements in the performances of SOI TRI GATE FinFET with gate oxide HfO2 compared with conventional gate oxide SiO2 for the same structure. SOI TRI-GATE FinFET structure with the use of high K materials (HfO2) in gate oxide results into the increase in saturation current, threshold voltage, on-state current and Ion/Ioff ratio while off-state current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, SOI-TRI Gate FinFET, high-K dielectric, Silvaco software

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Authors: Zina Saheb, Ezz El-Masry

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As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

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Authors: Yun-Hsuan Yu, Chi-Shung Tang, Nzar Rauf Abdullah, Vidar Gudmundsson

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Spin-orbit gap feature in energy dispersion of one-dimensional devices is revealed via strong spin-orbit interaction (SOI) effects under Zeeman field. We describe the utilization of a finger-gate or a top-gate to control the spin-dependent transport characteristics in the SOI-Zeeman influenced split-gate devices by means of a generalized spin-mixed propagation matrix method. For the finger-gate system, we find a bound state in continuum for incident electrons within the ultra-low energy regime. For the top-gate system, we observe more bound-state features in conductance associated with the formation of spin-associated hole-like or electron-like quasi-bound states around band thresholds, as well as hole bound states around the reverse point of the energy dispersion. We demonstrate that the spin-dependent transport behavior of a top-gate system is similar to that of a finger-gate system only if the top-gate length is less than the effective Fermi wavelength.

Keywords: spin-orbit, zeeman, top-gate, finger-gate, bound state

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Authors: A. Douara, N. Kermas, B. Djellouli

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In this study, we report calculations of gate capacitance of AlGaN/GaN HEMTs with nextnano device simulation software. We have used a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. These simulations explore various device structures with different values of barrier thickness and channel thickness. A detailed understanding of the impact of gate capacitance in HEMTs will allow us to determine their role in future 10 nm physical gate length node.

Keywords: gate capacitance, AlGaN/GaN, HEMTs, quantum capacitance, centroid capacitance

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Authors: Krishnendra Shekhawat

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Given a graph G = (V, E), a rectangular dual of G represents the vertices of G by a set of interior-disjoint rectangles such that two rectangles touch if and only if there is an edge between the two corresponding vertices in G. Rectangular duals do not exist for every graph, so we can define maximal rectangular duals. A maximal rectangular dual is a rectangular dual of a graph G such that there exists no graph G ′ with a rectangular dual where G is a subgraph of G ′. In this paper, we enumerate all maximal rectangular duals (or, to be precise, the corresponding planar graphs) up to six nodes and presents a necessary condition for the existence of a rectangular dual. This work allegedly has applications in integrated circuit design and architectural floor plans.

Keywords: adjacency, degree sequence, dual graph, rectangular dual

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: A.N. Moulay Khatir, A. Guen-Bouazza, B. Bouazza

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SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator to investigate the influence of fins number on corner effect by analyzing its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current for SOI-single-fin FET, three-fin and five-fin, and we provide a comparison with a Trigate SOI Multi-FinFET structure.

Keywords: SOI, FinFET, corner effect, dual-gate, tri-gate, Multi-Fin FET

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Authors: Nikhil Jain, Yang Xu, Bin Yu

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Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Dheeraj Sharma, Santosh Kumar Vishvakarma

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We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product.

Keywords: Gate-All-Around MOSFET, GAA, output resistance, transconductance generation factor, intrinsic gain, cutoff frequency, fT

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Authors: Roumaissa Derdour, Lebbal Mohamed Redha

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We present a study of the transmission of the all-optical logic gate using a structure connected with a triangular photonic crystal lattice that is improved. The proposed logic gate consists of a photonic crystal nano-resonator formed by changing the size of the air holes. In addition to the simplicity, the response time is very short, and the designed nano-resonator increases the bit rate of the logic gate. The two-dimensional finite difference time domain (2DFDTD) method is used to simulate the structure; the transmission obtained is about 98% with very negligible losses. The proposed photonic crystal AND logic gate is widely used in future integrated optical microelectronics.

Keywords: logic gates, photonic crystals, optical integrated circuits, resonant cavities

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Authors: A. A. Akande, B. P. Dhonge, B. W. Mwakikunga, A. G. J. Machatine

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This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH₄VO₃ precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO₂ (B) with V₂O₅ and an amorphous phase. The BET surface area is found to be 67.67 m²/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO₂ sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO₂ sensors which normally show response and recovery times of the order of 5 minutes (300 s).

Keywords: VO2, VO2(B), MOSFET, gate voltage, humidity sensor

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Authors: S. Slimani, B. Djellouli

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Novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials like Ge is a very promising material due to its high mobility and is being considered to replace Si in the channel to achieve higher drive currents and switching speeds .Various approaches to circumvent the scaling limits to benchmark the performance of nanoscale MOSFETS with different channel materials, the optimized structure is simulated within nextnano in order to highlight the quantum effects on DG MOSFETs when Si is replaced by Ge and SiO2 is replaced by ZrO2 and HfO2as the gate dielectric. The results have shown that Ge MOSFET have the highest mobility and high permittivity oxides serve to maintain high drive current. The simulations show significant improvements compared with DGMOSFET using SiO2 gate dielectric and Si channel.

Keywords: high mobility, high-k, quantum effects, SOI-DGMOSFET

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Authors: A. N. Moulai Khatir

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SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number.

Keywords: SOI, finFET, corner effect, dual-gate, tri-gate, BOX, multi-finFET

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Authors: S. Koul, Joshua Adedamola

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Currently, the global concerning fact about electromagnetic pollution (EMP) is that it not only adversely affects human health but rather projects the malfunctioning of sensitive equipment both locally and at a global level. The market offers many incumbent technologies to solve the issues, but still, a processable sustainable material solution with acceptable limits for GHG emission is still at an exploratory stage. The present work offers a sustainable material solution with a wide range of processability in terms of a polymeric resin matrix and shielding operational efficiency across the electromagnetic spectrum, covering both ionizing and non-ionizing electromagnetic radiations. The present work offers an in-situ synthesized conducting polyaniline (PANI) in the presence of the hybrid dual dopant system with tuned conductivity and high shielding efficiency between 89 to 92 decibels, depending upon the EMI frequency range. The conductive polymer synthesized in the presence of a hybrid dual dopant system via the in-situ emulsion polymerization method offers a higher surface resistance of 1.0 ohms/cm with thermal stability up to 2450C in their powder form. This conductive polymer with a hybrid dual dopant system was used as a filler material with different polymeric thermoplastic resin systems for the preparation of conductive composites. Intrinsically Conductive polymeric (ICP) composites based on hybrid dual dopant systems were prepared using melt blending, extrusion, and finally by, compression molding processing techniques. ICP composites with hybrid dual dopant systems offered good mechanical, thermal, structural, weathering, and stable surface resistivity properties over a period of time. The preliminary shielding behavior for ICP composites between frequency levels of 10 GHz to 24GHZ offered a shielding efficiency of more than 90 dB.

Keywords: ICP, dopant, EMI, shielding

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

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Multi-gate SOI MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with a scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high -k dielectric materials as oxide layer at different places in MOSFET structures. One of the most important multi-gate structures is square GAA SOI MOSFET that is a strong candidate for the next generation nanoscale devices; show an even stronger control of short channel effects. In this paper, GAA SOI MOSFET structure with using high -k dielectrics materials Al2O3 (k~9), HfO2 (k~20), La2O3 (k~30) and metal gate TiN are simulated by using 3-D device simulator DevEdit and Atlas of SILVACO TCAD tools. Square GAA SOI MOSFET transistor with High-k HfO2 gate dielectrics and TiN metal gate exhibits significant improvements performances compared to Al2O3 and La2O3 dielectrics for the same structure. Simulation results of GAA SOI MOSFET transistor with HfO2 dielectric show the increase in saturation current and Ion/Ioff ratio while leakage current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, square GAA SOI MOSFET, high-k dielectric, Silvaco software

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Authors: Birinderjit Singh Kalyan, Inderpreet Kaur, Balwinder Singh Sohi

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In this paper, an equivalent model for floating gate transistor has been proposed. Using the floating gate voltage value, capacitive coupling coefficients has been found at different bias conditions. The amount of charge present on the gate has been then calculated using the transient models of hot electron programming and Fowler-Nordheim Tunnelling. The proposed model can be extended to the transient conditions as well. The SPICE equivalent model is designed and current-voltage characteristics and Transfer characteristics are comparatively analysed. The dc current-voltage characteristics, as well as dc transfer characteristics, have been plotted for an FGMOS with W/L=0.25μm/0.375μm, the inter-poly capacitance of 0.8fF for both programmed and erased states. The Comparative analysis has been made between the present model and capacitive coefficient coupling methods which were already available.

Keywords: FGMOS, floating gate transistor, capacitive coupling coefficient, SPICE model

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Authors: Mitchell Stanton

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Background: Endovascular management is well established as a mainstay treatment option for cerebral aneurysms. It is also well established that immediate post procedural imaging can be difficult to interpret due to the presence of contrast material. However, through the use of Dual-Energy computed tomography, it has become possible to differentiate contrast extravasation and intracranial haemorrhage. This case illustrates the importance of this technology following endovascular treatment of an unruptured cerebral aneurysm. Case Presentation: A 79-year-old female was found to have an unruptured large intracavernous ICA fusiform aneurysm on CT Brain Angiogram after presenting with acute ophthalmoplegia. This ophthalmoplegia was caused by mass effect from the aneurysm and subsequently the aneurysm was treated with an endovascular flow diverting stent. CT brain was performed post operatively due to a reduced level of consciousness and this showed diffuse subarachnoid hyperdensity of the left hemisphere. The use of Dual-Energy CT allowed accurate differentiation and illustrated diffuse contrast material extravasation, allowing patient to continue on dual-antiplatelets and therapeutic anticoagulation to reduce the risk of ischaemic injury post endovascular stent. Conclusion: Endovascular treatment options for management of intracranial aneurysms are constantly evolving. The use of Dual-Energy CT therefore has an integral role in accurately diagnosing any post-operative complications. Specifically, differentiating between subarachnoid haemorrhage and contrast extravasation is vital in these patients due to the significant consequences to their ongoing management in regards to continuation or cessation of antiplatelets or anticoagulation. With increasing access to this technology, its use should become standard practice in the post-operative investigation of these patients undergoing endovascular treatment.

Keywords: aneurysm, computed tomography, contrast extravasation, dual-energy CT, endovascular, subarachnoid haemorrhage

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Authors: Yingxu Wang

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This work presents basic research on the recursive structures and dual sequential patterns of primes for the formal proof of the Twin-Prime Conjecture (TPC). A rigorous methodology of Twin-Prime Decomposition (TPD) is developed in MATLAB to inductively verify potential twins in the dual sequences of primes. The key finding of this basic study confirms that the dual sequences of twin primes are not only symmetric but also infinitive in the unique base 6 cycle, except a limited subset of potential pairs is eliminated by the lack of dual primality. Both theory and experiments have formally proven that the infinity of twin primes stated in TPC holds in the P x P space.

Keywords: number theory, primes, twin-prime conjecture, dual primes (P x P), twin prime decomposition, formal proof, algorithm

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Authors: Ramnath Narhete, Saket Pandey, Puran Gour

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This paper presents of dual-band planner antenna with a compact radiator for 2.4/5.2/5.8 proposed by optimizing its resonant frequency, Bandwidth of operation and radiation frequency using the genetic algorithm. The antenna consists L-shaped and E-shaped radiating element to generate two resonant modes for dual band operation. The above techniques have been successfully used in many applications. Dual band antenna with the compact radiator for 2.4/5.2/5.8 GHz WLAN application design and radiator size only width 8mm and a length is 11.3 mm. The antenna can we used for various application in the field of communication. Genetic algorithm will be used to design the antenna and impedance matching network.

Keywords: genetic algorithm, dual-band E, dual-band L, WLAN, compact radiator

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Authors: Jitendra Pratap, Jonathan Sivyer

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Introduction: Dual energy/Spectral CT scanning permits simultaneous acquisition of two x-ray spectra datasets and can complement radiological diagnosis by allowing tissue characterisation (e.g., uric acid vs. non-uric acid renal stones), enhancing structures (e.g. boost iodine signal to improve contrast resolution), and quantifying substances (e.g. iodine density). However, the latter showed inconsistent results between the 2 main modes of dual energy scanning (i.e. dual source vs. dual layer). Therefore, the present study aimed to determine which technology is more accurate in quantifying iodine density. Methods: Twenty vials with known concentrations of iodine solutions were made using Optiray 350 contrast media diluted in sterile water. The concentration of iodine utilised ranged from 0.1 mg/ml to 1.0mg/ml in 0.1mg/ml increments, 1.5 mg/ml to 4.5 mg/ml in 0.5mg/ml increments followed by further concentrations at 5.0 mg/ml, 7mg/ml, 10 mg/ml and 15mg/ml. The vials were scanned using Dual Energy scan mode on a Siemens Somatom Force at 80kV/Sn150kV and 100kV/Sn150kV kilovoltage pairing. The same vials were scanned using Spectral scan mode on a Philips iQon at 120kVp and 140kVp. The images were reconstructed at 5mm thickness and 5mm increment using Br40 kernel on the Siemens Force and B Filter on Philips iQon. Post-processing of the Dual Energy data was performed on vendor-specific Siemens Syngo VIA (VB40) and Philips Intellispace Portal (Ver. 12) for the Spectral data. For each vial and scan mode, the iodine concentration was measured by placing an ROI in the coronal plane. Intraclass correlation analysis was performed on both datasets. Results: The iodine concentrations were reproduced with a high degree of accuracy for Dual Layer CT scanner. Although the Dual Source images showed a greater degree of deviation in measured iodine density for all vials, the dataset acquired at 80kV/Sn150kV had a higher accuracy. Conclusion: Spectral CT scanning by the dual layer technique has higher accuracy for quantitative measurements of iodine density compared to the dual source technique.

Keywords: CT, iodine density, spectral, dual-energy

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Authors: Carla Pérez-Chirinos Buxadé, Bruno Fernández-Valdés, Mónica Morral-Yepes, Sílvia Tuyà Viñas, Josep Maria Padullés Riu, Gerard Moras Feliu

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There is a long way to explore all the possible applications inertial measurement units (IMUs) have in the sports field. The aim of this study was to evaluate the validity of a new application on the use of these wearable sensors, specifically it was to evaluate a magnet-based timing system (M-BTS) for timing gate-to-gate in an alpine ski slalom using the magnetometer embedded in an IMU. This was a validation study. The criterion validity of time measured by the M-BTS was assessed using the 95% error range against actual time obtained from photocells. The experiment was carried out with first-and second-year junior skiers performing a ski slalom on a ski training slope. Eight alpine skiers (17.4 ± 0.8 years, 176.4 ± 4.9 cm, 67.7 ± 2.0 kg, 128.8 ± 26.6 slalom FIS-Points) participated in the study. An IMU device was attached to the skier’s lower back. Skiers performed a 40-gate slalom from which four gates were assessed. The M-BTS consisted of placing four bar magnets buried into the snow surface on the inner side of each gate’s turning pole; the magnetometer built into the IMU detected the peak-shaped magnetic field when passing near the magnets at a certain speed. Four magnetic peaks were detected. The time compressed between peaks was calculated. Three inter-gate times were obtained for each system: photocells and M-BTS. The total time was defined as the time sum of the inter-gate times. The 95% error interval for the total time was 0.050 s for the ski slalom. The M-BTS is valid for timing gate-to-gate in an alpine ski slalom. Inter-gate times can provide additional data for analyzing a skier’s performance, such as asymmetries between left and right foot.

Keywords: gate crossing time, inertial measurement unit, timing system, wearable sensor

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Authors: Shih-Yan Chen, Shin-Shin Kao

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In this paper, a thorough review about dual-cubes, DCn, the related studies and their variations are given. DCn was introduced to be a network which retains the pleasing properties of hypercube Qn but has a much smaller diameter. In fact, it is so constructed that the number of vertices of DCn is equal to the number of vertices of Q2n +1. However, each vertex in DCn is adjacent to n + 1 neighbors and so DCn has (n + 1) × 2^2n edges in total, which is roughly half the number of edges of Q2n+1. In addition, the diameter of any DCn is 2n +2, which is of the same order of that of Q2n+1. For selfcompleteness, basic definitions, construction rules and symbols are provided. We chronicle the results, where eleven significant theorems are presented, and include some open problems at the end.

Keywords: dual-cubes, dual-cube extensive networks, dual-cube-like networks, hypercubes, fault-tolerant hamiltonian property

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Authors: Tebogo Mabotsa, Tamba Jamiru, David Ibrahim

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Dual phase(DP) steel consists essentially of fine grained equiaxial ferrite and a dispersion of martensite. Martensite is the primary precipitate in DP steels, it is the main resistance to dislocation motion within the material. The objective of this paper is to present a relation between the intercritical annealing holding time and the hardness of a dual phase steel. The initial heat treatment involved heating the specimens to 1000oC and holding the sample at that temperature for 30 minutes. After the initial heat treatment, the samples were heated to 770oC and held for a varying amount of time at constant temperature. The samples were held at 30, 60, and 90 minutes respectively. After heating and holding the samples at the austenite-ferrite phase field, the samples were quenched in water, brine, and oil for each holding time. The experimental results proved that an equation for predicting the hardness of a dual phase steel as a function of the intercritical holding time is possible. The relation between intercritical annealing holding time and hardness of a dual phase steel heat treated at high temperatures is parabolic in nature. Theoretically, the model isdependent on the cooling rate because the model differs for each quenching medium; therefore, a universal hardness equation can be derived where the cooling rate is a variable factor.

Keywords: quenching medium, annealing temperature, dual phase steel, martensite

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Authors: Nikhil Jain, Bin Yu

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We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: P. Geetha, R. S. D. Wahida Banu

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The crowning advances in Silicon based electronic technology have dominated the computation world for the past decades. The captivating performance of Si devices lies in sustainable scaling down of the physical dimensions, by that increasing device density and improved performance. But, the fundamental limitations due to physical, technological, economical, and manufacture features restrict further miniaturization of Si based devices. The pit falls are due to scaling down of the devices such as process variation, short channel effects, high leakage currents, and reliability concerns. To fix the above-said problems, it is needed either to follow a new concept that will manage the current hitches or to support the available concept with different materials. The new concept is to design spintronics, quantum computation or two terminal molecular devices. Otherwise, presently used well known three terminal devices can be modified with different materials that suits to address the scaling down difficulties. The first approach will occupy in the far future since it needs considerable effort; the second path is a bright light towards the travel. Modelling paves way to know not only the current-voltage characteristics but also the performance of new devices. So, it is desirable to model a new device of suitable gate control and project the its abilities towards capability of handling high current, high power, high frequency, short delay, and high velocity with excellent electronic and optical properties. Carbon nanotube became a thriving material to replace silicon in nano devices. A well-planned optimized utilization of the carbon material leads to many more advantages. The unique nature of this organic material allows the recent developments in almost all fields of applications from an automobile industry to medical science, especially in electronics field-on which the automation industry depends. More research works were being done in this area. This paper reviews the carbon nanotube field effect transistor with various gate configurations, number of channel element, CNT wall configurations and different modelling techniques.

Keywords: array of channels, carbon nanotube field effect transistor, double gate transistor, gate wrap around transistor, modelling, multi-walled CNT, single-walled CNT

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Authors: Junhong Feng, Wenyu Lu, Xinhong Cheng, Li Zheng, Yuehui Yu

Abstract:

The effects of proton irradiation on the properties of gate oxide were evaluated by monitoring the static parameters (such as threshold voltage and on-resistance) and dynamic parameters (Miller plateau time) of 1700V SiC VDMOS before and after proton irradiation. The incident proton energy was 3MeV, and the doses were 5 × 10¹² P / cm², 1 × 10¹³ P / cm², respectively. The results show that the threshold voltage of MOS exhibits negative drift under proton irradiation, and the near-interface traps in the gate oxide layer are occupied by holes generated by the ionization effect of irradiation, thus forming more positive charges. The basis for selecting TMiller is that the change time of Vgs is the time when Vds just shows an upward trend until it rises to a stable value. The degradation of the turn-off time of the Miller platform verifies that the capacitance Cgd becomes larger, reflecting that the gate oxide layer is introduced into the trap by the displacement effect caused by proton irradiation, and the interface state deteriorates. As a more sensitive area in the irradiation process, the gate oxide layer will be optimized for its parameters (such as thickness, type, etc.) in subsequent studies.

Keywords: SiC VDMOS, proton radiation, Miller time, gate oxide

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