Search results for: bipolar transistors

Authors: Zakarya Kourdi, Mohammed Khaouani, Benyounes Bouazza, Ahlam Guen-Bouazza, Amine Boursali

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In this paper, we have evaluated the thermal effect for high electron mobility transistors (HEMTs) heterostructure InAlN/GaN with a gate length 30nm high-performance. It also shows the analysis and simulated these devices, and how can be used in different application. The simulator Tcad-Silvaco software has used for predictive results good for the DC, AC and RF characteristic, Devices offered max drain current 0.67A; transconductance is 720 mS/mm the unilateral power gain of 180 dB. A cutoff frequency of 385 GHz, and max frequency 810 GHz These results confirm the feasibility of using HEMTs with InAlN/GaN in high power amplifiers, as well as thermal places.

Keywords: HEMT, Thermal Effect, Silvaco, InAlN/GaN

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Authors: Parisa Khoshvaght, Mehdi Hosseinzadeh

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During the past few years, the Residue Number System (RNS) has been receiving considerable interest due to its parallel and fault-tolerant properties. This system is a useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. One of the drawbacks of Residue Number System is the fractional numbers, that is, the corresponding circuit is very hard to realize in conventional CMOS technology. In this paper, we propose a method in which the numbers of transistors are significantly reduced. The related delay is extremely diminished, in the first glance we use this method to solve concerning problem of one decimal functional number some how this proposition can be extended to generalize the idea. Another advantage of this method is the independency on the kind of moduli.

Keywords: computer arithmetic, residue number system, number system, one-Hot, VLSI

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Authors: Hsin-Ping Huang, Shyankay Jou

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Resistive switching of aluminum nitride (AlNx) thin film was demonstrated in a TaN/AlNx/TiN memory cell that was prepared by sputter deposition techniques. The memory cell showed bipolar switching of resistance between +3.5 V and –3.5 V. The resistance ratio of high resistance state (HRS) to low resistance state (HRS), RHRS/RLRS, was about 2 over 100 cycles of endurance test. Both the LRS and HRS of the memory cell exhibited ohmic conduction at low voltages and Poole-Frenkel emission at high voltages. The electrical conduction in the TaN/AlNx/TiN memory cell was possibly attributed to the interactions between charges and defects in the AlNx film.

Keywords: aluminum nitride, nonvolatile memory, resistive switching, thin films

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Authors: Tae Kyu An

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We demonstrate repurposing linear micropatterns on the CD as a master mold to fabricate TIPS-PEN microwires. From the micropatterns on CDs, we replicated polyurethane acrylate (PUA) templates which are robust and flexible until submicrometer scale patterns. Subsequently, 1.5 μm TIPS-PEN microwires separated by 1.5 μm were grown. Using crystal analysis tools with polarized optical microscopy and X-ray diffraction measurement, it was revealed that each TIPS-PEN microwires are highly crystalline and uniform compared to spin-coated films. It is attributed to the template-guided growth of TIPS-PEN crystals along the linear template, thus the OFETs comprised of TIPS-PEN microwires displayed the high field-effect mobility.

Keywords: compact disk, macro patterning, OFET, soft lithography

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Madina Hamiane

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Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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Authors: V. Swarnalatha, A. V. Narasimha Rao, P. Pal

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The present research reports the investigation of fast etching of silicon for the fabrication of microelectromechanical systems (MEMS) structures using silicon wet bulk micromachining. Low concentration tetramethyl-ammonium hydroxide (TMAH) and hydroxylamine (NH₂OH) are used as main etchant and additive, respectively. The concentration of NH₂OH is varied to optimize the composition to achieve best etching characteristics such as high etch rate, significantly high undercutting at convex corner for the fast release of the microstructures from the substrate, and improved etched surface morphology. These etching characteristics are studied on Si{100} and Si{110} wafers as they are most widely used in the fabrication of MEMS structures as wells diode, transistors and integrated circuits.

Keywords: KOH, MEMS, micromachining, silicon, TMAH, wet anisotropic etching

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Authors: Adriana-Gabriela Plaiasu, Catalin Marian Ducu

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The interest in the unique properties associated with materials having structures on a nanometer scale has been increasing at an exponential rate in last decade. Among the functional mineral compounds such as perovskite (CaTiO3), rutile (TiO2), CaF2, spinel (MgAl2O4), wurtzite (ZnS), zincite (ZnO) and the cupric oxide (CuO) has been used in numerous applications such as catalysis, semiconductors, batteries, gas sensors, biosensors, field transistors and medicine. The Solar Physical Vapor Deposition (SPVD) presented in the paper as elaboration method is an original process to prepare nanopowders working under concentrated sunlight in 2kW solar furnaces. The influence of the synthesis parameters on the chemical and microstructural characteristics of zinc and manganese oxides synthesized nanophases has been systematically studied using XRD, TEM and SEM.

Keywords: characterization, morphological, nano-oxides, structural

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Authors: Ayad Asaad Ibrahim

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Myoelectrically controlled prostheses are becoming more and more popular, for below-elbow amputation, the wrist flexor and extensor muscle group, while for above-elbow biceps and triceps brachii muscles are used for control of the prosthesis. A two site multi-function controller is presented. Two stainless steel bipolar electrode pairs are used to monitor the activities in both muscles. The detected signals are processed by new pre-whitening technique to identify the accurate tension estimation in these muscles. These estimates will activate the relevant prosthesis control signal, with a time constant of 200 msec. It is ensured that the tension states in the control muscle to activate a particular prosthesis function are similar to those used to activate normal functions in the natural hand. This facilitates easier training.

Keywords: prosthesis, biosignal processing, pre-whitening, myoelectric controller

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

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This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, voltage transition, node stabilization, biasing circuits

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Authors: Abdelghafour Galadi

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In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: power MOSFET, drift layer, quasi-saturation effect, SPICE model

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Authors: Anwar Jarndal

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In this paper, a genetic-neural-network (GNN) based large-signal model for GaN HEMTs is presented along with its parameters extraction procedure. The model is easy to construct and implement in CAD software and requires only DC and S-parameter measurements. An improved decomposition technique is used to model self-heating effect. Two GNN models are constructed to simulate isothermal drain current and power dissipation, respectively. The two model are then composed to simulate the drain current. The modeling procedure was applied to a packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation with measured data. A very good agreement between the simulation and measurement is obtained.

Keywords: GaN HEMT, computer-aided design and modeling, neural networks, genetic optimization

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Authors: A. boursali, A. Guen Bouazza, M. Khaouani, Z. Kourdi, B. Bouazza

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This paper presents the design, development and characterization of the devices simulation for X-Band Radar applications. The effect of an InAlN/GaN structure on the RF performance High Electron Mobility Transistor (HEMT) device. Systematic investigations on the small signal as well as power performance as functions of the drain biases are presented. Were improved for X-band applications. The Power Added Efficiency (PAE) was achieved over 23% for X-band. The developed devices combine two InAlN/GaN HEMTs of 30nm gate periphery and exhibited the output power of over 50W. An InAlN/GaN HEMT with 30nm gate periphery was developed and exhibited the output power of over 120W.

Keywords: InAlN/GaN, HEMT, RF analyses, PAE, X-Band, radar

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Authors: Dorota Witkowska, Paweł Gosek, Lukasz Swiecicki, Wojciech Jernajczyk, Bruce J. West, Miroslaw Latka

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In clinical practice, the selection of an antidepressant often degrades to lengthy trial-and-error. In this work we employ a normalized wavelet power of alpha waves as a biomarker of antidepressant treatment response. This novel EEG metric takes into account both non-stationarity and intersubject variability of alpha waves. We recorded resting, 19-channel EEG (closed eyes) in 22 inpatients suffering from unipolar (UD, n=10) or bipolar (BD, n=12) depression. The EEG measurement was done at the end of the short washout period which followed previously unsuccessful pharmacotherapy. The normalized alpha wavelet power of 11 responders was markedly different than that of 11 nonresponders at several, mostly temporoparietal sites. Using the prediction of treatment response based on the normalized alpha wavelet power, we achieved 81.8% sensitivity and 81.8% specificity for channel T4.

Keywords: alpha waves, antidepressant, treatment outcome, wavelet

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

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This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, multi-inputs, voltage transition, node stabilization, biasing circuits

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Authors: Kuan Yu Lin, Shih Chih Chen

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This study focuses on the Al/HfO₂/Si/Al structure to explore the electrical properties of the structure. This experiment uses a radio frequency magnetron sputtering system to deposit high dielectric materials on p-type silicon substrates of 1~10 Ω-cm (100). Consider the hafnium dioxide film as a dielectric layer. Post-deposition annealing at 750°C in nitrogen atmosphere. Electron beam evaporation of metallic aluminum is then used to complete the top/bottom electrodes. The metal is post-annealed at 450°C for 20 minutes in a nitrogen environment to complete the MOS component. Its dielectric constant, equivalent oxide layer thickness, oxide layer defects, and leakage current mechanism are discussed. At PDA 750°C-5s, the maximum k value was found to be 21.2, and the EOT was 3.68nm.

Keywords: high-k gate dielectrics, HfO₂, post deposition annealing, RF magnetic

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Authors: Suruchi Saini, Hitender Kumar Tyagi

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With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Chetna Tyagi, Ambuj Tripathi, Devesh Avasthi

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Graphene oxide consists of sp³ hybridization along with sp² hybridization due to the presence of different oxygen-containing functional groups on its edges and basal planes. However, its sp³ / sp² hybridization can be tuned by various methods to utilize it in different applications, like transistors, solar cells and biosensors. Ion beam irradiation can also be one of the methods to optimize sp² and sp³ hybridization ratio for its desirable properties. In this work, graphene oxide films were irradiated with 100 keV Argon ions at different fluences varying from 10¹³ to 10¹⁶ ions/cm². Synchrotron X-ray diffraction measurements showed an increase in crystallinity at the low fluence of 10¹³ ions/cm². Raman spectroscopy performed on irradiated samples determined the defects induced by the ion beam qualitatively. Also, identification of different groups and their removal with different fluences was done using Fourier infrared spectroscopy technique.

Keywords: graphene oxide, ion beam irradiation, spectroscopy, X-ray diffraction

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Authors: Phanumas Khumsat, Chalermchai Janmane

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Low-voltage instrumentation amplifier has been proposed for 3-lead electrocardiogram measurement system. The circuit’s interference rejection technique is based upon common-mode feed-forwarding where common-mode currents have cancelled each other at the output nodes. The common-mode current for cancellation is generated by means of common-mode sensing and emitter or source followers with resistors employing only one transistor. Simultaneously this particular transistor also provides common-mode feedback to the patient’s right/left leg to further reduce interference entering the amplifier. The proposed designs have been verified with simulations in 0.18-µm CMOS process operating under 1.0-V supply with CMRR greater than 80dB. Moreover ECG signals have experimentally recorded with the proposed instrumentation amplifiers implemented from discrete BJT (BC547, BC558) and MOSFET (ALD1106, ALD1107) transistors working with 1.5-V supply.

Keywords: electrocardiogram, common-mode feedback, common-mode feedforward, communication engineering

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

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Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Xuerui Niu, Bolin Wang, Xinchuang Zhang, Xiaohua Ma, Bin Hou, Ling Yang

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The application of discrete GaN-based power switches requires the collaboration of silicon-based peripheral circuit structures. However, the packages and interconnection between the Si and GaN devices can introduce parasitic effects to the circuit, which has great impacts on GaN power transistors. GaN-based monolithic power integration technology is an emerging solution which can improve the stability of circuits and allow the GaN-based devices to achieve more functions. Complementary logic circuits consisting of GaN-based E-mode p-channel heterostructure field-effect transistors (p-HFETs) and E-mode n-channel HEMTs can be served as the gate drivers. E-mode p-HFETs with recessed gate have attracted increasing interest because of the low leakage current and large gate swing. However, they suffer from a poor interface between the gate dielectric and polarized nitride layers. The reliability of p-HFETs is analyzed and discussed in this work. In circuit applications, the inverter is always operated with dynamic gate voltage (VGS) rather than a constant VGS. Therefore, dynamic electrical stress has been simulated to resemble the operation conditions for E-mode p-HFETs. The dynamic electrical stress condition is as follows. VGS is a square waveform switching from -5 V to 0 V, VDS is fixed, and the source grounded. The frequency of the square waveform is 100kHz with the rising/falling time of 100 ns and duty ratio of 50%. The effective stress time is 1000s. A number of stress tests are carried out. The stress was briefly interrupted to measure the linear IDS-VGS, saturation IDS-VGS, As VGS switches from -5 V to 0 V and VDS = 0 V, devices are under negative-bias-instability (NBI) condition. Holes are trapped at the interface of oxide layer and GaN channel layer, which results in the reduction of VTH. The negative shift of VTH is serious at the first 10s and then changes slightly with the following stress time. However, different phenomenon is observed when VDS reduces to -5V. VTH shifts negatively during stress condition, and the variation in VTH increases with time, which is different from that when VDS is 0V. Two mechanisms exists in this condition. On the one hand, the electric field in the gate region is influenced by the drain voltage, so that the trapping behavior of holes in the gate region changes. The impact of the gate voltage is weakened. On the other hand, large drain voltage can induce the hot holes generation and lead to serious hot carrier stress (HCS) degradation with time. The poor-quality interface between the oxide layer and GaN channel layer at the gate region makes a major contribution to the high-density interface traps, which will greatly influence the reliability of devices. These results emphasize that the improved etching and pretreatment processes needs to be developed so that high-performance GaN complementary logics with enhanced stability can be achieved.

Keywords: GaN-based E-mode p-HFETs, dynamic electric stress, threshold voltage, monolithic power integration technology

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Authors: T. Bielewicz, S. Dogan, C. Klinke

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Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

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Authors: X. S. Wu, H. Jia, P. H. Qian, Z. Zhang, H. L. Cai, F. M. Zhang

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A bipolar resistance switching behaviour is detected for a Ti/TiO2-x/Au memristor device, which is fabricated by a masked designed magnetic sputtering. The current dependence of voltage indicates the curve changes slowly and continuously. When voltage pulses are applied to the device, the set and reset processes maintains linearity, which is used to simulate the synapses. We argue that the conduction mechanism of the device is from the oxygen vacancy channel model, and the resistance of the device change slowly due to the reaction between the titanium electrode and the intermediate layer and the existence of a large number of oxygen vacancies in the intermediate layer. Then, Hopfield neural network is constructed to simulate the behaviour of neural network in image processing, and the accuracy rate is more than 98%. This shows that titanium dioxide memristor has a broad application prospect in high performance neural network simulation.

Keywords: memristor fabrication, neuromorphic computing, bionic synaptic application, TiO₂-based

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, GaInP

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Authors: Mahsa Fathollahzadeh

Abstract:

The quick advancement of nanotechnology necessitates the creation of innovative theoretical approaches to elucidate complex experimental findings and forecast novel capabilities of nanodevices. Therefore, over the past ten years, a difficult task in quantum chemistry has been comprehending electron and spin transport in molecular devices. This thorough evaluation presents a comprehensive overview of current research and its status in the field of molecular electronics, emphasizing the theoretical applications to various device types and including a brief introduction to theoretical methods and their practical implementation plan. The subject matter includes a variety of molecular mechanisms like molecular cables, diodes, transistors, electrical and visual switches, nano detectors, magnetic valve gadgets, inverse electrical resistance gadgets, and electron tunneling exploration. The text discusses both the constraints of the method presented and the potential strategies to address them, with a total of 183 references.

Keywords: chemistry, nanotechnology, quantum, molecule, spin

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Authors: Soo Ho Lim, Minju Lee, Dong In Kim, Gi Youn Han, Seunghun Hong, Hyung Wook Kwon

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We report a floating electrode-based bioelectronic tongue mimicking honeybee taste systems for the detection and discrimination of various nutrients. Here, carbon nanotube field effect transistors with floating electrodes (CNT-FET) were hybridized with nanovesicles containing honeybee nutrient receptors, gustatory receptors of Apis mellifera. This strategy enables us to detect nutrient substance with a high sensitivity and selectivity. It could also be utilized for the detection of nutrients in liquid food. This floating electrode-based bioelectronic tongue mimicking insect taste systems can be a simple, but highly effective strategy in many different basic research areas about sensory systems. Moreover, our research provides opportunities to develop various applications such as food screening, and it also can provide valuable insights on insect taste systems.

Keywords: taste system, CNT-FET, insect gustatory receptor, biolelectronic tongue

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Authors: L. Giraudet, O. Simonetti, G. de Tournadre, N. Dumelié, B. Clarenc, F. Reisdorffer

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In this paper we intend to give a comprehensive view of the saturation misbehavior of thin film transistors (TFTs) based on disordered semiconductors, such as most organic TFTs, and its link to the field activation of the mobility. Experimental evidence of the field activation of the mobility is given for disordered semiconductor based TFTs, when reducing the gate length. Saturation misbehavior is observed simultaneously. Advanced transport models have been implemented in a quasi-2D numerical TFT simulation software. From the numerical simulations it is clearly established that field activation of the mobility alone cannot explain the saturation misbehavior. Evidence is given that high longitudinal field gradient at the drain end of the channel is responsible for an excess charge accumulation, preventing saturation. The two combined effects allow reproducing the experimental output characteristics of short channel TFTs, with S-shaped characteristics and saturation failure.

Keywords: mobility field activation, numerical simulation, OTFT, saturation failure

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Authors: Khaled A. Madi, Abdulalhakim O. Naji, Hassouna A. Aalaoh, Elmahdi Eldeeb

Abstract:

Solar energy is one of the cleanest energy sources with no environmental impact. Due to rapid increase in industrial as well as domestic needs, solar energy becomes a good candidate for safe and easy to handle energy source, especially after it becomes available due to reduction of manufacturing price. The main part of the solar inverter system is the inverter where the DC is inverted to AC, where we try to minimize the loss of power to the minimum possible level by the use of microcontroller. In this work, a deep investigation is made experimentally as well as theoretically for a microcontroller based variable frequency power inverter. The microcontroller will provide the variable frequency Pulse Width Modulation (PWM) signal that will control the switching of the gate of the Insulating Gate Bipolar Transistor (IGBT) with less harmonics at the output of power inverter which can be fed to the public grid at high quality. The proposed work for single phase as well as three phases is also simulated using Matlab/Simulink where we found a good agreement between the simulated and the practical results, even though the experimental work were done in the laboratory of the academy.

Keywords: solar, inverter, PV, solar inverter system

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