Search results for: VHDL

Authors: Ankit Shai

Abstract:

CRC or Cyclic Redundancy Check is one of the most common, and one of the most powerful error-detecting codes implemented on modern computers. Most of the modern communication protocols use some error detection algorithms in digital networks and storage devices to detect accidental changes to raw data between transmission and reception. Cyclic Redundancy Check, or CRC, is the most popular one among these error detection codes. CRC properties are defined by the generator polynomial length and coefficients. The aim of this project is to implement an efficient FPGA based CRC-8 that accepts a 32 bit input, taking into consideration optimal chip area and high performance, using VHDL. The proposed architecture is implemented on Xilinx ISE Simulator. It is designed while keeping in mind the hardware design, complexity and cost factor.

Keywords: cyclic redundancy checker, CRC-8, 32-bit input, FPGA, VHDL, ModelSim, Xilinx

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

Abstract:

Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Anirudh Bhaikhel

Abstract:

The exclusive objective of this paper is to develop a device which can pass on the interpreted result of the sensed information to the interfaced communicable devices to avoid or minimise accidents. This device may also be used in case of emergencies like kidnapping, robberies, medical emergencies etc. The present era has seen a rapid metamorphosis in the automobile industry with increasing use of technology and speed. The increase in purchasing power of customers and price war of automobile companies has made an easy access to the automobile users. The use of automobiles has increased tremendously in last 4-5 years thus causing traffic congestions and thus making vehicles more prone to accidents. This device can be an effective measure to counteract cases of abduction. Risks of accidents can be decreased tremendously through the notifications received by these alerts. It will help to detect the upcoming emergencies. This paper includes the simulation of the communication and sensing device required in automobiles using VHDL.

Keywords: automobiles, communication, component, cyclic redundancy check (CRC), modulo-2 arithmetic, parity bits, receiver, sensors, transmitter, turns, VHDL (VHSIC hardware descriptive language)

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Authors: Khaled Shehata, Hanady Hussien, Sara Yehia

Abstract:

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Keywords: RSA, VHDL, FPGA, modular multiplication, modular exponential

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Authors: Rehab I. Abdul Rahman, Mazhar B. Tayel

Abstract:

This paper presents a method of hardening the 8051 microcontroller, that able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 microcontroller, Hamming code protection was used in its SRAM memory and registers. A VHDL code and its simulation have been used for this hamming code protection.

Keywords: radiation, hardening, bitflip, hamming

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Authors: Rozita Borhan, Lam Kien Sieng

Abstract:

This paper describes I²C Slave implementation using I²C master obtained from the OpenCores website. This website provides free Verilog and VHDL Codes to users. The design implementation for the I²C slave is in Verilog Language and uses EDA tools for ASIC design known as ModelSim from Mentor Graphic. This tool is used for simulation and verification purposes. Common application for this I²C Master-Slave integration is also included. This paper also addresses the advantages and limitations of the said design.

Keywords: I²C, master, OpenCores, slave, Verilog, verification

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Authors: Hanan Mikhael Dawood, Haider Salim, Jafar Al-Wash

Abstract:

This paper presents Proportional-Integral (PI) controller to improve the system performance which gives better torque and flux response. In addition, it reduces the undesirable torque ripple. The conventional DTC controller approach for induction machines, based on an improved torque and stator flux estimator, is implemented using Xilinx System Generator (XSG) for MATLAB/Simulink environment through Xilinx blocksets. The design was achieved in VHDL which is based on a MATLAB/Simulink simulation model. The hardware in the loop results are obtained considering the implementation of the proposed model on the Xilinx NEXYS2 Spartan 3E1200 FG320 Kit.

Keywords: induction motor, Direct Torque Control (DTC), Xilinx FPGA, motor drive

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Authors: L. Hassaine, A. Mraoui, M. R. Bengourina

Abstract:

In photovoltaic system, connected to the grid, the main goal is to control the power that the inverter injects into the grid from the energy provided by the photovoltaic generator. This paper proposes a control technique for a photovoltaic system connected to the grid based on the digital pulse-width modulation (DSPWM) which can synchronise a sinusoidal current output with a grid voltage and generate power at unity power factor. This control is based on H-Bridge inverter controlled by bipolar PWM Switching. The electrical scheme of the system is presented. Simulations results of output voltage and current validate the impact of this method to determinate the appropriate control of the system. A digital design of a generator PWM using VHDL is proposed and implemented on a Xilinx FPGA.

Keywords: grid connected photovoltaic system, H-Bridge inverter, control, bipolar PWM

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Authors: Sergio Saponara, Luca Fanucci, Riccardo Cassettari, Ruggero Piernicola, Marco Righetto

Abstract:

The paper presents an innovative networked radar system for detection of obstacles in a railway level crossing scenario. This Monitoring System (MS) is able to detect moving or still obstacles within the railway level crossing area automatically, avoiding the need of human presence for surveillance. The MS is also connected to the National Railway Information and Signaling System to communicate in real-time the level crossing status. The architecture is compliant with the highest Safety Integrity Level (SIL4) of the CENELEC standard. The number of radar sensors used is configurable at set-up time and depends on how large the level crossing area can be. At least two sensors are expected and up four can be used for larger areas. The whole processing chain that elaborates the output sensor signals, as well as the communication interface, is fully-digital, was designed in VHDL code and implemented onto a Xilinx Virtex 6.

Keywords: radar for safe mobility, railroad crossing, railway, transport safety

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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Authors: Tayab D. Memon, Shahji Farooque, Marvi Deshi, Imtiaz Hussain Kalwar, B. S. Chowdhry

Abstract:

Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this paper, an optimized adder module for ternary quantized sigma-delta modulated signal is presented. The adder is simulated using ModelSim for functional verification the area-performance of the proposed adder were obtained through synthesis in Xilinx and compared to conventional adder trees. The synthesis results show that the proposed adder tree achieves higher clock rates and lower chip area at higher inputs to the adder block; whereas conventional adder tree achieves better performance and lower chip area at lower number of inputs to the same adder block. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Keywords: short word length (SWL), DSP algorithms, FPGA, SBTFF, VHDL

Procedia PDF Downloads 314