Search results for: network on chip

Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

Abstract:

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: WiNoC, simulation tool, network-on-chip, SoC

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

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Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum

Abstract:

3D technology can lead to a significant reduction in power and average hop-count in Networks on Chip (NoCs). It offers short and fast vertical links which copes with the long wire problem in 2D NoCs. This work proposes heuristic-based method to optimize number and placement of vertical links to achieve specified performance goals. Experiments show that significant improvement can be achieved by using a specific number of vertical interconnect.

Keywords: interconnect optimization, monolithic inter-tier vias, network on chip, system on chip, through silicon vias, three dimensional integration circuits

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Authors: Vinayaga Jagadessh Raja, R. Ganesan, S. Ramesh Kumar

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An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system on- chip (SoC) is due to the interconnection scheme. In information, as equipment shrinks, the power contributes of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of clock gating in the data encoding techniques as a viable way to reduce both power dissipation and time consumption of NoC links. The projected scramble scheme exploits the wormhole switching techniques. That is, flits are scramble by the network interface (NI) before they are injected in the network and are decoded by the target NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers structural design is required. We review the projected scramble scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links.

Keywords: Xilinx 12.1, power consumption, Encoder, NOC

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Mark Davey

Abstract:

Communications on a Network on Chip (NoC) produce timing information, i.e., network injection delays, packet traversal times, throughput metrics, and other attributes relating to the traffic being sent across the chip. The security requirements of a platform encompass each node to operate with confidentiality, integrity, and availability (ISO 27001). Inherently, a shared NoC interconnect is exposed to analysis of timing patterns created by contention for the network components, i.e., links and switches/routers. This phenomenon is defined as information leakage, which represents a ‘side channel’ of sensitive information that can be correlated to platform activity. The key algorithm presented in this paper evaluates how an adversary can control two platform neighbouring nodes of a target node to obtain sensitive information about communication with the target node. The actual information obtained is the period value of a periodic task communication. This enacts a breach of the expected confidentiality of a node operating in a multiprocessor platform. An experimental investigation of the side channel is undertaken to judge the level and significance of inferred information produced by access times to the NoC. Results are presented with a series of expanding task set scenarios to evaluate the efficacy of the side channel detection algorithm as the network load increases.

Keywords: embedded systems, multiprocessor, network on chip, side channel

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Authors: Farnaz Fotovvatikhah, Javad Akbari

Abstract:

Test time of a test architecture is an important factor which depends on the architecture's delay and test patterns. Here a new architecture to store the test results based on network on chip is presented. In addition, simple analytical model is proposed to calculate link test time for built in self-tester (BIST) and external tester (Ext) in multiprocessor systems. The results extracted from the model are verified using FPGA implementation and experimental measurements. Systems consisting 16, 25, and 36 processors are implemented and simulated and test time is calculated. In addition, BIST and Ext are compared in terms of test time at different conditions such as at different number of test patterns and nodes. Using the model the maximum frequency of testing could be calculated and the test structure could be optimized for high speed testing.

Keywords: test, nano on-chip network, JTAG, modelling

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: methodology, flip chip, bump cell, LEF, astro, calibre, SCHEME, TCL

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Authors: Long Kim Vu

Abstract:

The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

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Authors: Bhuvnesh Narayanan, Bernhard Weiss, Tvrtko Mandic, Adrijan Baric

Abstract:

This paper discusses a method to reconstruct internal high-frequency signals through subsampling techniques in an IC using an on-chip sensor. Though there are existing methods to internally probe and reconstruct high frequency signals through subsampling techniques; these methods have been applicable mainly for synchronized systems. This paper demonstrates a method for making such non-intrusive on-chip reconstructions possible also in non-synchronized systems. The TLP pulse is used to demonstrate the experimental validation of the concept. The on-chip sensor measures the voltage in an internal node. The jitter in the input pulse causes a varying pulse delay with respect to the on-chip sampling command. By measuring this pulse delay and by correlating it with the measured on-chip voltage, time domain waveforms can be reconstructed, and the influence of the pulse on the internal nodes can be better understood.

Keywords: on-chip sensor, jitter, transmission line pulse, subsampling

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Authors: P. G. Kaviya, B. Muthupandian, R. Ganesan

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On-chip routers typically have buffers are used input or output ports for temporarily storing packets. The buffers are consuming some router area and power. The multiple queues in parallel as in VC router. While running a traffic trace, not all input ports have incoming packets needed to be transferred. Therefore large numbers of queues are empty and others are busy in the network. So the time consumption should be high for the high traffic. Therefore using a RoShaQ, minimize the buffer area and time The RoShaQ architecture was send the input packets are travel through the shared queues at low traffic. At high load traffic the input packets are bypasses the shared queues. So the power and area consumption was reduced. A parallel cross bar architecture is proposed in this project in order to reduce the power consumption. Also a new adaptive weighted routing algorithm for 8-port router architecture is proposed in order to decrease the delay of the network on chip router. The proposed system is simulated using Modelsim and synthesized using Xilinx Project Navigator.

Keywords: buffer, RoShaQ architecture, shared queue, VC router, weighted routing algorithm

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Authors: J. Shiue, I. H. Chen, S. W. Y. Chiu, Y. L. Wang

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In this work, we present a nondestructive method to characterize bacteria in a TEM system. Unlike the conventional TEM specimen preparation method, which needs to thin the specimen in a destructive way, or spread the samples on a tiny millimeter sized carbon grid, our method is easy to operate without the need of sample pretreatment. With a specially designed transparent chip that allows the electron beam to pass through, and a custom made chip holder to fit into a standard TEM sample holder, the bacteria specimen can be easily prepared on the chip without any pretreatment, and then be observed under TEM. The centimeter-sized chip is covered with Au nanoparticles in the surface as the markers which allow the bacteria to be observed easily on the chip. We demonstrate the success of our method by using E. coli as an example, and show that high-resolution TEM images of E. coli can be obtained with the method presented. Some E. coli morphology characteristics imaged using this method are also presented.

Keywords: bacteria, chip, nanoparticles, TEM

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Authors: D. Dorota

Abstract:

This paper presents a method to generate and schedule task in the architecture of embedded systems based on the simulated annealing. This method takes into account the attribute of divisibility of tasks. A proposal represents the process in the form of trees. Despite the fact that the architecture of Network-on-Chip (NoC) is an interesting alternative to a bus architecture based on multi-processors systems, it requires a lot of work that ensures the optimization of communication. This paper proposes an effective approach to generate dedicated NoC topology solving communication problems. Network NoC is generated taking into account the energy consumption and resource issues. Ultimately generated is minimal, dedicated NoC topology. The proposed solution is assumed to be a simple router design and the minimum number of lines.

Keywords: Network-on-Chip, NoC-based embedded systems, scheduling task in embedded systems, simulated annealing

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Authors: Mahdiar Hosseinghadiry, Razali Ismail, F. Fotovati

Abstract:

One of the most important and challenging tasks in testing network-on-chip based system-on-chips (NoC based SoCs) is to verify the communication entity. It is important because of its usage for transferring both data packets and test patterns for intellectual properties (IPs) during normal and test mode. Hence, ensuring of NoC reliability is required for reliable IPs functionality and testing. On the other hand, it is challenging due to the required time to test it and the way of transferring test patterns from the tester to the NoC components. In this paper, two testing techniques for mesh-based NoC interconnections are proposed. The first one is based on one-by-one testing and the second one divides NoC interconnects into three parts, horizontal links of switches in even columns, horizontal links of switches in odd columns and all vertical. A design for testability (DFT) architecture is represented to send test patterns directly to each switch under test and also support the proposed testing techniques by providing a loopback path in each switch. The simulation results shows the second proposed testing mechanism outperforms in terms of test time because this method test all the interconnects in only three phases, independent to the number of existed interconnects in the network, while test time of other methods are highly dependent to the number of switches and interconnects in the NoC.

Keywords: on chip, interconnection testing, horizontal-vertical testing, enhanced unicast

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Authors: M. K. Benhaoua, A. E. H. Benyamina, T. Djeradi, P. Boulet

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In this paper, we propose adaptive routing that considers the routing of communications in order to optimize the overall performance. The routing technique uses a newly proposed Algorithm to route communications between the tasks. The routing we propose of the communications leads to a better optimization of several performance metrics (time and energy consumption). Experimental results show that the proposed routing approach provides significant performance improvements when compared to those using static routing.

Keywords: multi-processor systems-on-chip (mpsocs), network-on-chip (noc), heterogeneous architectures, adaptive routin

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Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

Abstract:

High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: integration, electrokinetic, on-chip, fluid pumping, microfluidic

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Authors: Martin Pumera

Abstract:

Graphene materials are being widely used in electrochemistry due to their versatility and excellent properties as platforms for biosensing. Here we present current trends in the electrochemical biosensing of pesticides and other toxic compounds. We explore two fundamentally different designs, (i) using graphene and other 2-D nanomaterials as an electrochemical platform and (ii) using these nanomaterials in the laboratory on chip design, together with paramagnetic beads. More specifically: (i) We explore graphene as transducer platform with very good conductivity, large surface area, and fast heterogeneous electron transfer for the biosensing. We will present the comparison of these materials and of the immobilization techniques. (ii) We present use of the graphene in the laboratory on chip systems. Laboratory on the chip had a huge advantage due to small footprint, fast analysis times and sample handling. We will show the application of these systems for pesticide detection and detection of other toxic compounds.

Keywords: graphene, 2D nanomaterials, biosensing, chip design

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Authors: M. K. Benhaoua, A. K. Singh, A. E. H. Benyamina

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In this paper, we propose heuristic for dynamic communications mapping that considers the placement of communications in order to optimize the overall performance. The mapping technique uses a newly proposed Algorithm to place communications between the tasks. The placement we propose of the communications leads to a better optimization of several performance metrics (time and energy consumption). Experimental results show that the proposed mapping approach provides significant performance improvements when compared to those using static routing.

Keywords: Multi-Processor Systems-on-Chip (MPSoCs), Network-on-Chip (NoC), heterogeneous architectures, dynamic mapping heuristics

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Authors: Mohsen Marani Barzani, Ahmed A. D. Sarhan, Saeed Farahany, Ramesh Singh

Abstract:

Surface roughness and chip morphology are important output in manufacturing product. In this paper, an experimental investigation was conducted to determine the effects of various cutting speeds and feed rates on surface roughness and chip morphology in turning the Al-Si cast alloy and Sr-containing. Experimental trials carried out using coated carbide inserts. Experiments accomplished under oblique dry cutting when various cutting speeds 70, 130 and 250 m/min and feed rates of 0.05, 0.1 and 0.15 mm/rev were used, whereas depth of cut kept constant at 0.05 mm. The results showed that Sr-containing Al-Si alloy have poor surface roughness in comparison to Al-Si alloy (base alloy). The surface roughness values reduce with cutting speed increment from 70 to 250 m/min. the size of chip changed with changing silicon shape in Al matrix. Also, the surface finish deteriorated with increase in feed rate from 0.5 mm/rev to 0.15 mm/rev.

Keywords: strontium, surface roughness, chip, morphology, turning

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Authors: M. Benghersallah, L. Boulanouar, G. List, G. Sutter

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The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000 and 1200 m / min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. In these experiments, the chip shape was systematically investigated at each cutting conditions using optical microscopy. The chips produced were collected and polished to measure the thicknesses t2max and t2min, dch the distance between each segments and ɸseg the inclination angle As described in the introduction part, the shear angle f and the inclination angle of a segment ɸseg are differentiated. The angle ɸseg is actually measured on the collected chips while the shear angle f cannot be. The angle ɸ represents the initial shear similar to the one that describes the formation of a continuous chip in the primary shear zone. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: dry high speed, orthogonal turning, chip formation, cutting speed, cutting forces

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

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A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: M. Benghersallah, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000, and 1200 m/min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: titanium alloy, dry hjgh speed turning, wear insert, MQL technique

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Authors: Moaz H. Ali, Ahmed H. Al-Saadi

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Most of the materials used in the industry of aero-engine components generally consist of titanium alloys. Advanced materials, because of their excellent combination of high specific strength, lightweight, and general corrosion resistance. In fact, chemical wear resistance of aero-engine alloy provide a serious challenge for cutting tool material during the machining process. The reduction in cutting temperature distributions leads to an increase in tool life and a decrease in wear rate. Hence, the chip morphology and segmentation play a predominant role in determining machinability and tool wear during the machining process. The result of low thermal conductivity and diffusivity of this alloy in the concentration of high temperatures at the tool-work-piece and tool-chip interface. Consequently, the chip morphology is very important in the study of machinability of metals as well as the study of cutting tool wear. Otherwise, the result will be accelerating tool wear, increasing manufacturing cost and time consuming.

Keywords: machinability, titanium alloy (ti-6al-4v), chip formation, milling process

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Authors: Khyamling Parane, B. M. Prabhu Prasad, Basavaraj Talawar

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Fast simulations are critical in reducing time to market in CMPs and SoCs. Several simulators have been used to evaluate the performance and power consumed by Network-on-Chips. Researchers and designers rely upon these simulators for design space exploration of NoC architectures. Our experiments show that simulating large NoC topologies take hours to several days for completion. To speed up the simulations, it is necessary to investigate and optimize the hotspots in simulator source code. Among several simulators available, we choose Booksim2.0, as it is being extensively used in the NoC community. In this paper, we analyze the cache and memory system behaviour of Booksim2.0 to accurately monitor input dependent performance bottlenecks. Our measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having least misses has been identified. To further reduce the cache misses, we use software optimization techniques such as removal of unused functions, loop interchanging and replacing post-increment operator with pre-increment operator for non-primitive data types. The cache misses were reduced by 18.52%, 5.34% and 3.91% by employing above technology respectively. We also employ thread parallelization and vectorization to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93x and 3.97x were observed for the Mesh topology with 30 × 30 network size by employing thread parallelization and vectorization respectively.

Keywords: cache behaviour, network-on-chip, performance profiling, vectorization

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Authors: D. O. Ramadan, R. S. Dwyer-Joyce

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The measurement of the interface conditions in a cutting tool contact is essential information for performance monitoring and control. This interface provides the path for the heat flux to the cutting tool. This elevate in the cutting tool temperature leads to motivate the mechanism of tool wear, thus affect the life of the cutting tool and the productivity. This zone is representative by the tool-chip interface. Therefore, understanding and monitoring this interface is considered an important issue in machining. In this paper, an acoustic emission (AE) technique was used to find the correlation between AE parameters and the tool-chip interface. For this reason, a response surface design (RSD) has been used to analyse and optimize the machining parameters. The experiment design was based on the face centered, central composite design (CCD) in the Minitab environment. According to this design, a series of orthogonal cutting experiments for different cutting conditions were conducted on a Triumph 2500 lathe machine to study the sensitivity of the acoustic emission (AE) signal to change in tool-chip contact length. The cutting parameters investigated were the cutting speed, depth of cut, and feed and the experiments were performed for 6082-T6 aluminium tube. All the orthogonal cutting experiments were conducted unlubricated. The tool-chip contact area was investigated using a scanning electron microscope (SEM). The results obtained in this paper indicate that there is a strong dependence of the root mean square (RMS) on the cutting speed, where the RMS increases with increasing the cutting speed. A dependence on the tool-chip contact length has been also observed. However there was no effect observed of changing the cutting depth and feed on the RMS. These dependencies have been clarified in terms of the strain and temperature in the primary and secondary shear zones, also the tool-chip sticking and sliding phenomenon and the effect of these mechanical variables on dislocation activity at high strain rates. In conclusion, the acoustic emission technique has the potential to monitor in situ the tool-chip interface in turning and consequently could indicate the approaching end of life of a cutting tool.

Keywords: Acoustic emission, tool-chip interface, orthogonal cutting, monitoring

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Authors: Laura Boschis, Elena D. Ozzello, Enzo Mastromatteo

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Point of care diagnostic finds growing interest in medicine and agri-food because of faster intervention and prevention. EliChip is a microfluidic platform to perform Point of Care immunoenzymatic assay based on ready-to-use kits and a portable instrument to manage fluidics and read reliable quantitative results. Thanks to miniaturization, analyses are faster and more sensible than conventional ELISA. EliChip is one of the crucial assets of the Europen-founded Flamingo project for in-line measuring inflammatory markers.

Keywords: lab on chip, point of care, immunoenzymatic analysis, synovial arthritis

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Authors: Ş. Karabulut, A. Güllü, A. Güldaş, R. Gürbüz

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This study investigates the effects of the lead angle and chip thickness variation on surface roughness during the machining of compacted graphite iron using ceramic cutting tools under dry cutting conditions. Analytical models were developed for predicting the surface roughness values of the specimens after the face milling process. Experimental data was collected and imported to the artificial neural network model. A multilayer perceptron model was used with the back propagation algorithm employing the input parameters of lead angle, cutting speed and feed rate in connection with chip thickness. Furthermore, analysis of variance was employed to determine the effects of the cutting parameters on surface roughness. Artificial neural network and regression analysis were used to predict surface roughness. The values thus predicted were compared with the collected experimental data, and the corresponding percentage error was computed. Analysis results revealed that the lead angle is the dominant factor affecting surface roughness. Experimental results indicated an improvement in the surface roughness value with decreasing lead angle value from 88° to 45°.

Keywords: CGI, milling, surface roughness, ANN, regression, modeling, analysis

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Authors: Junior Nomani

Abstract:

This paper presents a novel approach to modelling the metal cutting of duplex stainless steels, a two-phase alloy regarded as a difficult-to-machine material. Calculation and control of shear strain and stresses during cutting are essential to achievement of ideal cutting conditions. Too low or too high leads to higher required cutting force or excessive heat generation causing premature tool wear failure. A 2D finite element cutting model was created based on electron backscatter diffraction (EBSD) data imagery of duplex microstructure. A mesh was generated using ‘object-oriented’ software OOF2 version V2.1.11, converting microstructural images to quadrilateral elements. A virtual workpiece was created on ABAQUS modelling software where a rigid body toolpiece advanced towards workpiece simulating chip formation, generating serrated edge chip formation cutting. Model results found calculated stress strain contour plots correlated well with similar finite element models tied with austenite stainless steel alloys. Virtual chip form profile is also similar compared experimental frozen machining chip samples. The output model data provides new insight description of strain behavior of two phase material on how it transitions from workpiece into the chip.

Keywords: Duplex stainless steel, ABAQUS, OOF2, Chip formation

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Authors: Zhao Bin, Yan Dan Lei

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In this paper, a multi-pattern parallel PRBS generator and a dedicated parallel BER tester is proposed for the 8-Gbps On-chip interconnection testing. A unique full-parallel PRBS checker is also proposed. The proposed design, together with the custom-designed high-speed parallel-to-serial and the serial-to-parallel circuit, will be used to test different on-chip interconnection transceivers. The design is implemented in TSMC 28nm CMOS technology with working voltage at 1.0 V. The serial to parallel ratio is 8:1 so the parallel PRBS generation and BER Tester can be run at lower speed.

Keywords: PRBS, BER, high speed, generator

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Authors: Rafiqul Tarefder, Mohiuddin Ahmad, Mohammad Hossain

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While milling materials from old pavement surface can be an important component of cost effective maintenance operation, their use in maintenance projects are not uniform and well documented. This study documents the different maintenance practices followed by four transportation districts of New Mexico Department of Transportation (NMDOT) in an attempt to find whether millings are being used in maintenance projects by those districts. Based on existing literature, a questionnaire was developed related to six common maintenance practices. NMDOT district personal were interviewed face to face to discuss and get answers to that questionnaire. It revealed that NMDOT districts mainly use chip seal and patching. Other maintenance procedures such as sand seal, scrub seal, slurry seal, and thin overlay have limited use. Two out of four participating districts do not have any documents on chip sealing; rather they employ the experiences of the chip seal crew. All districts use polymer modified high float emulsion (HFE100P) for chip seal with an application rate ranging from 0.4 to 0.56 gallons per square yard. Chip application rate varies from 15 to 40 lb/ square yard. State wide, the thickness of chip seal varies from 3/8" to 1" and life varies from 3 to 10 years. NMDOT districts mainly use three type of patching: pothole, dig-out and blade patch. Pothole patches are used for small potholes and during emergency, dig-out patches are used for all type of potholes sometimes after pothole patching, and blade patch is used when a significant portion of the pavement is damaged. Pothole patches last as low as three days whereas, blade patch lasts as long as 3 years. It was observed that all participating districts use millings in maintenance projects.

Keywords: chip seal, sand seal, scrub seal, slurry seal, overlay, patching, millings

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