Search results for: minimum power consumption.

Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Kenichiro Hida, Shin-Ichi Kuribayashi

Abstract:

In a conventional network, most network devices, such as routers, are dedicated devices that do not have much variation in capacity. In recent years, a new concept of network functions virtualisation (NFV) has come into use. The intention is to implement a variety of network functions with software on general-purpose servers and this allows the network operator to select their capacities and locations without any constraints. This paper focuses on the allocation of NFV-based routing functions which are one of critical network functions, and presents the virtual routing function allocation algorithm that minimizes the total power consumption. In addition, this study presents the useful allocation policy of virtual routing functions, based on an evaluation with a ladder-shaped network model. This policy takes the ratio of the power consumption of a routing function to that of a circuit and traffic distribution between areas into consideration. Furthermore, the present paper shows that there are cases where the use of NFV-based routing functions makes it possible to reduce the total power consumption dramatically, in comparison to a conventional network, in which it is not economically viable to distribute small-capacity routing functions.

Keywords: Virtual routing function, NFV, resource allocation, minimum power consumption.

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Authors: V. Tawiwat, P. Jumnong

Abstract:

Both the minimum energy consumption and smoothness, which is quantified as a function of jerk, are generally needed in many dynamic systems such as the automobile and the pick-and-place robot manipulator that handles fragile equipments. Nevertheless, many researchers come up with either solely concerning on the minimum energy consumption or minimum jerk trajectory. This research paper proposes a simple yet very interesting when combining the minimum energy and jerk of indirect jerks approaches in designing the time-dependent system yielding an alternative optimal solution. Extremal solutions for the cost functions of the minimum energy, the minimum jerk and combining them together are found using the dynamic optimization methods together with the numerical approximation. This is to allow us to simulate and compare visually and statistically the time history of state inputs employed by combining minimum energy and jerk designs. The numerical solution of minimum direct jerk and energy problem are exactly the same solution; however, the solutions from problem of minimum energy yield the similar solution especially in term of tendency.

Keywords: Optimization, Dynamic, Linear Systems, Jerks.

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Authors: V. Eramo, E. Miucci, A. Cianfrani, A. Germoni, M. Listanti

Abstract:

The power consumption of an Optical Packet Switch equipped with SOA technology based Spanke switching fabric is evaluated. Sophisticated analytical models are introduced to evaluate the power consumption versus the offered traffic, the main switch parameters, and the used device characteristics. The impact of Amplifier Spontaneous Emission (ASE) noise generated by a transmission system on the power consumption is investigated. As a matter of example for 32×32 switches supporting 64 wavelengths and offered traffic equal to 0,8, the average energy consumption per bit is 5, 07 · 10-2 nJ/bit and increases if ASE noise introduced by the transmission systems is increased.

Keywords: Spanke, Amplifier Spontaneous Emission Noise, Power Consumption, Optical Packet Switch.

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Authors: Joon-young Jung, Dong-oh Kang, Chang-seok Bae

Abstract:

Power consumption is rapidly increased in data centers because the number of data center is increased and more the scale of data center become larger. Therefore, it is one of key research items to reduce power consumption in data center. The peak power of a typical server is around 250 watts. When a server is idle, it continues to use around 60% of the power consumed when in use, though vendors are putting effort into reducing this “idle" power load. Servers tend to work at only around a 5% to 20% utilization rate, partly because of response time concerns. An average of 10% of servers in their data centers was unused. In those reason, we propose dynamic power management system to reduce power consumption in green data center. Experiment result shows that about 55% power consumption is reduced at idle time.

Keywords: Data Center, Green IT, Management Server, Power Saving.

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Authors: Baghdasaryan Marinka

Abstract:

Monitoring the distribution of electric power consumption in the technological process of ore grinding is conducted. As a result, the impacts of the mill filling rate, the productivity of the ore supply, the volumetric density of the grinding balls, the specific density of the ground ore, and the relative speed of the mill rotation on the specific consumption of electric power have been studied. The power and technological factors affecting the reactive power generated by the synchronous motors, operating within the technological scheme are studied. A block diagram for evaluating the power consumption modes of the technological process is presented, which includes the analysis of the technological scheme, the determination of the place and volumetric density of the ore-grinding mill, the evaluation of the technological and power factors affecting the energy saving process, as well as the assessment of the electric power standards.

Keywords: Electric power standard, factor, ore grinding, power consumption, reactive power, technological.

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Authors: Tawiwat Veeraklaew, Nathasit Phathana-im, Songkit Heama

Abstract:

Both the minimum energy consumption and smoothness, which is quantified as a function of jerk, are generally needed in many dynamic systems such as the automobile and the pick-and-place robot manipulator that handles fragile equipments. Nevertheless, many researchers come up with either solely concerning on the minimum energy consumption or minimum jerk trajectory. This research paper proposes a simple yet very interesting relationship between the minimum direct and indirect jerks approaches in designing the time-dependent system yielding an alternative optimal solution. Extremal solutions for the cost functions of direct and indirect jerks are found using the dynamic optimization methods together with the numerical approximation. This is to allow us to simulate and compare visually and statistically the time history of control inputs employed by minimum direct and indirect jerk designs. By considering minimum indirect jerk problem, the numerical solution becomes much easier and yields to the similar results as minimum direct jerk problem.

Keywords: Optimization, Dynamic, Linear Systems, Jerks.

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Authors: Dong-Woo Lim, Chang-Jae Chun, Hyung-Myung Kim

Abstract:

We consider a two-way relay network where two sources exchange information. A relay helps the two sources exchange information using the decode-and-XOR-forward protocol. We investigate the power minimization problem with minimum rate constraints. The system needs two time slots and in each time slot the required rate pair should be achievable. The power consumption is minimized in each time slot and we obtained the closed form solution. The simulation results confirm that the proposed power allocation scheme consumes lower total power than the conventional schemes.

Keywords: Decode-and-XOR-forward, power minimization, two-way relay

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Authors: M. Yousefi, N. Nasirzadeh

Abstract:

In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm².

Keywords: Comparator, low, power, efficiency.

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Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

Abstract:

This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Tien-Shun Chan, Yung-Chung Chang, Cheng-Yu Chu, Wen-Hui Chen, Yuan-Lin Chen, Shun-Chong Wang, Chang-Chun Wang

Abstract:

98% of the energy needed in Taiwan has been imported. The prices of petroleum and electricity have been increasing. In addition, facility capacity, amount of electricity generation, amount of electricity consumption and number of Taiwan Power Company customers have continued to increase. For these reasons energy conservation has become an important topic. In the past linear regression was used to establish the power consumption models for chillers. In this study, grey prediction is used to evaluate the power consumption of a chiller so as to lower the total power consumption at peak-load (so that the relevant power providers do not need to keep on increasing their power generation capacity and facility capacity). In grey prediction, only several numerical values (at least four numerical values) are needed to establish the power consumption models for chillers. If PLR, the temperatures of supply chilled-water and return chilled-water, and the temperatures of supply cooling-water and return cooling-water are taken into consideration, quite accurate results (with the accuracy close to 99% for short-term predictions) may be obtained. Through such methods, we can predict whether the power consumption at peak-load will exceed the contract power capacity signed by the corresponding entity and Taiwan Power Company. If the power consumption at peak-load exceeds the power demand, the temperature of the supply chilled-water may be adjusted so as to reduce the PLR and hence lower the power consumption.

Keywords: Gery system theory, grey prediction, chller.

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Authors: B. Malarkodi, S. K. Riyaz Hussain, B. Venkataramani

Abstract:

Power consumption of nodes in ad hoc networks is a critical issue as they predominantly operate on batteries. In order to improve the lifetime of an ad hoc network, all the nodes must be utilized evenly and the power required for connections must be minimized. In this project a link layer algorithm known as Power Aware medium Access Control (PAMAC) protocol is proposed which enables the network layer to select a route with minimum total power requirement among the possible routes between a source and a destination provided all nodes in the routes have battery capacity above a threshold. When the battery capacity goes below a predefined threshold, routes going through these nodes will be avoided and these nodes will act only as source and destination. Further, the first few nodes whose battery power drained to the set threshold value are pushed to the exterior part of the network and the nodes in the exterior are brought to the interior. Since less total power is required to forward packets for each connection. The network layer protocol AOMDV is basically an extension to the AODV routing protocol. AOMDV is designed to form multiple routes to the destination and it also avoid the loop formation so that it reduces the unnecessary congestion to the channel. In this project, the performance of AOMDV is evaluated using PAMAC as a MAC layer protocol and the average power consumption, throughput and average end to end delay of the network are calculated and the results are compared with that of the other network layer protocol AODV.

Keywords: AODV, PAMAC, AOMDV, Power consumption.

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Authors: Shuen-Tai Wang, Chin-Hung Li, Ying-Chuan Chen

Abstract:

In recent years there has been renewal of interest in the relation between Green IT and Cloud Computing. The growing use of computers in cloud platform has caused marked energy consumption, putting negative pressure on electricity cost of cloud data center. This paper proposes an effective mechanism to reduce energy utilization in cloud computing environments. We present initial work on the integration of resource and power management that aims at reducing power consumption. Our mechanism relies on recalling virtualization services dynamically according to user-s virtualization request and temporarily shutting down the physical machines after finish in order to conserve energy. Given the estimated energy consumption, this proposed effort has the potential to positively impact power consumption. The results from the experiment concluded that energy indeed can be saved by powering off the idling physical machines in cloud platforms.

Keywords: Green IT, Cloud Computing, virtualization, power consumption.

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Authors: Md. Asif Jahangir Chowdhury, Md. Shahriar Rizwan, M. S. Islam

Abstract:

In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords: variable body biasing, state saving technique, stack effect, dual V-th, static power reduction.

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Authors: Min Kyung An

Abstract:

In Wireless Sensor Networks which consist of tiny wireless sensor nodes with limited battery power, one of the most fundamental applications is data aggregation which collects nearby environmental conditions and aggregates the data to a designated destination, called a sink node. Important issues concerning the data aggregation are time efficiency and energy consumption due to its limited energy, and therefore, the related problem, named Minimum Latency Aggregation Scheduling (MLAS), has been the focus of many researchers. Its objective is to compute the minimum latency schedule, that is, to compute a schedule with the minimum number of timeslots, such that the sink node can receive the aggregated data from all the other nodes without any collision or interference. For the problem, the two interference models, the graph model and the more realistic physical interference model known as Signal-to-Interference-Noise-Ratio (SINR), have been adopted with different power models, uniform-power and non-uniform power (with power control or without power control), and different antenna models, omni-directional antenna and directional antenna models. In this survey article, as the problem has proven to be NP-hard, we present and compare several state-of-the-art approximation algorithms in various models on the basis of latency as its performance measure.

Keywords: Data aggregation, convergecast, gathering, approximation, interference, omni-directional, directional.

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Authors: Won-Ho Kim, Chang-Ho Hyun, Moon-Jung Kim

Abstract:

In this paper, zigbee communication based wireless energy surveillance system is presented. The proposed system consists of multiple energy surveillance devices and an energy surveillance monitor. Each different standby power-off value of electric device is set automatically by using learning function of energy surveillance device. Thus adaptive standby power-off function provides user convenience and it maximizes the energy savings. Also, power consumption monitoring function is helpful to reduce inefficient energy consumption in home. The zigbee throughput simulator is designed to evaluate minimum transmission power and maximum allowable information quantity in the proposed system. The test result of prototype has been satisfied all the requirements. The proposed system has confirmed that can be used as an intelligent energy surveillance system for energy savings in home or office.

Keywords: Energy monitoring system, Energy surveillance system, Energy sensor network, Energy savings.

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Deogratius Musiige, François Anton, Vital Yatskevich, Laulagnet Vincent, Darka Mioc, Nguyen Pierre

Abstract:

This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.

Keywords: Radio frequency, high power amplifier, baseband, LTE, power, emulation, homotopy, interval analysis, Tx power, register-transfer level.

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Authors: Darshana Thomas, Edward Wilkie, James Irvine

Abstract:

The Internet of things (IoT) is currently a highly researched topic, especially within the context of the smart home. These are small sensors that are capable of gathering data and transmitting it to a server. The majority of smart home products use protocols such as ZigBee or Bluetooth Low Energy (BLE). As these small sensors are increasing in number, the need to implement these with much more capable and ubiquitous transmission technology is necessary. The high power consumption is the reason that holds these small sensors back from using other protocols such as the most ubiquitous form of communication, WiFi. Comparing the power consumption of existing transmission technologies to one with WiFi inbuilt, would provide a better understanding for choosing between these technologies. We have developed a small IoT device with WiFi capability and proven that it is much more efficient than the first protocol, 433 MHz. We extend our work in this paper and compare WiFi power consumption with the other most widely used protocol BLE. The experimental results in this paper would conclude whether the developed prototype is capable in terms of power consumption to replace the existing protocol BLE with WiFi.

Keywords: Bluetooth, internet of things, power consumption, WiFi.

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Authors: N. Mahendran, R. Madhuranthi

Abstract:

Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.

Keywords: Power consumption, energy efficiency, low power WSN node, recursive structure, sleep/wake scheduling.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

Abstract:

While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: Ilya Kavalchuk, Hayrettin Arisoy, Alex Stojcevski, Aman Maun Than Oo

Abstract:

Electric vehicles are one of the most complicated electric devices to simulate due to the significant number of different processes involved in electrical structure of it. There are concurrent processes of energy consumption and generation with different onboard systems, which make simulation tasks more complicated to perform. More accurate simulation on energy consumption can provide a better understanding of all energy management for electric transport. As a result of all those processes, electric transport can allow for a more sustainable future and become more convenient in relation to the distance range and recharging time. This paper discusses the problems of energy consumption simulations for electric vehicles using different software packages to provide ideas on how to make this process more precise, which can help engineers create better energy management strategies for electric vehicles.

Keywords: Electric Vehicles, EV, Power Consumption, Power Management, Simulation.

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Authors: Tatyana Aleksandrovna Barbasova, Lev Sergeevich Kazarinov, Olga Valerevna Kolesnikova, Aleksandra Aleksandrovna Filimonova

Abstract:

We regard forecasting of energy consumption by private production areas of a large industrial facility as well as by the facility itself. As for production areas, the forecast is made based on empirical dependencies of the specific energy consumption and the production output. As for the facility itself, implementation of the task to minimize the energy consumption forecasting error is based on adjustment of the facility’s actual energy consumption values evaluated with the metering device and the total design energy consumption of separate production areas of the facility. The suggested procedure of optimal energy consumption was tested based on the actual data of core product output and energy consumption by a group of workshops and power plants of the large iron and steel facility. Test results show that implementation of this procedure gives the mean accuracy of energy consumption forecasting for winter 2014 of 0.11% for the group of workshops and 0.137% for the power plants.

Keywords: Energy consumption, energy consumption forecasting error, energy efficiency, forecasting accuracy, forecasting.

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Authors: Theerawut Jinayim, Somchai Arunrungrasmi, Tanes Tanitteerapan, Narong Mungkung

Abstract:

Although White LED lighting systems powered by solar cells have presented for many years, they are not widely used in today application because of their cost and low energy conversion efficiency. The proposed system use the dc power generated by fixed solar cells module to energize White LED light sources that are operated by directly connected White LED with current limitation resistors, resulting in much more power consumption. This paper presents the use of white LED as a general lighting application powered by tracking solar cells module and using pulse to apply the electrical power to the White LED. These systems resulted in high efficiency power conversion, low power consumption, and long light of the white LED.

Keywords: Efficiency, lighting, light-emitting diode, pulse, Solar, white LED.

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Authors: Pawel P. Czapski, Andrzej Sluzek

Abstract:

This paper presents preliminary results regarding system-level power awareness for FPGA implementations in wireless sensor networks. Re-configurability of field programmable gate arrays (FPGA) allows for significant flexibility in its applications to embedded systems. However, high power consumption in FPGA becomes a significant factor in design considerations. We present several ideas and their experimental verifications on how to optimize power consumption at high level of designing process while maintaining the same energy per operation (low-level methods can be used additionally). This paper demonstrates that it is possible to estimate feasible power consumption savings even at the high level of designing process. It is envisaged that our results can be also applied to other embedded systems applications, not limited to FPGA-based.

Keywords: Power optimization, FPGA, system-level designing, wireless sensor networks.

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Authors: Ching Kin Keong, Koh Tieng Wei, Abdul Azim Abd. Ghani, Khaironi Yatim Sharif

Abstract:

Maintaining factory default battery endurance rate over time in supporting huge amount of running applications on energy-restricted mobile devices has created a new challenge for mobile applications developer. While delivering customers’ unlimited expectations, developers are barely aware of efficient use of energy from the application itself. Thus, developers need a set of valid energy consumption indicators in assisting them to develop energy saving applications. In this paper, we present a few software product metrics that can be used as an indicator to measure energy consumption of Android-based mobile applications in the early of design stage. In particular, Trepn Profiler (Power profiling tool for Qualcomm processor) has used to collect the data of mobile application power consumption, and then analyzed for the 23 software metrics in this preliminary study. The results show that McCabe cyclomatic complexity, number of parameters, nested block depth, number of methods, weighted methods per class, number of classes, total lines of code and method lines have direct relationship with power consumption of mobile application.

Keywords: Battery endurance, software metrics, mobile application, power consumption.

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Authors: M. Benbouzid, Q. Bresson, A. Duclos, K. Longo, Q. Morel

Abstract:

Currently, electricity suppliers must predict the consumption of their customers in order to deduce the power they need to produce. It is then important in a first step to optimize household consumptions to obtain more constant curves by limiting peaks in energy consumption. Here centralized real time scheduling is proposed to manage the equipments starting in parallel. The aim is not to exceed a certain limit while optimizing the power consumption across a habitat. The Raspberry Pi is used as a box; this scheduler interacts with the various sensors in 6LoWPAN. At the scale of a single dwelling, household consumption decreases, particularly at times corresponding to the peaks. However, it would be wiser to consider the use of a residential complex so that the result would be more significant. So the ceiling would no longer be fixed. The scheduling would be done on two scales, on the one hand per dwelling, and secondly, at the level of a residential complex.

Keywords: Smart grid, Energy box, Scheduling, Gang Model, Energy consumption, Energy management system, and Wireless Sensor Network.

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Authors: E. Shahhaidar

Abstract:

In this paper we present a novel design of a wearable electronic textile. After defining a special application, we used the specifications of some low power, tiny elements including sensors, microcontrollers, transceivers, and a fault tolerant special topology to have the most reliability as well as low power consumption and longer lifetime. We have considered two different conditions as normal and bodily critical conditions and set priorities for using different sensors in various conditions to have a longer effective lifetime.

Keywords: ECG, E-Textile, Fault Tolerance, Powerconsumption.

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