Search results for: Redundancy Switched Capacitor Sample and Hold Circuit
Commenced in January 2007
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Edition: International
Paper Count: 2132

Search results for: Redundancy Switched Capacitor Sample and Hold Circuit

2072 Incorporation of Long-Term Redundancy in ECG Time Domain Compression Methods through Curve Simplification and Block-Sorting

Authors: Bachir Boucheham, Youcef Ferdi, Mohamed Chaouki Batouche

Abstract:

We suggest a novel method to incorporate longterm redundancy (LTR) in signal time domain compression methods. The proposition is based on block-sorting and curve simplification. The proposition is illustrated on the ECG signal as a post-processor for the FAN method. Test applications on the new so-obtained FAN+ method using the MIT-BIH database show substantial improvement of the compression ratio-distortion behavior for a higher quality reconstructed signal.

Keywords: ECG compression, Long-term redundancy, Block-sorting, Curve Simplification.

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2071 Stability of a Special Class of Switched Positive Systems

Authors: Xiuyong Ding, Lan Shu, Xiu Liu

Abstract:

This paper is concerned with the existence of a linear copositive Lyapunov function(LCLF) for a special class of switched positive linear systems(SPLSs) composed of continuousand discrete-time subsystems. Firstly, by using system matrices, we construct a special kind of matrices in appropriate manner. Secondly, our results reveal that the Hurwitz stability of these matrices is equivalent to the existence of a common LCLF for arbitrary finite sets composed of continuous- and discrete-time positive linear timeinvariant( LTI) systems. Finally, a simple example is provided to illustrate the implication of our results.

Keywords: Linear co-positive Lyapunov functions, positive systems, switched systems.

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2070 Simulation of Surge Protection for a Direct Current Circuit

Authors: Pedro Luis Ferrer Penalver, Edmundo da Silva Braga

Abstract:

In this paper, the performance of a simple surge protection for a direct current circuit was simulated. The protection circuit was developed from modified electric macro models of a gas discharge tube and a transient voltage suppressor diode. Moreover, a combination wave generator circuit was used as source of energy surges. The simulations showed that the circuit presented ensures immunity corresponding with test level IV of the IEC 61000-4-5:2014 international standard. The developed circuit can be modified to meet the requirements of any other equipment to be protected. Similarly, the parameters of the combination wave generator can be changed to provide different surge amplitudes.

Keywords: Combination wave generator, IEC 61000-4-5, Pspice simulation, surge protection.

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2069 H-Infinity Controller Design for the Switched Reluctance Machine

Authors: Siwar Fadhel, Imen Bahri, Man Zhang

Abstract:

The switched reluctance machine (SRM) has undeniable qualities in terms of low cost and mechanical robustness. However, its highly nonlinear character and its uncertain parameters justify the development of complicated controls. In this paper, authors present the design of a robust H-infinity current controller for an 8/6 SRM with taking into account the nonlinearity of the SRM and with rejection of disturbances. The electromagnetic torque is indirectly regulated through the current controller. To show the performances of this control, a robustness analysis is performed by comparing the H-infinity and PI controller simulation results. This comparison demonstrates better performances for the presented controller. The effectiveness and robustness of the presented controller are also demonstrated by experimental tests.

Keywords: Current regulation, experimentation, robust H-infinity control, switched reluctance machine.

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2068 Realization of a Temperature Based Automatic Controlled Domestic Electric Boiling System

Authors: Shengqi Yu, Jinwei Zhao

Abstract:

This paper presents a kind of analog circuit based temperature control system, which is mainly composed by threshold control signal circuit, synchronization signal circuit and trigger pulse circuit. Firstly, the temperature feedback signal function is realized by temperature sensor TS503F3950E. Secondly, the main control circuit forms the cycle controlled pulse signal to control the thyristor switching model. Finally two reverse paralleled thyristors regulate the output power by their switching state. In the consequence, this is a modernized and energy-saving domestic electric heating system.

Keywords: Time base circuit, automatic control, zero-crossing trigger, temperature control.

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2067 A 3rd order 3bit Sigma-Delta Modulator with Reduced Delay Time of Data Weighted Averaging

Authors: Soon Jai Yi, Sun-Hong Kim, Hang-Geun Jeong, Seong-Ik Cho

Abstract:

This paper presents a method of reducing the feedback delay time of DWA(Data Weighted Averaging) used in sigma-delta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigma-delta modulator improves the timing margin about 16%. The sub-circuits of sigma-delta modulator such as SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and DWA are designed with the non-ideal characteristics taken into account. The sigma-delta modulator has a maximum SNR (Signal to Noise Ratio) of 84 dB or 13 bit resolution.

Keywords: Sigma-delta modulator, multibit, DWA

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2066 Effects of Tap Changing Transformer and Shunt Capacitor on Voltage Stability Enhancement of Transmission Networks

Authors: Pyone Lai Swe, Wanna Swe, Kyaw Myo Lin

Abstract:

Voltage stability has become an important issue to many power systems around the world due to the weak systems and long line on power system networks. In this paper, MATLAB load flow program is applied to obtain the weak points in the system combined with finding the voltage stability limit. The maximum permissible loading of a system, within the voltage stability limit, is usually determined. The methods for varying tap ratio (using tap changing transformer) and applying different values of shunt capacitor injection to improve the voltage stability within the limit are also provided.

Keywords: Load flow, Voltage stability, Tap changingtransformer, Shunt capacitor injection, Voltage stability limit

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2065 On General Stability for Switched Positive Linear Systems with Bounded Time-varying Delays

Authors: Xiu Liu, Shouming Zhong, Xiuyong Ding

Abstract:

This paper focuses on the problem of a common linear copositive Lyapunov function(CLCLF) existence for discrete-time switched positive linear systems(SPLSs) with bounded time-varying delays. In particular, applying system matrices, a special class of matrices are constructed in an appropriate manner. Our results reveal that the existence of a common copositive Lyapunov function can be related to the Schur stability of such matrices. A simple example is provided to illustrate the implication of our results.

Keywords: Common linear co-positive Lyapunov functions, positive systems, switched systems, delays.

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2064 A Comparative Analysis of Multicarrier SPWM Strategies for Five-Level Flying Capacitor Inverter

Authors: Bachir Belmadani, Rachid Taleb, Zinelaabidine Boudjema, Adil Yahdou

Abstract:

Carrier-based methods have been used widely for switching of multilevel inverters due to their simplicity, flexibility and reduced computational requirements compared to space vector modulation (SVM). This paper focuses on Multicarrier Sinusoidal Pulse Width Modulation (MCSPWM) strategy for the three phase Five-Level Flying Capacitor Inverter (5LFCI). The inverter is simulated for Induction Motor (IM) load and Total Harmonic Distortion (THD) for output waveforms is observed for different controlling schemes.

Keywords: Flying capacitor inverter, multicarrier sinusoidal pulse width modulation, space vector modulation, total harmonic distortion, induction motor.

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2063 Clinical Factors of Quality Switched Ruby Laser Therapy for Lentigo Depigmentation

Authors: SunWoo Lee, TaeBum Lee, YoonHwa Park, YooJeong Kim

Abstract:

Solar lentigines appear predominantly on chronically sun-exposed areas of skin, such as the face and the back of the hands. Among the several ways to lentigines treatment, quality-switched lasers are well-known effective treatment for removing solar lentigines. The present pilot study was therefore designed to assess the efficacy of quality-switched ruby laser treatment of such lentigines compare between pretreatment and posttreatment of skin brightness. Twenty-two adults with chronic sun-damaged skin (mean age 52.8 years, range 37–74 years) were treated at the Korean site. A 694 nm Q-switched ruby laser was used, with the energy density set from 1.4 to 12.5 J/cm2, to treat solar lentigines. Average brightness of skin color before ruby laser treatment was 137.3 and its skin color was brightened after ruby laser treatment by 150.5. Also, standard deviation of skin color was decreased from 17.8 to 16.4. Regarding the multivariate model, age and energy were identified as significant factors for skin color brightness change in lentigo depigmentation by ruby laser treatment. Their respective odds ratios were 1.082 (95% CI, 1.007–1.163), and 1.431 (95% CI, 1.051–1.946). Lentigo depigmentation treatment using ruby lasers resulted in a high performance in skin color brightness. Among the relative factors involve with ruby laser treatment, age and energy were the most effective factors which skin color change to brighter than pretreatment.

Keywords: Depigmentation, lentigo, quality switched ruby laser, skin color.

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2062 Delay Specific Investigations on QoS Scheduling Schemes for Real-Time Traffic in Packet Switched Networks

Authors: P.S.Prakash, S.Selvan

Abstract:

Packet switched data network like Internet, which has traditionally supported throughput sensitive applications such as email and file transfer, is increasingly supporting delay-sensitive multimedia applications such as interactive video. These delaysensitive applications would often rather sacrifice some throughput for better delay. Unfortunately, the current packet switched network does not offer choices, but instead provides monolithic best-effort service to all applications. This paper evaluates Class Based Queuing (CBQ), Coordinated Earliest Deadline First (CEDF), Weighted Switch Deficit Round Robin (WSDRR) and RED-Boston scheduling schemes that is sensitive to delay bound expectations for variety of real time applications and an enhancement of WSDRR is proposed.

Keywords: QoS, Delay-sensitive, Queuing delay, Scheduling

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2061 Sensorless Commutation Control of Switched Reluctance Motor

Authors: N.H. Mvungi

Abstract:

This paper addresses control of commutation of switched reluctance (SR) motor without the use of a physical position detector. Rotor position detection schemes for SR motor based on magnetisation characteristics of the motor use normal excitation or applied current /voltage pulses. The resulting schemes are referred to as passive or active methods respectively. The research effort is in realizing an economical sensorless SR rotor position detector that is accurate, reliable and robust to suit a particular application. An effective and reliable means of generating commutation signals of an SR motor based on inductance profile of its stator windings determined using active probing technique is presented. The scheme has been validated online using a 4-phase 8/6 SR motor and an 8-bit processor.

Keywords: Position detection, rotor position, sensorless, switched reluctance, SR.

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2060 High Level Characterization and Optimization of Switched-Current Sigma-Delta Modulators with VHDL-AMS

Authors: A. Fakhfakh, N. Ksentini, M. Loulou, N. Masmoudi, J. J. Charlot

Abstract:

Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline design. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of Switched-Current Sigma- Delta Modulators. It uses the new hardware description language VHDL-AMS to help the designers to optimize the characteristics of the modulator at a high level with a considerably reduced CPU time before passing to a transistor level characterization.

Keywords: high level design, optimization, switched-Current Sigma-Delta Modulators, VHDL-AMS.

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2059 Metal-Oxide-Semiconductor-Only Process Corner Monitoring Circuit

Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: Detection, monitoring, process corner, process variation.

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2058 A New Hybrid Optimization Method for Optimum Distribution Capacitor Planning

Authors: A. R. Seifi

Abstract:

This work presents a new algorithm based on a combination of fuzzy (FUZ), Dynamic Programming (DP), and Genetic Algorithm (GA) approach for capacitor allocation in distribution feeders. The problem formulation considers two distinct objectives related to total cost of power loss and total cost of capacitors including the purchase and installation costs. The novel formulation is a multi-objective and non-differentiable optimization problem. The proposed method of this article uses fuzzy reasoning for sitting of capacitors in radial distribution feeders, DP for sizing and finally GA for finding the optimum shape of membership functions which are used in fuzzy reasoning stage. The proposed method has been implemented in a software package and its effectiveness has been verified through a 9-bus radial distribution feeder for the sake of conclusions supports. A comparison has been done among the proposed method of this paper and similar methods in other research works that shows the effectiveness of the proposed method of this paper for solving optimum capacitor planning problem.

Keywords: Capacitor planning, Fuzzy logic method, Genetic Algorithm, Dynamic programming, Radial Distribution feeder

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2057 Realization of Electronically Controllable Current-mode Square-rooting Circuit Based on MO-CFTA

Authors: P. Silapan, C. Chanapromma, T. Worachak

Abstract:

This article proposes a current-mode square-rooting circuit using current follower transconductance amplifier (CTFA). The amplitude of the output current can be electronically controlled via input bias current with wide input dynamic range. The proposed circuit consists of only single CFTA. Without any matching conditions and external passive elements, the circuit is then appropriate for an IC architecture. The magnitude of the output signal is temperature-insensitive. The PSpice simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.96mW at ±1.5V supply voltages.

Keywords: CFTA, Current-mode, Square-rooting Circuit

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2056 A Low-Voltage Current-Mode Wheatstone Bridge using CMOS Transistors

Authors: Ebrahim Farshidi

Abstract:

This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with multiple sensors and works by single supply voltage. The circuit employs MOSFET transistors, so it can be used for standard CMOS fabrication. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Keywords: Wheatstone bridge, current-mode, low-voltage, MOS.

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2055 Reductive Control in the Management of Redundant Actuation

Authors: Mkhinini Maher, Knani Jilani

Abstract:

We present in this work the performances of a mobile omnidirectional robot through evaluating its management of the redundancy of actuation. Thus we come to the predictive control implemented.

The distribution of the wringer on the robot actions, through the inverse pseudo of Moore-Penrose, corresponds to a « geometric ›› distribution of efforts. We will show that the load on vehicle wheels would not be equi-distributed in terms of wheels configuration and of robot movement.

Thus, the threshold of sliding is not the same for the three wheels of the vehicle. We suggest exploiting the redundancy of actuation to reduce the risk of wheels sliding and to ameliorate, thereby, its accuracy of displacement. This kind of approach was the subject of study for the legged robots.

Keywords: Mobile robot, actuation, redundancy, omnidirectional, inverse pseudo Moore-Penrose, reductive control.

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2054 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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2053 Reliability Modeling and Data Analysis of Vacuum Circuit Breaker Subject to Random Shocks

Authors: Rafik Medjoudj, Rabah Medjoudj, D. Aissani

Abstract:

The electrical substation components are often subject to degradation due to over-voltage or over-current, caused by a short circuit or a lightning. A particular interest is given to the circuit breaker, regarding the importance of its function and its dangerous failure. This component degrades gradually due to the use, and it is also subject to the shock process resulted from the stress of isolating the fault when a short circuit occurs in the system. In this paper, based on failure mechanisms developments, the wear out of the circuit breaker contacts is modeled. The aim of this work is to evaluate its reliability and consequently its residual lifetime. The shock process is based on two random variables such as: the arrival of shocks and their magnitudes. The arrival of shocks was modeled using homogeneous Poisson process (HPP). By simulation, the dates of short-circuit arrivals were generated accompanied with their magnitudes. The same principle of simulation is applied to the amount of cumulative wear out contacts. The objective reached is to find the formulation of the wear function depending on the number of solicitations of the circuit breaker.

Keywords: reliability, short-circuit, models of shocks.

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2052 Sensitivity of Input Blocking Capacitor on Output Voltage and Current of a PV Inverter Employing IGBTs

Authors: Z.A. Jaffery, Vinay Kumar Chandna, Sunil Kumar Chaudhary

Abstract:

This paper present a MATLAB-SIMULINK model of a single phase 2.5 KVA, 240V RMS controlled PV VSI (Photovoltaic Voltage Source Inverter) inverter using IGBTs (Insulated Gate Bipolar Transistor). The behavior of output voltage, output current, and the total harmonic distortion (THD), with the variation in input dc blocking capacitor (Cdc), for linear and non-linear load has been analyzed. The values of Cdc as suggested by the other authors in their papers are not clearly defined and it poses difficulty in selecting the proper value. As the dc power stored in Cdc, (generally placed parallel with battery) is used as input to the VSI inverter. The simulation results shows the variation in the output voltage and current with different values of Cdc for linear and non-linear load connected at the output side of PV VSI inverter and suggest the selection of suitable value of Cdc.

Keywords: DC Blocking capacitor, IGBTs, PV VSI, THD.

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2051 Determination of Geometric Dimensions of a Double Sided Linear Switched Reluctance Motor

Authors: Dursun M., Koc F., Ozbay H.

Abstract:

In this study, a double-sided linear switched reluctance motor (LSRM) drive was investigated as an alternative actuator for vertical linear transportation applications such as a linear elevator door, hospital and subway doors which move linearly and where accurate position control and rapid response is requested. A prototype sliding elevator door that is focused on a home elevator with LSRMs is designed. The motor has 6/4 poles, 3 phases, 8A, 24V, 250 W and 250 N pull forces. Air gap between rotor and translator poles of the designed motor and phase coil-s ideal inductance profile are obtained in compliance with the geometric dimensions. Operation and switching sections as motor and generator has been determined from the inductance profile.

Keywords: Linear switched reluctance motor, sliding door, elevator door, linear motor design.

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2050 Transient Enhanced LDO Voltage Regulator with Improved Feed Forward Path Compensation

Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

Abstract:

Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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2049 A Capacitive Sensor Interface Circuit Based on Phase Differential Method

Authors: H. A. Majid, N. Razali, M. S. Sulaiman, A. K. A'ain

Abstract:

A new interface circuit for capacitive sensor is presented. This paper presents the design and simulation of soil moisture capacitive sensor interface circuit based on phase differential technique. The circuit has been designed and fabricated using MIMOS- 0.35"m CMOS technology. Simulation and test results show linear characteristic from 36 – 52 degree phase difference, representing 0 – 100% in soil moisture level. Test result shows the circuit has sensitivity of 0.79mV/0.10 phase difference, translating into resolution of 10% soil moisture level.

Keywords: Capacitive sensor, interface, phase differential.

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2048 Modeling and Simulation of Position Estimation of Switched Reluctance Motor with Artificial Neural Networks

Authors: Oguz Ustun, Erdal Bekiroglu

Abstract:

In the present study, position estimation of switched reluctance motor (SRM) has been achieved on the basis of the artificial neural networks (ANNs). The ANNs can estimate the rotor position without using an extra rotor position sensor by measuring the phase flux linkages and phase currents. Flux linkage-phase current-rotor position data set and supervised backpropagation learning algorithm are used in training of the ANN based position estimator. A 4-phase SRM have been used to verify the accuracy and feasibility of the proposed position estimator. Simulation results show that the proposed position estimator gives precise and accurate position estimations for both under the low and high level reference speeds of the SRM

Keywords: Artificial neural networks, modeling andsimulation, position observer, switched reluctance motor.

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2047 A Genetic Algorithm Approach Considering Zero Injection Bus Constraint Modeling for Optimal Phasor Measurement Unit Placement

Authors: G. Chandana Sushma, T. R. Jyothsna

Abstract:

This paper presents optimal Phasor Measurement Unit (PMU) Placement in network using a genetic algorithm approach as it is infeasible and require high installation cost to place PMUs at every bus in network. This paper proposes optimal PMU allocation considering observability and redundancy utilizing Genetic Algorithm (GA) approach. The nonlinear constraints of buses are modeled to give accurate results. Constraints associated with Zero Injection (ZI) buses and radial buses are modeled to optimize number of locations for PMU placement. GA is modeled with ZI bus constraints to minimize number of locations without losing complete observability. Redundancy of every bus in network is computed to show optimum redundancy of complete system network. The performance of method is measured by Bus Observability Index (BOI) and Complete System Observability Performance Index (CSOPI). MATLAB simulations are carried out on IEEE -14, -30 and -57 bus-systems and compared with other methods in literature survey to show the effectiveness of the proposed approach.

Keywords: Constraints, genetic algorithm, observability, phasor measurement units, redundancy, synchrophasors, zero injection bus.

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2046 Analog Circuit Design using Genetic Algorithm: Modified

Authors: Amod P. Vaze

Abstract:

Genetic Algorithm has been used to solve wide range of optimization problems. Some researches conduct on applying Genetic Algorithm to analog circuit design automation. These researches show a better performance due to the nature of Genetic Algorithm. In this paper a modified Genetic Algorithm is applied for analog circuit design automation. The modifications are made to the topology of the circuit. These modifications will lead to a more computationally efficient algorithm.

Keywords: Genetic algorithm, analog circuits, design.

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2045 A Methodology for Reducing the BGP Convergence Time

Authors: Eatedal A. Alabdulkreem, Hamed S. Al-Raweshidy, Maysam F. Abbod

Abstract:

Border Gateway Protocol (BGP) is the standard routing protocol between various autonomous systems (AS) in the internet. In the event of failure, a considerable delay in the BGP convergence has been shown by empirical measurements. During the convergence time the BGP will repeatedly advertise new routes to some destination and withdraw old ones until it reach a stable state. It has been found that the KEEPALIVE message timer and the HOLD time are tow parameters affecting the convergence speed. This paper aims to find the optimum value for the KEEPALIVE timer and the HOLD time that maximally reduces the convergence time without increasing the traffic. The KEEPALIVE message timer optimal value founded by this paper is 30 second instead of 60 seconds, and the optimal value for the HOLD time is 90 seconds instead of 180 seconds.

Keywords: BGP, Convergence Time, HOLD time, Keep alive.

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2044 The Invariant Properties of Two-Port Circuits

Authors: Alexandr A. Penin

Abstract:

Application of projective geometry to the theory of two-ports and cascade circuits with a load change is considered. The equations linking the input and output of a two-port are interpreted as projective transformations which have the invariant as a cross-ratio of four points. This invariant has place for all regime parameters in all parts of a cascade circuit. This approach allows justifying the definition of a regime and its change, to calculate a circuit without explicitly finding the aparameters, to transmit accurately an analogue signal through the unstable two-port.

Keywords: Circuit regime, geometric circuit theory, projective geometry, two-port.

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2043 Equivalent Circuit Modelling of Active Reflectarray Antenna

Authors: M. Y. Ismail, M. Inam

Abstract:

This paper presents equivalent circuit modeling of active planar reflectors which can be used for the detailed analysis and characterization of reflector performance in terms of lumped components. Equivalent circuit representation has been proposed for PIN diodes and liquid crystal based active planar reflectors designed within X-band frequency range. A very close agreement has been demonstrated between equivalent circuit results, 3D EM simulated results as well as measured scattering parameter results. In the case of measured results, a maximum discrepancy of 1.05dB was observed in the reflection loss performance, which can be attributed to the losses occurred during measurement process.

Keywords: Equivalent circuit modelling, planar reflectors, reflectarray antenna, PIN diode, liquid crystal.

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