@article{(Open Science Index):https://publications.waset.org/pdf/10802,
	  title     = {A 3rd order 3bit Sigma-Delta Modulator with Reduced Delay Time of Data Weighted Averaging},
	  author    = {Soon Jai Yi and  Sun-Hong Kim and  Hang-Geun Jeong and  Seong-Ik Cho},
	  country	= {},
	  institution	= {},
	  abstract     = {This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigma-delta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigma-delta modulator improves the timing
margin about 16%. The sub-circuits of sigma-delta modulator such as
SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and
DWA are designed with the non-ideal characteristics taken into
account. The sigma-delta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {4},
	  number    = {11},
	  year      = {2010},
	  pages     = {1688 - 1691},
	  ee        = {https://publications.waset.org/pdf/10802},
	  url   	= {https://publications.waset.org/vol/47},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 47, 2010},