%0 Journal Article
	%A Soon Jai Yi and  Sun-Hong Kim and  Hang-Geun Jeong and  Seong-Ik Cho
	%D 2010
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 47, 2010
	%T A 3rd order 3bit Sigma-Delta Modulator with Reduced Delay Time of Data Weighted Averaging
	%U https://publications.waset.org/pdf/10802
	%V 47
	%X This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigma-delta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigma-delta modulator improves the timing
margin about 16%. The sub-circuits of sigma-delta modulator such as
SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and
DWA are designed with the non-ideal characteristics taken into
account. The sigma-delta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.
	%P 1688 - 1691