Soon Jai Yi and Sun-Hong Kim and Hang-Geun Jeong and Seong-Ik Cho
A 3rd order 3bit SigmaDelta Modulator with Reduced Delay Time of Data Weighted Averaging
1688 - 1691
2010
4
11
International Journal of Electrical and Computer Engineering
https://publications.waset.org/pdf/10802
https://publications.waset.org/vol/47
World Academy of Science, Engineering and Technology
This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigmadelta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigmadelta modulator improves the timing
margin about 16. The subcircuits of sigmadelta modulator such as
SC(Switched Capacitor) integrator, 9level quantizer, comparator, and
DWA are designed with the nonideal characteristics taken into
account. The sigmadelta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.
Open Science Index 47, 2010