Search results for: Integrator circuits
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 260

Search results for: Integrator circuits

170 Comparative Study of Evolutionary Model and Clustering Methods in Circuit Partitioning Pertaining to VLSI Design

Authors: K. A. Sumitra Devi, N. P. Banashree, Annamma Abraham

Abstract:

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.

Keywords: VLSI, circuit partitioning, memetic algorithm, genetic algorithm.

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169 Library Aware Power Conscious Realization of Complementary Boolean Functions

Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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168 Location Detection of Vehicular Accident Using Global Navigation Satellite Systems/Inertial Measurement Units Navigator

Authors: Neda Navidi, Rene Jr. Landry

Abstract:

Vehicle tracking and accident recognizing are considered by many industries like insurance and vehicle rental companies. The main goal of this paper is to detect the location of a car accident by combining different methods. The methods, which are considered in this paper, are Global Navigation Satellite Systems/Inertial Measurement Units (GNSS/IMU)-based navigation and vehicle accident detection algorithms. They are expressed by a set of raw measurements, which are obtained from a designed integrator black box using GNSS and inertial sensors. Another concern of this paper is the definition of accident detection algorithm based on its jerk to identify the position of that accident. In fact, the results convinced us that, even in GNSS blockage areas, the position of the accident could be detected by GNSS/INS integration with 50% improvement compared to GNSS stand alone.

Keywords: Driving behavior, integration, IMU, GNSS, monitoring, tracking.

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167 Modular Harmonic Cancellation in a Multiplier High Voltage Direct Current Generator

Authors: Ahmad Zahran, Ahmed Herzallah, Ahmad Ahmad, Mahran Quraan

Abstract:

Generation of high DC voltages is necessary for testing the insulation material of high voltage AC transmission lines with long lengths. The harmonic and ripple contents of the output DC voltage supplied by high voltage DC circuits require the use of costly capacitors to smooth the output voltage after rectification. This paper proposes a new modular multiplier high voltage DC generator with embedded Cockcroft-Walton circuits that achieve a negligible harmonic and ripple contents of the output DC voltage without the need for costly filters to produce a nearly constant output voltage. In this new topology, Cockcroft-Walton modules are connected in series to produce a high DC output voltage. The modules are supplied by low input AC voltage sources that have the same magnitude and frequency and shifted from each other by a certain angle to eliminate the harmonics from the output voltage. The small ripple factor is provided by the smoothing column capacitors and the phase shifted input voltages of the cascaded modules. The constituent harmonics within each module are determined using Fourier analysis. The viability of the proposed DC generator for testing purposes and the effectiveness of the cascaded connection are confirmed by numerical simulations using MATLAB/Simulink.

Keywords: Cockcroft-Walton circuit, Harmonics, Ripple factor, HVDC generator.

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166 Higher Frequency Modeling of Synchronous Exciter Machines by Equivalent Circuits and Transfer Functions

Authors: Marcus Banda

Abstract:

In this article the influence of higher frequency effects in addition to a special damper design on the electrical behavior of a synchronous generator main exciter machine is investigated. On the one hand these machines are often highly stressed by harmonics from the bridge rectifier thus facing additional eddy current losses. On the other hand the switching may cause the excitation of dangerous voltage peaks in resonant circuits formed by the diodes of the rectifier and the commutation reactance of the machine. Therefore modern rotating exciters are treated like synchronous generators usually modeled with a second order equivalent circuit. Hence the well known Standstill Frequency Response Test (SSFR) method is applied to a test machine in order to determine parameters for the simulation. With these results it is clearly shown that higher frequencies have a strong impact on the conventional equivalent circuit model. Because of increasing field displacement effects in the stranded armature winding the sub-transient reactance is even smaller than the armature leakage at high frequencies. As a matter of fact this prevents the algorithm to find an equivalent scheme. This issue is finally solved using Laplace transfer functions fully describing the transient behavior at the model ports.

Keywords: Synchronous exciter machine, Linear transfer function, SSFR, Equivalent Circuit

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165 Evaluation Performance of PID, LQR, Pole Placement Controllers for Heat Exchanger

Authors: Mohamed Essahafi, Mustapha Ait Lafkih

Abstract:

In industrial environments, the heat exchanger is a necessary component to any strategy of energy conversion. Much of thermal energy used in industrial processes passes at least one times by a heat exchanger, and methods systems recovering thermal energy. This survey paper tries to presents in a systemic way an sample control of a heat exchanger by comparison between three controllers LQR (linear quadratic regulator), PID (proportional, integrator and derivate) and Pole Placement. All of these controllers are used mainly in industrial sectors (chemicals, petrochemicals, steel, food processing, energy production, etc…) of transportation (automotive, aeronautics), but also in the residential sector and tertiary (heating, air conditioning, etc...) The choice of a heat exchanger, for a given application depends on many parameters: field temperature and pressure of fluids, and physical properties of aggressive fluids, maintenance and space. It is clear that the fact of having an exchanger appropriate, well-sized, well made and well used allows gain efficiency and energy processes.

Keywords: LQR linear-quadratic regulator, PID control, Pole Placement, Heat exchanger.

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164 Third Order Current-mode Quadrature Sinusoidal Oscillator with High Output Impedances

Authors: Kritphon Phanruttanachai, Winai Jaikla

Abstract:

This article presents a current-mode quadrature oscillator using differential different current conveyor (DDCC) and voltage differencing transconductance amplifier (VDTA) as active elements. The proposed circuit is realized fro m a non-inverting lossless integrator and an inverting second order low-pass filter. The oscillation condition and oscillation frequency can be electronically/orthogonally controlled via input bias currents. The circuit description is very simple, consisting of merely 1 DDCC, 1 VDTA, 1 grounded resistor and 3 grounded capacitors. Using only grounded elements, the proposed circuit is then suitable for IC architecture. The proposed oscillator has high output impedance which is easy to cascade or dive the external load without the buffer devices. The PSPICE simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.76mW at ±1.25V supply voltages.

Keywords: Current-mode, oscillator, integrated circuit, DDCC, VDTA

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163 Stable Delta-Sigma Modulator with Signal Dependent Forward Path Gain for Industrial Applications

Authors: K. Diwakar, K. Aanandha Saravanan, C. Senthilpari

Abstract:

Higher order ΔΣ Modulator (DSM) is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The existing second order, single stage, single bit, unity feedback gain , discrete DSM cannot be used for the normalized full range (-1 to +1) of an input signal since the DSM becomes unstable when the input signal is above ±0.55. The stability is also not guaranteed for input signals of amplitude less than ±0.55. In the present paper, the above mentioned second order DSM is modified with input signal dependent forward path gain. The proposed DSM is suitable for industrial applications where one needs the digital representation of the analog input signal, during each sampling period. The proposed DSM can operate almost for the full range of input signals (-0.95 to +0.95) without causing instability, assuming that the second integrator output should not exceed the circuit supply voltage, ±15 Volts.

Keywords: DSM, stability, SNR, state variables.

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162 Research on Load Balancing Technology for Web Service Mobile Host

Authors: Yao Lu, Xiuguo Zhang, Zhiying Cao

Abstract:

In this paper, Load Balancing idea is used in the Web service mobile host. The main idea of Load Balancing is to establish a one-to-many mapping mechanism: An entrance-mapping request to plurality of processing node in order to realize the dividing and assignment processing. Because the mobile host is a resource constrained environment, there are some Web services which cannot be completed on the mobile host. When the mobile host resource is not enough to complete the request, Load Balancing scheduler will divide the request into a plurality of sub-requests and transfer them to different auxiliary mobile hosts. Auxiliary mobile host executes sub-requests, and then, the results will be returned to the mobile host. Service request integrator receives results of sub-requests from the auxiliary mobile host, and integrates the sub-requests. In the end, the complete request is returned to the client. Experimental results show that this technology adopted in this paper can complete requests and have a higher efficiency.

Keywords: Dinic, load balancing, mobile host, web service.

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161 PID Control Design Based on Genetic Algorithm with Integrator Anti-Windup for Automatic Voltage Regulator and Speed Governor of Brushless Synchronous Generator

Authors: O. S. Ebrahim, M. A. Badr, Kh. H. Gharib, H. K. Temraz

Abstract:

This paper presents a methodology based on genetic algorithm (GA) to tune the parameters of proportional-integral-differential (PID) controllers utilized in the automatic voltage regulator (AVR) and speed governor of a brushless synchronous generator driven by three-stage steam turbine. The parameter tuning is represented as a nonlinear optimization problem solved by GA to minimize the integral of absolute error (IAE). The problem of integral windup due to physical system limitations is solved using simple anti-windup scheme. The obtained controllers are compared to those designed using classical Ziegler-Nichols technique and constrained optimization. Results show distinct superiority of the proposed method.

Keywords: Brushless synchronous generator, Genetic Algorithm, GA, Proportional-Integral-Differential control, PID control, automatic voltage regulator, AVR.

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160 A Comprehensive Evaluation of Supervised Machine Learning for the Phase Identification Problem

Authors: Brandon Foggo, Nanpeng Yu

Abstract:

Power distribution circuits undergo frequent network topology changes that are often left undocumented. As a result, the documentation of a circuit’s connectivity becomes inaccurate with time. The lack of reliable circuit connectivity information is one of the biggest obstacles to model, monitor, and control modern distribution systems. To enhance the reliability and efficiency of electric power distribution systems, the circuit’s connectivity information must be updated periodically. This paper focuses on one critical component of a distribution circuit’s topology - the secondary transformer to phase association. This topology component describes the set of phase lines that feed power to a given secondary transformer (and therefore a given group of power consumers). Finding the documentation of this component is call Phase Identification, and is typically performed with physical measurements. These measurements can take time lengths on the order of several months, but with supervised learning, the time length can be reduced significantly. This paper compares several such methods applied to Phase Identification for a large range of real distribution circuits, describes a method of training data selection, describes preprocessing steps unique to the Phase Identification problem, and ultimately describes a method which obtains high accuracy (> 96% in most cases, > 92% in the worst case) using only 5% of the measurements typically used for Phase Identification.

Keywords: Distribution network, machine learning, network topology, phase identification, smart grid.

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159 Design of Extremum Seeking Control with PD Accelerator and its Application to Monod and Williams-Otto Models

Authors: Hitoshi Takata, Tomohiro Hachino, Masaki Horai, Kazuo Komatsu

Abstract:

In this paper, we are concerned with the design and its simulation studies of a modified extremum seeking control for nonlinear systems. A standard extremum seeking control has a simple structure, but it takes a long time to reach an optimal operating point. We consider a modification of the standard extremum seeking control which is aimed to reach the optimal operating point more speedily than the standard one. In the modification, PD acceleration term is added before an integrator making a principal control, so that it enables the objects to be regulated to the optimal point smoothly. This proposed method is applied to Monod and Williams-Otto models to investigate its effectiveness. Numerical simulation results show that this modified method can improve the time response to the optimal operating point more speedily than the standard one.

Keywords: Extremum seeking control, Monod model, Williams- Otto model, PD acceleration term, Optimal operating point.

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158 A 24-Bit, 8.1-MS/s D/A Converter for Audio Baseband Channel Applications

Authors: N. Ben Ameur, M. Loulou

Abstract:

This paper study the high-level modelling and design of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-Noise- Ratio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolution in the final stage. To reduce sensitivity of Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a high pass second order Data Weighted Averaging (R2DWA) is introduced. This paper presents a MATLAB description modelling approach of the proposed DAC architecture with low distortion and swing suppression integrator designs. The ΔΣ Modulator design can be configured as a 3rd-order and allows 24-bit PCM at sampling rate of 64 kHz for Digital Video Disc (DVD) audio application. The modeling approach provides 139.38 dB of dynamic range for a 32 kHz signal band at -1.6 dBFS input signal level.

Keywords: DVD-audio, DAC, Interpolator and Interpolation Filter, Single-Loop ΔΣ Modulation, R2DWA, Clock Jitter

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157 Online Robust Model Predictive Control for Linear Fractional Transformation Systems Using Linear Matrix Inequalities

Authors: Peyman Sindareh Esfahani, Jeffery Kurt Pieper

Abstract:

In this paper, the problem of robust model predictive control (MPC) for discrete-time linear systems in linear fractional transformation form with structured uncertainty and norm-bounded disturbance is investigated. The problem of minimization of the cost function for MPC design is converted to minimization of the worst case of the cost function. Then, this problem is reduced to minimization of an upper bound of the cost function subject to a terminal inequality satisfying the l2-norm of the closed loop system. The characteristic of the linear fractional transformation system is taken into account, and by using some mathematical tools, the robust predictive controller design problem is turned into a linear matrix inequality minimization problem. Afterwards, a formulation which includes an integrator to improve the performance of the proposed robust model predictive controller in steady state condition is studied. The validity of the approaches is illustrated through a robust control benchmark problem.

Keywords: Linear fractional transformation, linear matrix inequality, robust model predictive control, state feedback control.

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156 A New Intelligent Strategy to Integrated Control of AFS/DYC Based on Fuzzy Logic

Authors: R. Karbalaei, A. Ghaffari, R. Kazemi, S. H. Tabatabaei

Abstract:

An integrated vehicle dynamics control system is developed in this paper by a combination of active front steering (AFS) and direct yaw-moment control (DYC) based on fuzzy logic control. The control system has a hierarchical structure consisting of two layers. A fuzzy logic controller is used in the upper layer (yaw rate controller) to keep the yaw rate in its desired value. The yaw rate error and its rate of change are applied to the upper controlling layer as inputs, where the direct yaw moment control signal and the steering angle correction of the front wheels are the outputs. In the lower layer (fuzzy integrator), a fuzzy logic controller is designed based on the working region of the lateral tire forces. Depending on the directions of the lateral forces at the front wheels, a switching function is activated to adjust the scaling factor of the fuzzy logic controller. Using a nonlinear seven degrees of freedom vehicle model, the simulation results illustrate considerable improvements which are achieved in vehicle handling through the integrated AFS/DYC control system in comparison with the individual AFS or DYC controllers.

Keywords: Intelligent strategy, integrated control, fuzzy logic, AFS/DYC.

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155 Chaos Synchronization Using Sliding Mode Technique

Authors: Behzad Khademian, Mohammad Haeri

Abstract:

In this paper, an effective sliding mode design is applied to chaos synchronization. The proposed controller can make the states of two identical modified Chua-s circuits globally asymptotically synchronized. Numerical results are provided to show the effectiveness and robustness of the proposed method.

Keywords: Sliding mode, Chaos synchronization, Modified Chua's circuit.

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154 A New Approach to Design an Efficient CIC Decimator Using Signed Digit Arithmetic

Authors: Vishal Awasthi, Krishna Raj

Abstract:

Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.

Keywords: Sampling rate conversion, Multirate Filtering, Compensation Theory, Decimation filter, CIC filter, Redundant signed digit arithmetic, Fast adders.

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153 Control Algorithm for Shunt Active Power Filter using Synchronous Reference Frame Theory

Authors: Consalva J. Msigwa, Beda J. Kundy, Bakari M. M. Mwinyiwiwa,

Abstract:

This paper presents a method for obtaining the desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for obtaining the best control performance of the SAPF. To improve the performance of the PI controller, the feedback path to the integral term is introduced to compensate the winding up phenomenon due to integrator. Using Reference Frame Transformation, reference signals are transformed from a - b - c stationery frame to 0 - d - q rotating frame. Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.

Keywords: Phase Locked Loop (PLL), Voltage Source Converter (VSC), Shunt Active Power Filter (SAPF), PI, Pulse Width Modulation (PWM)

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152 Fuzzy Logic Speed Controller with Reduced Rule Base for Dual PMSM Drives

Authors: Jurifa Mat Lazi, Zulkifilie Ibrahim, Marizan Sulaiman, Fizatul Aini Patakor, Siti Noormiza Mat Isa

Abstract:

Dual motor drives fed by single inverter is purposely designed to reduced size and cost with respect to single motor drives fed by single inverter. Previous researches on dual motor drives only focus on the modulation and the averaging techniques. Only a few of them, study the performance of the drives based on different speed controller other than Proportional and Integrator (PI) controller. This paper presents a detailed comparative study on fuzzy rule-base in Fuzzy Logic speed Controller (FLC) for Dual Permanent Magnet Synchronous Motor (PMSM) drives. Two fuzzy speed controllers which are standard and simplified fuzzy speed controllers are designed and the results are compared and evaluated. The standard fuzzy controller consists of 49 rules while the proposed controller consists of 9 rules determined by selecting the most dominant rules only. Both designs are compared for wide range of speed and the robustness of both controllers over load disturbance changes is tested to demonstrate the effectiveness of the simplified/reduced rulebase.

Keywords: Dual Motor Drives, Fuzzy Logic Speed Controller, Reduced Rule-Base, PMSM

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151 Applying Wavelet Transform to Ferroresonance Detection and Protection

Authors: Chun-Wei Huang, Jyh-Cherng Gu, Ming-Ta Yang

Abstract:

Non-synchronous breakage or line failure in power systems with light or no loads can lead to core saturation in transformers or potential transformers. This can cause component and capacitance matching resulting in the formation of resonant circuits, which trigger ferroresonance. This study employed a wavelet transform for the detection of ferroresonance. Simulation results demonstrate the efficacy of the proposed method.

Keywords: Ferroresonance, Wavelet Transform, Intelligent Electronic Device, Transformer.

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150 Evaluation of Coupling Factor in RF Inductively Coupled Systems

Authors: Rômulo Volpato, Filipe Ramos, Paulo Crepaldi, Michel Santana, Tales C Pimenta

Abstract:

This work presents an approach for the measurement of mutual inductance on near field inductive coupling. The mutual inductance between inductive circuits allows the simulation of energy transfer from reader to tag, that can be used in RFID and powerless implantable devices. It also allows one to predict the maximum voltage in the tag of the radio-frequency system.

Keywords: RFID, Inductive Coupling, Energy Transfer, Implantable Device

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149 A ±0.5V BiCMOS Class-A Current Conveyor

Authors: Subodh Thankachan, Manisha Pattanaik, S. S. Rajput

Abstract:

In this paper, a new BiCMOS CCII and CCCII, capable of operate at ±0.5V and having wide dynamic range with achieved bandwidth of 480MHz and 430MHz respectively have been proposed. The structures have been found to be insensitive to the threshold voltage variations. The proposed circuits are suitable for implementation using 0.25μm BiCMOS technology. Pspice simulations confirm the performance of the proposed structures.

Keywords: BiCMOS, Current conveyor, Compound current conveyor, Low supply voltage, Threshold voltage variation.

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148 Siding Mode Control of Pitch-Rate of an F-16 Aircraft

Authors: Ekprasit Promtun, Sridhar Seshagiri

Abstract:

This paper considers the control of the longitudinal flight dynamics of an F-16 aircraft. The primary design objective is model-following of the pitch rate q, which is the preferred system for aircraft approach and landing. Regulation of the aircraft velocity V (or the Mach-hold autopilot) is also considered, but as a secondary objective. The problem is challenging because the system is nonlinear, and also non-affine in the input. A sliding mode controller is designed for the pitch rate, that exploits the modal decomposition of the linearized dynamics into its short-period and phugoid approximations. The inherent robustness of the SMC design provides a convenient way to design controllers without gain scheduling, with a steady-state response that is comparable to that of a conventional polynomial based gain-scheduled approach with integral control, but with improved transient performance. Integral action is introduced in the sliding mode design using the recently developed technique of “conditional integrators", and it is shown that robust regulation is achieved with asymptotically constant exogenous signals, without degrading the transient response. Through extensive simulation on the nonlinear multiple-input multiple-output (MIMO) longitudinal model of the F-16 aircraft, it is shown that the conditional integrator design outperforms the one based on the conventional linear control, without requiring any scheduling.

Keywords: Sliding-mode Control, Integral Control, Model Following, F-16 Longitudinal Dynamics, Pitch-Rate Control.

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147 Pulse Generator with Constant Pulse Width

Authors: Hanif Che Lah, Wee Leong Son, Rozita Borhan

Abstract:

This paper is about method to produce a stable and accurate constant output pulse width regardless of the amplitude, period and pulse width variation of the input signal source. The pulse generated is usually being used in numerous applications as the reference input source to other circuits in the system. Therefore, it is crucial to produce a clean and constant pulse width to make sure the system is working accurately as expected.

Keywords: Amplitude, Constant Pulse Width, Frequency Divider, Pulse Generator.

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146 Matrix Based Synthesis of EXOR dominated Combinational Logic for Low Power

Authors: Padmanabhan Balasubramanian, C. Hari Narayanan

Abstract:

This paper discusses a new, systematic approach to the synthesis of a NP-hard class of non-regenerative Boolean networks, described by FON[FOFF]={mi}[{Mi}], where for every mj[Mj]∈{mi}[{Mi}], there exists another mk[Mk]∈{mi}[{Mi}], such that their Hamming distance HD(mj, mk)=HD(Mj, Mk)=O(n), (where 'n' represents the number of distinct primary inputs). The method automatically ensures exact minimization for certain important selfdual functions with 2n-1 points in its one-set. The elements meant for grouping are determined from a newly proposed weighted incidence matrix. Then the binary value corresponding to the candidate pair is correlated with the proposed binary value matrix to enable direct synthesis. We recommend algebraic factorization operations as a post processing step to enable reduction in literal count. The algorithm can be implemented in any high level language and achieves best cost optimization for the problem dealt with, irrespective of the number of inputs. For other cases, the method is iterated to subsequently reduce it to a problem of O(n-1), O(n-2),.... and then solved. In addition, it leads to optimal results for problems exhibiting higher degree of adjacency, with a different interpretation of the heuristic, and the results are comparable with other methods. In terms of literal cost, at the technology independent stage, the circuits synthesized using our algorithm enabled net savings over AOI (AND-OR-Invert) logic, AND-EXOR logic (EXOR Sum-of- Products or ESOP forms) and AND-OR-EXOR logic by 45.57%, 41.78% and 41.78% respectively for the various problems. Circuit level simulations were performed for a wide variety of case studies at 3.3V and 2.5V supply to validate the performance of the proposed method and the quality of the resulting synthesized circuits at two different voltage corners. Power estimation was carried out for a 0.35micron TSMC CMOS process technology. In comparison with AOI logic, the proposed method enabled mean savings in power by 42.46%. With respect to AND-EXOR logic, the proposed method yielded power savings to the tune of 31.88%, while in comparison with AND-OR-EXOR level networks; average power savings of 33.23% was obtained.

Keywords: AOI logic, ESOP, AND-OR-EXOR, Incidencematrix, Hamming distance.

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145 Computation of Natural Logarithm Using Abstract Chemical Reaction Networks

Authors: Iuliia Zarubiieva, Joyun Tseng, Vishwesh Kulkarni

Abstract:

Recent researches has focused on nucleic acids as a substrate for designing biomolecular circuits for in situ monitoring and control. A common approach is to express them by a set of idealised abstract chemical reaction networks (ACRNs). Here, we present new results on how abstract chemical reactions, viz., catalysis, annihilation and degradation, can be used to implement circuit that accurately computes logarithm function using the method of Arithmetic-Geometric Mean (AGM), which has not been previously used in conjunction with ACRNs.

Keywords: Abstract chemical reaction network, DNA strand displacement, natural logarithm.

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144 Development of Precise Ephemeris Generation Module for Thaichote Satellite Operations

Authors: Manop Aorpimai, Ponthep Navakitkanok

Abstract:

In this paper, the development of the ephemeris generation module used for the Thaichote satellite operations is presented. It is a vital part of the flight dynamics system, which comprises, the orbit determination, orbit propagation, event prediction and station-keeping maneouvre modules. In the generation of the spacecraft ephemeris data, the estimated orbital state vector from the orbit determination module is used as an initial condition. The equations of motion are then integrated forward in time to predict the satellite states. The higher geopotential harmonics, as well as other disturbing forces, are taken into account to resemble the environment in low-earth orbit. Using a highly accurate numerical integrator based on the Burlish-Stoer algorithm the ephemeris data can be generated for long-term predictions, by using a relatively small computation burden and short calculation time. Some events occurring during the prediction course that are related to the mission operations, such as the satellite’s rise/set viewed from the ground station, Earth and Moon eclipses, the drift in groundtrack as well as the drift in the local solar time of the orbital plane are all detected and reported. When combined with other modules to form a flight dynamics system, this application is aimed to be applied for the Thaichote satellite and successive Thailand’s Earth-observation missions. 

Keywords: Flight Dynamics System, Orbit Propagation, Satellite Ephemeris, Thailand’s Earth Observation Satellite.

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143 Design of a Novel Fractal Multiband Planar Antenna with a CPW-Feed

Authors: T. Benyetho, L. El Abdellaoui, J. Terhzaz, H. Bennis, N. Ababssi, A. Tajmouati, A. Tribak, M. Latrach

Abstract:

This work presents a new planar multiband antenna based on fractal geometry. This structure is optimized and validated into simulation by using CST-MW Studio. To feed this antenna we have used a CPW line which makes it easy to be incorporated with integrated circuits. The simulation results presents a good matching input impedance and radiation pattern in the GSM band at 900 MHz and ISM band at 2.4 GHz. The final structure is a dual band fractal antenna with 70 x 70 mm² as a total area by using an FR4 substrate.

Keywords: Antenna, CPW, Fractal, GSM, Multiband.

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142 High-Speed Pipeline Implementation of Radix-2 DIF Algorithm

Authors: Christos Meletis, Paul Bougas, George Economakos , Paraskevas Kalivas, Kiamal Pekmestzi

Abstract:

In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital signal processing, systolic circuits, FFTalgorithm.

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141 Wireless Communicated Smart Wind Sensor

Authors: Zdenek Bohuslavek

Abstract:

Development of microprocessor controlled sensor for measurement of wind speed and direction is the aim of this study. Electrical circuits and software were developed to the existing electromechanical part of the sensor TM-W2 becoming the properties of so-called smart sensor. The measured data about wind speed (sensitivity 0.01 m/s) and direction (0-360° by step 10°) are transmitted as 16-bit information. The connection between sensor and control unit is realized by radio communication (FM 433 MHz). Transition range is 220 m if used Quad type antenna. This concept provides substitution of actual cable systems by wireless ones.

Keywords: smart wind sensor, anemometer, wind speed, wireless communication

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