Search results for: Input Power Factor

Authors: Tarek A. Kasmieh, Hassan S. Omran

Abstract:

This paper aims to give a full study of the dynamic behavior of a mono-phase active power filter. First, the principle of the parallel active power filter will be introduced. Then, a dimensioning procedure for all its components will be explained in detail, such as the input filter, the current and voltage controllers. This active power filter is simulated using OrCAD program showing the validity of the theoretical study.

Keywords: Active power filter, Power Quality, Hysteresiscurrent controller.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

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In this paper, a single phase soft switched Zero Voltage Transition and Zero Current Transition (ZVT-ZCT) Power Factor Correction (PFC) boost converter is proposed. In the proposed PFC converter, the main switch turns on with ZVT and turns off with ZCT without any additional voltage or current stresses. Auxiliary switch turns on and off with zero current switching (ZCS). Also, the main diode turns on with zero voltage switching (ZVS) and turns off with ZCS. The proposed converter has features like low cost, simple control and structure. The output current and voltage are controlled by the proposed PFC converter in wide line and load range. The theoretical analysis of converter is clarified and the operating steps are given in detail. The simulation results of converter are obtained for 500 W and 100 kHz. It is observed that the semiconductor devices operate with soft switching (SS) perfectly. So, the switching power losses are minimum. Also, the proposed converter has 0.99 power factor with sinusoidal current shape.

Keywords: Power factor correction, zero-voltage transition, zero-current transition, soft switching.

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Authors: A. Karimzad Ghavidel, M. Zadshakouyan

Abstract:

Laser cutting is a very common production method for cutting 2D polymeric parts. Developing of polymer composites with nano-fibers makes important their other properties like laser workability. The aim of this research is investigation of the influence different laser cutting conditions on the dimensional accuracy of parts and holes from poly methyl methacrylate (PMMA)/carbon nanotubes (CNTs) material. Experiments were carried out by considering of CNTs (in four level 0,0.5, 1 and 1.5% wt.%), laser power (60, 80, and 100 watt) and cutting speed 20, 30, and 40 mm/s as input variable factors. The results reveal that CNTs adding improves the laser workability of PMMA and the increasing of power has a significant effect on the part and hole size. The findings also show cutting speed is effective parameter on the size accuracy. Eventually, the statistical analysis of results was done, and calculated mathematical equations by the regression are presented for determining relation between input and output factor.

Keywords: Dimensional accuracy-PMMA-CNTs-laser cutting.

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Authors: Shazia Javed, Noor Atinah Ahmad

Abstract:

In this paper an efficient incomplete factorization preconditioner is proposed for the Least Mean Squares (LMS) adaptive filter. The proposed preconditioner is approximated from a priori knowledge of the factors of input correlation matrix with an incomplete strategy, motivated by the sparsity patter of the upper triangular factor in the QRD-RLS algorithm. The convergence properties of IPLMS algorithm are comparable with those of transform domain LMS(TDLMS) algorithm. Simulation results show efficiency and robustness of the proposed algorithm with reduced computational complexity.

Keywords: Autocorrelation matrix, Cholesky's factor, eigenvalue spread, Markov input.

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Authors: A. Muthuramalingam, S. Himavathi

Abstract:

Harmonic pollution and low power factor in power systems caused by power converters have been of great concern. To overcome these problems several converter topologies using advanced semiconductor devices and control schemes have been proposed. This investigation is to identify a low cost, small size, efficient and reliable ac to dc converter to meet the input performance index of UPS. The performance of single phase and three phase ac to dc converter along with various control techniques are studied and compared. The half bridge converter topology with linear current control is identified as most suitable. It is simple, energy efficient because of single switch power loss and transformer-less operation of UPS. The results are validated practically using a prototype built using IGBT and analog controller. The performance for both single and three-phase system is verified. Digital implementation of closed loop control achieves higher reliability. Its cost largely depends on chosen bit precision. The minimal bit precision for optimum converter performance is identified as 16-bit with fixed-point operation. From the investigation and practical implementation it is concluded that half bridge ac – dc converter along with digital linear controller meets the performance index of UPS for single and three phase systems.

Keywords: PFC, energy efficient, half bridge, ac-dc converter, boost topology, linear current control, digital bit precision.

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Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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Authors: Dody Ismoyo, Mohammad Awan, Norashikin Yahya

Abstract:

The presence of harmonic in power system is a major concerned to power engineers for many years. With the increasing usage of nonlinear loads in power systems, the harmonic pollution becomes more serious. One of the widely used computation algorithm for harmonic analysis is fast Fourier transform (FFT). In this paper, a harmonic analyzer using FFT was implemented on TMS320C6713 DSK. The supply voltage of 240 V 59 Hz is stepped down to 5V using a voltage divider in order to match the power rating of the DSK input. The output from the DSK was displayed on oscilloscope and Code Composer Studio™ software. This work has demonstrated the possibility of analyzing the 240V power supply harmonic content using the DSK board.

Keywords: Harmonic Analysis, DSP.

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Authors: Boram Kim, Shigeyasu Uno, Kazuo Nakazato

Abstract:

Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.

Keywords: continuous time, delta sigma, A/D converter, RFID, biosensor, CMOS

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Authors: M. Salehi, A. A. Motie Birjandi, F. Namdari

Abstract:

Weak damping of low frequency oscillations is a frequent phenomenon in electrical power systems. These frequencies can be damped by power system stabilizers. Unified power flow controller (UPFC), as one of the most important FACTS devices, can be applied to increase the damping of power system oscillations and the more effect of this controller on increasing the damping of oscillations depends on its proper placement in power systems. In this paper, a technique based on controllability is proposed to select proper location of UPFC and the best input control signal in order to enhance damping of power oscillations. The effectiveness of the proposed technique is demonstrated in IEEE 9 bus power system.

Keywords: Unified power flow controller (UPFC), controllability, small signal analysis, eigenvalues.

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Authors: A. Moussouni, L. Mouzai, M. Bouhadef

Abstract:

The purpose of this investigation is to relate the rain power and the overland flow power to soil erodibility to assess the effects of both parameters on soil erosion using variable rainfall intensity on remoulded agricultural soil. Six rainfall intensities were used to simulate the natural rainfall and are as follows: 12.4mm/h, 20.3mm/h, 28.6mm/h, 52mm/h, 73.5mm/h and 103mm/h. The results have shown that the relationship between overland flow power and rain power is best represented by a linear function (R2=0.99). As regards the relationships between soil erodibility factor and rain and overland flow powers, the evolution of both parameters with the erodibility factor follow a polynomial function with high coefficient of determination. From their coefficients of determination (R2=0.95) for rain power and (R2=0.96) for overland flow power, we can conclude that the flow has more power to detach particles than rain. This could be explained by the fact that the presence of particles, already detached by rain and transported by the flow, give the flow more weight and then contribute to the detachment of particles by collision.

Keywords: Laboratory experiments, soil erosion, flow power, erodibility, rainfall intensity.

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Authors: ChangWoo Lee, Young Kow Lee, Sung Jun Ban, SungHoo Choi, Sang Woo Kim

Abstract:

This paper suggests a new Affine Projection (AP) algorithm with variable data-reuse factor using the condition number as a decision factor. To reduce computational burden, we adopt a recently reported technique which estimates the condition number of an input data matrix. Several simulations show that the new algorithm has better performance than that of the conventional AP algorithm.

Keywords: Affine projection algorithm, variable data-reuse factor, condition number, convergence rate, misalignment.

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Authors: I. Habi, M. Bouguerra, D. Ouahdi, H. Meglouli

Abstract:

In this paper, we apply the PQ theory with shunt active power filter in an unbalanced and distorted power system voltage to compensate the perturbations generated by non linear load. The power factor is also improved in the current source. The PLL system is used to extract the fundamental component of the even sequence under conditions mentioned of the power system voltage.

Keywords: Converter, power filter, harmonies, non-linear load, pq theory, PLL, unbalanced voltages, distorted voltages.

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Authors: Khalil Monfaredi, Hassan Faraji Baghtash, Majid Abbasi

Abstract:

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.

Keywords: Analog circuits, Current mirror, high frequency, Low power, Low voltage.

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Authors: Taufik Taufik, Tadeus Gunawan, Dale Dolan, Makbul Anwari

Abstract:

Multiphasing of dc-dc converters has been known to give technical and economical benefits to low voltage high power buck regulator modules. A major advantage of multiphasing dc-dc converters is the improvement of input and output performances in the buck converter. From this aspect, a potential use would be in renewable energy where power quality plays an important factor. This paper presents the design of a 2-phase 200W boost converter for battery charging application. Analysis of results from hardware measurement of the boost converter demonstrates the benefits of using multiphase. Results from the hardware prototype of the 2-phase boost converter further show the potential extension of multiphase beyond its commonly used low voltage high current domains.

Keywords: Multiphase, boost converter, power electronics.

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Authors: M. Susithra, R. Gnanadass

Abstract:

Ancillary services are support services which are essential for humanizing and enhancing the reliability and security of the electric power system. Reactive power ancillary service is one of the important ancillary services in a restructured electricity market which determines the cost of supplying ancillary services and finding of how this cost would change with respect to operating decisions. This paper presents a new formation that can be used to minimize the Independent System Operator (ISO)’s total payment for reactive power ancillary service. The modified power flow tracing algorithm estimates the availability of reserve reactive power for ancillary service. In order to find optimum reactive power dispatch, Biogeography based optimization method (BPO) is proposed. Market Reactive Clearing Price (MRCP) is then estimated and it encourages generator companies (GENCOs) to participate in an ancillary service. Finally, optimal weighting factor and real time utilization factor of reactive power give the minimum ISO’s total payment. The effectiveness of proposed design is verified using IEEE 30 bus system.

Keywords: Biogeography based optimization method, Power flow tracing method, Reactive generation capability curve and Reactive power ancillary service.

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Authors: Yu-Wei Chang, Chiao-Hung Cheng, Wen-Fang Wu, Sih-Li Chen

Abstract:

This article experimentally investigates the thermal performance of thermoelectric air-cooling module which comprises a thermoelectric cooler (TEC) and an air-cooling heat sink. The influences of input current and heat load are determined. And performances under each situation are quantified by thermal resistance analysis. Since TEC generates Joule heat, this nature makes construction of thermal resistance network difficult. To simplify the analysis, this article emphasizes on the resistance heat load might meet when passing through the device. Therefore, the thermal resistances in this paper are to divide temperature differences by heat load. According to the result, there exists an optimum input current under every heating power. In this case, the optimum input current is around 6A or 7A. The performance of the heat sink would be improved with TEC under certain heating power and input current, especially at a low heat load. According to the result, the device can even make the heat source cooler than the ambient. However, TEC is not always effective at every heat load and input current. In some situation, the device works worse than the heat sink without TEC. To determine the availability of TEC, this study figures out the effective operating region in which the TEC air-cooling module works better than the heat sink without TEC. The result shows that TEC is more effective at a lower heat load. If heat load is too high, heat sink with TEC will perform worse than without TEC. The limit of this device is 57W. Besides, TEC is not helpful if input current is too high or too low. There is an effective range of input current, and the range becomes narrower when the heat load grows.

Keywords: Thermoelectric cooler, TEC, electronic cooling, heat sink.

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Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

Abstract:

In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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Authors: Jihyung Kim, Taejin Kim, Sungho Park, Jun-Dong Cho

Abstract:

A conventional binding method for low power in a high-level synthesis mainly focuses on finding an optimal binding for an assumed input data, and obtains only one binding table. In this paper, we show that a binding method which uses multiple binding tables gets better solution compared with the conventional methods which use a single binding table, and propose a dynamic bus binding scheme for low power using multiple binding tables. The proposed method finds multiple binding tables for the proper partitions of an input data, and switches binding tables dynamically to produce the minimum total switching activity. Experimental result shows that the proposed method obtains a binding solution having 12.6-28.9% smaller total switching activity compared with the conventional methods.

Keywords: low power, bus binding, switching activity, multiplebinding tables

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Authors: E. Taslak, C. Kocatepe, O. Arıkan, C. F. Kumru

Abstract:

In insulation and cooling of power transformers various liquids are used. Mineral oils have wide availability and low cost. However, they have a poor biodegradability potential and lower fire point in comparison with other insulating liquids. Use of a liquid having high biodegradability is important due to environmental consideration. This paper investigates edible corn oil as an alternative to mineral oil. Various properties of mineral and corn oil like breakdown voltage, dissipation factor, relative dielectric constant, power loss and resistivity were measured according to different standards.

Keywords: Breakdown voltage, corn oil, dissipation factor, mineral oil, power loss, relative dielectric constant, resistivity.

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Authors: M. Marsadek, A. Mohamed

Abstract:

Power system security analysis is the most time demanding process due to large number of possible contingencies that need to be analyzed.  In a power system, any contingency resulting in security violation such as line overload or low voltage may occur for a number of reasons at any time.  To efficiently rank a contingency, both probability and the extent of security violation must be considered so as not to underestimate the risk associated with the contingency. This paper proposed a contingency ranking method that take into account the probabilistic nature of power system and the severity of contingency by using a newly developed method based on risk factor.  The proposed technique is implemented on IEEE 24-bus system.

Keywords: Line overload, low voltage, probability, risk factor, severity.

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Authors: M. H. Al-Mansoori, W. S. Al-Ghaithi, F. N. Hasoon

Abstract:

In this paper, we experimentally investigate the performance of an efficient high gain triple-pass L-band Erbium-Doped Fiber (EDF) amplifier structure with a single pump source. The amplifier gain and noise figure variation with EDF pump power, input signal power and wavelengths have been investigated. The generated backward Amplified Spontaneous Emission (ASE) noise of the first amplifier stage is suppressed by using a tunable band-pass filter. The amplifier achieves a signal gain of 55 dB with low noise figure of 3.8 dB at -50 dBm input signal power. The amplifier gain shows significant improvement of 12.8 dB compared to amplifier structure without ASE suppression.

Keywords: Optical amplifiers, EDFA, L-band, optical networks.

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Authors: Renbin Dai, Rana Arslan Ali Khan

Abstract:

The design of Class A and Class AB 2-stage X band Power Amplifier is described in this report. This power amplifier is part of a transceiver used in radar for monitoring iron characteristics in a blast furnace. The circuit was designed using foundry WIN Semiconductors. The specification requires 15dB gain in the linear region, VSWR nearly 1 at input as well as at the output, an output power of 10 dBm and good stable performance in the band 10.9-12.2 GHz. The design was implemented by using inter-stage configuration, the Class A amplifier was chosen for driver stage i.e. the first amplifier focusing on the gain and the output amplifier conducted at Class AB with more emphasis on output power.

Keywords: Power amplifier, Class AB, Class A, MMIC, 2-stage, X band.

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

Abstract:

A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.

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Authors: Lei Yao, Jia Hao Cheong, Rui-Feng Xue, Minkyu Je

Abstract:

A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.

Keywords: Implantable biomedical devices, wireless power transfer, LDO, rectifier, closed-loop power control

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Authors: Jyh-Da Wei, Hsin-Chen Tsai

Abstract:

This work presents a novel means of extracting fixedlength parameters from voice signals, such that words can be recognized in linear time. The power and the zero crossing rate are first calculated segment by segment from a voice signal; by doing so, two feature sequences are generated. We then construct an FIR system across these two sequences. The parameters of this FIR system, used as the input of a multilayer proceptron recognizer, can be derived by recursive LSE (least-square estimation), implying that the complexity of overall process is linear to the signal size. In the second part of this work, we introduce a weighting factor λ to emphasize recent input; therefore, we can further recognize continuous speech signals. Experiments employ the voice signals of numbers, from zero to nine, spoken in Mandarin Chinese. The proposed method is verified to recognize voice signals efficiently and accurately.

Keywords: Speech Recognition, FIR system, Recursive LSE, Multilayer Perceptron

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Authors: Tao Dai, Andy Adler, Behnam Shahrrava

Abstract:

This paper presents a forgetting factor scheme for variable step-size affine projection algorithms (APA). The proposed scheme uses a forgetting processed input matrix as the projection matrix of pseudo-inverse to estimate system deviation. This method introduces temporal weights into the projection matrix, which is typically a better model of the real error's behavior than homogeneous temporal weights. The regularization overcomes the ill-conditioning introduced by both the forgetting process and the increasing size of the input matrix. This algorithm is tested by independent trials with coloured input signals and various parameter combinations. Results show that the proposed algorithm is superior in terms of convergence rate and misadjustment compared to existing algorithms. As a special case, a variable step size NLMS with forgetting factor is also presented in this paper.

Keywords: Adaptive signal processing, affine projection algorithms, variable step-size adaptive algorithms, regularization.

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

Abstract:

This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: Energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm.

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ∼72% PAE and output power of >39dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The loadand source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: Power Amplifier (PA), GaN HEMT, Class-J and Class-E, High Efficiency.

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