Commenced in January 2007
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Edition: International
Paper Count: 32129
Dynamic Bus Binding for Low Power Using Multiple Binding Tables

Authors: Jihyung Kim, Taejin Kim, Sungho Park, Jun-Dong Cho


A conventional binding method for low power in a high-level synthesis mainly focuses on finding an optimal binding for an assumed input data, and obtains only one binding table. In this paper, we show that a binding method which uses multiple binding tables gets better solution compared with the conventional methods which use a single binding table, and propose a dynamic bus binding scheme for low power using multiple binding tables. The proposed method finds multiple binding tables for the proper partitions of an input data, and switches binding tables dynamically to produce the minimum total switching activity. Experimental result shows that the proposed method obtains a binding solution having 12.6-28.9% smaller total switching activity compared with the conventional methods.

Keywords: low power, bus binding, switching activity, multiplebinding tables

Digital Object Identifier (DOI):

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[1] J. Chang and M. Pedram, "Module assignment for low power," " in Proc. Eur. Design Automation Conf., pp.376-381, 1996.
[2] Y. Choi and T. Kim, "An efficient low-power binding algorithm in high-level synthesis," IEEE Int. Symp. On Circuits and Systems, vol. 4, pp. 321-324, 2002.
[3] C. Lyuh and T. Kim, "High-level synthesis for low power based on network flow method," " IEEE Trans. VLSI, vol. 1, no. 3, pp. 309-320, 2003
[4] X. Xing and C. C. Jong, "A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis," Microelectronics Journal, vol. 38, no. 4-5, pp. 595-605, 2007.
[5] H. Sankaran and S. Katkoori, "Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis," in Proc. 4th IEEE Intl. Symp. On Electronics Design, Test & Applications, pp. 454-457, 2008.
[6] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low power methodology manual : for system-on-chip design, Springer, pp. 4-7, 2007.
[7] J. Kim and J. Cho, "Low power bus binding exploiting optimal substructure," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E94-A, no. 1, pp. 332-341, 2011.