Search results for: Implementation.FPGA.

Authors: Amira Abbes Kheriji, Faouzi Bouani, Mekki Ksouri, Mohamed Ben Ahmed

Abstract:

Model Predictive Control (MPC) is increasingly being proposed for real time applications and embedded systems. However comparing to PID controller, the implementation of the MPC in miniaturized devices like Field Programmable Gate Arrays (FPGA) and microcontrollers has historically been very small scale due to its complexity in implementation and its computation time requirement. At the same time, such embedded technologies have become an enabler for future manufacturing enterprises as well as a transformer of organizations and markets. Recently, advances in microelectronics and software allow such technique to be implemented in embedded systems. In this work, we take advantage of these recent advances in this area in the deployment of one of the most studied and applied control technique in the industrial engineering. In fact in this paper, we propose an efficient framework for implementation of Generalized Predictive Control (GPC) in the performed STM32 microcontroller. The STM32 keil starter kit based on a JTAG interface and the STM32 board was used to implement the proposed GPC firmware. Besides the GPC, the PID anti windup algorithm was also implemented using Keil development tools designed for ARM processor-based microcontroller devices and working with C/Cµ langage. A performances comparison study was done between both firmwares. This performances study show good execution speed and low computational burden. These results encourage to develop simple predictive algorithms to be programmed in industrial standard hardware. The main features of the proposed framework are illustrated through two examples and compared with the anti windup PID controller.

Keywords: Embedded systems, Model Predictive Control, microcontroller, Keil tool.

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Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: Channel simulation, electromagnetic simulation, power-aware signal integrity analysis, power integrity, PIPro.

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Authors: Mushavhanamadi K., Mbohwa C.

Abstract:

This paper presents the findings of the investigation of ERP implementation, challenges experiences by a South African Company in ERP implementation, success factors, failures, and propose recommendations to improve ERP implementation. The data collections methods used are questionnaires. The paper contributes to discussion on ERP implementation in developing economics.

Keywords: CSF, ERP, MRP, MRP II.

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Authors: Rotchanakitumnuai, Siriluck

Abstract:

The objectives of the study are to examine the determinants of ERP implementation success factors of ERP implementation. The result indicates that large scale ERP implementation success consist of eight factors: project management competence, knowledge sharing, ERP system quality , understanding, user involvement, business process re-engineering, top management support, organization readiness.

Keywords: large scale ERP, implementation success factors, Thailand

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Authors: Fatemeh Nikpay, Rodina Binti Ahmad, Babak Darvish Rouhani

Abstract:

Enterprise Architecture (EA) is employed by enterprises for providing integrated Information Systems (ISs) in order to support alignment of their business and Information Technology (IT). Evaluation of EA implementation can support enterprise to reach intended goals. There are some problems in current evaluation methods of EA implementation that lead to ineffectiveness implementation of EA. This paper represents current issues on evaluation of EA implementation. In this regard, we set the framework in order to represent evaluation’s issues based on their functionality and structure. The results of this research not only increase the knowledge of evaluation, but also could be useful for both academics and practitioners in order to realize the current situation of evaluations.

Keywords: Current issues on EA, implementation evaluation, Evaluation, Enterprise Architecture, Evaluation of Enterprise Architecture Implementation.

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Authors: S. Mohamed Rabeek, Mi Kyoung Park, M. Annamalai Arasu

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This paper presents a design of a wireless read out system for tracking the frequency shift of the polymer coated piezoelectric micro electromechanical resonator due to gas absorption. The measure of this frequency shift indicates the percentage of a particular gas the sensor is exposed to. It is measured using an oscillator and an FPGA based frequency counter by employing the resonator as a frequency determining element in the oscillator. This system consists of a Gas Sensing Wireless Readout (GSWR) and an USB Wireless Transceiver (UWT). GSWR consists of an oscillator based on a trans-impedance sustaining amplifier, an FPGA based frequency readout, a sub 1GHz wireless transceiver and a micro controller. UWT can be plugged into the computer via USB port and function as a wireless module to transfer gas sensor data from GSWR to the computer through its USB port. GUI program running on the computer periodically polls for sensor data through UWT - GSWR wireless link, the response from GSWR is logged in a file for post processing as well as displayed on screen.

Keywords: Gas sensor, GSWR, micro-mechanical system, UWT, volatile emissions.

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Authors: Babak Darvish Rouhani, Mohd Naz’ri Mahrin, Fatemeh Nikpay, Maryam Khanian Najafabadi, Pourya Nikfard

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Enterprise Architecture (EA) Implementation Methodologies have become an important part of EA projects. Several implementation methodologies have been proposed, as a theoretical and practical approach, to facilitate and support the development of EA within an enterprise. A significant question when facing the starting of EA implementation is deciding which methodology to utilize. In order to answer this question, a framework with several criteria is applied in this paper for the comparative analysis of existing EA implementation methodologies. Five EA implementation methodologies including: EAP, TOGAF, DODAF, Gartner, and FEA are selected in order to compare with proposed framework. The results of the comparison indicate that those methodologies have not reached a sufficient maturity as whole due to lack of consideration on requirement management, maintenance, continuum, and complexities in their process. The framework has also ability for the evaluation of any kind of EA implementation methodologies.

Keywords: Enterprise Architecture, Enterprise Architecture Implementation Methodology. EAIM, Evaluating EAIM, Framework for evaluation.

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Authors: Turan Erman Erkan

Abstract:

Business Process Reengineering (BPR) is an essential tool before an information system project implementation. Enterprise Resource Planning (ERP) projects definitely require the standardization and fixation of business processes from customer order to shipment. Therefore, ERP implementations are well proven to be coupled with BPR, although the extend and timing of BPR with respect to ERP implementation differ. This study aims at analyzing the effects of BPR on ERP implementation success. Basing on two Turkish ERP implementations in pharmaceutical sector, a comparative study is performed. One of the ERP implementations took place after a BPR implementation, whereas the other implementation was without a prior BPR application. Both implementations have been realized with the same consultant team, the case with prior BPR implementation going live first. The results of the case study reveal that if business processes are not optimized and improved before an ERP implementation, ERP live system would face with disharmony problems of processes and processes automated by ERP. This suggests a definite precedence relationship between BPR and ERP applications

Keywords: Business Process Reengineering, Enterprise Resource Planning

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Authors: S. J. Arif

Abstract:

In the presented technique, a simple method is given for accurate measurement and control of power frequency deviation. The sinusoidal signal for which the frequency deviation measurement is required is transformed to a low voltage level and passed through a zero crossing detector to convert it into a pulse train. Another stable square wave signal of 10 KHz is obtained using a crystal oscillator and decade dividing assemblies (DDA). These signals are combined digitally and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded to make them equally suitable for both control applications and display units. The developed circuit using discrete components has a resolution of 0.5 Hz and completes measurement within 20 ms. The realized circuit is simulated and synthesized using Verilog HDL and subsequently implemented on FPGA. The results of measurement on FPGA are observed on a very high resolution logic analyzer. These results accurately match the simulation results as well as the results of same circuit implemented with discrete components. The proposed system is suitable for accurate measurement and control of power frequency deviation.

Keywords: Digital encoder for frequency measurement, frequency deviation measurement, measurement and control systems, power systems.

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Authors: Si Mon Kueh, Tom J. Kazmierski

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There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

Keywords: Artificial Neural Networks, bit-serial neural processor, FPGA, Neural Processing Element.

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Authors: Nisachon Mawai, Jeerapat Ngaoprasertwong

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This study reports the implementation of Good Manufacturing Practice (GMP) in a polycarbonate film processing plant. The implementation of GMP took place with the creation of a multidisciplinary team. It was carried out in four steps: conduct gap assessment, create gap closure plan, close gaps, and follow up the GMP implementation. The basis for the gap assessment is the guideline for GMP for plastic materials and articles intended for Food Contact Material (FCM), which was edited by Plastic Europe. The effective results of the GMP implementation in this study showed 100% completion of gap assessment. The key success factors for implementing GMP in production process are the commitment, intention and support of top management.

Keywords: Implementation, Good Manufacturing Practice, Polycarbonate Film, Food Contact Materials.

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Authors: Tomyslav Sledevič, Artūras Serackis, Gintautas Tamulevičius, Dalius Navakauskas

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Paper presents an comparative evaluation of features extraction algorithm for a real-time isolated word recognition system based on FPGA. The Mel-frequency cepstral, linear frequency cepstral, linear predictive and their cepstral coefficients were implemented in hardware/software design. The proposed system was investigated in speaker dependent mode for 100 different Lithuanian words. The robustness of features extraction algorithms was tested recognizing the speech records at different signal to noise rates. The experiments on clean records show highest accuracy for Mel-frequency cepstral and linear frequency cepstral coefficients. For records with 15 dB signal to noise rate the linear predictive cepstral coefficients gives best result. The hard and soft part of the system is clocked on 50 MHz and 100 MHz accordingly. For the classification purpose the pipelined dynamic time warping core was implemented. The proposed word recognition system satisfy the real-time requirements and is suitable for applications in embedded systems.

Keywords: Isolated word recognition, features extraction, MFCC, LFCC, LPCC, LPC, FPGA, DTW.

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Authors: Y. Bai, M. Bodlak, V. Frolov, S. Huber, V. Jary, I. Konorov, D. Levit, J. Novy, D. Steffen, O. Subrt, M. Virius

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Modern experiments in high energy physics impose great demands on the reliability, the efficiency, and the data rate of Data Acquisition Systems (DAQ). This contribution focuses on the development and deployment of the new communication library DIALOG for the intelligent, FPGA-based Data Acquisition System (iFDAQ) of the COMPASS experiment at CERN. The iFDAQ utilizing a hardware event builder is designed to be able to readout data at the maximum rate of the experiment. The DIALOG library is a communication system both for distributed and mixed environments, it provides a network transparent inter-process communication layer. Using the high-performance and modern C++ framework Qt and its Qt Network API, the DIALOG library presents an alternative to the previously used DIM library. The DIALOG library was fully incorporated to all processes in the iFDAQ during the run 2016. From the software point of view, it might be considered as a significant improvement of iFDAQ in comparison with the previous run. To extend the possibilities of debugging, the online monitoring of communication among processes via DIALOG GUI is a desirable feature. In the paper, we present the DIALOG library from several insights and discuss it in a detailed way. Moreover, the efficiency measurement and comparison with the DIM library with respect to the iFDAQ requirements is provided.

Keywords: Data acquisition system, DIALOG library, DIM library, FPGA, Qt framework, TCP/IP.

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Authors: Jun Wang, Tingcun Wei

Abstract:

The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, PLL megafunction, FPGA, time resolution, digitally-controlled DC-DC switching converter.

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Authors: Redha Elhuni, M. Munir Ahmad

Abstract:

The main purpose of this research is to construct a generic model for successful implementation of Total Quality Management (TQM) in Oil sector, and to find out the effects of this model on the organizational sustainability development (OSD) performance of Libyan oil and gas companies using the structured equation modeling (SEM) approach. The research approach covers both quantitative and qualitative methods. A questionnaire was developed in order to identify the quality factors that are seen by Libyan oil and gas companies to be critical to the success of TQM implementation. Hypotheses were developed to evaluate the impact of TQM implementation on O SD. Data analysis reveals that there is a significant positive effect of the TQM implementation on OSD. 24 quality factors are found to be critical and absolutely essential for successful TQM implementation. The results generated a structure of the TQMSD implementation framework based on the four major road map constructs (Top management commitment, employee involvement and participation, customer-driven processes, and continuous improvement culture).

Keywords: TQM, CQFs, Oil & Gas, OSD, Libya.

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Authors: Shobha Sharma, Amita Dev, Akanksha Kant

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Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.

Keywords: Detection of edges, Vedic multiplier, image processing, Urdhva Tiryakbhyam sutra.

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Authors: Hazem M. El-Bakry

Abstract:

Principal Component Analysis (PCA) has many different important applications especially in pattern detection such as face detection / recognition. Therefore, for real time applications, the response time is required to be as small as possible. In this paper, new implementation of PCA for fast face detection is presented. Such new implementation is designed based on cross correlation in the frequency domain between the input image and eigenvectors (weights). Simulation results show that the proposed implementation of PCA is faster than conventional one.

Keywords: Fast Face Detection, PCA, Cross Correlation, Frequency Domain

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Authors: G. Renuka Devi

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This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed drive is implemented in hardware. SVPWM pulses are generated in FPGA platform through Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding. The experimental results are observed under different loading conditions and compared with simulation results to validate the simulation model.

Keywords: Five-phase induction motor drive, field programmable gate array, indirect field oriented control, multi-phase, space vector pulse width modulation, voltage source inverter, very high speed integrated circuit hardware description language.

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Authors: A.Muthuramalingam, S.Himavathi

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Space Vector Modulation (SVM) is an optimum Pulse Width Modulation (PWM) technique for an inverter used in a variable frequency drive applications. It is computationally rigorous and hence limits the inverter switching frequency. Increase in switching frequency can be achieved using Neural Network (NN) based SVM, implemented on application specific chips. This paper proposes a neural network based SVM technique for a Voltage Source Inverter (VSI). The network proposed is independent of switching frequency. Different architectures are investigated keeping the total number of neurons constant. The performance of the inverter is compared for various switching frequencies for different architectures of NN based SVM. From the results obtained, the network with minimum resource and appropriate word length is identified. The bit precision required for this application is identified. The network with 8-bit precision is implemented in the IC XCV 400 and the results are presented. The performance of NN based general purpose SVM with higher bit precision is discussed.

Keywords: NN based SVM, FPGA Implementation, LayerMultiplexing, NN structure and Resource Reduction, PerformanceEvaluation

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis

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Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.

Keywords: Design Methodology, FPGA, Interconnection, Low-Energy, High-Performance, CAD tool.

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Authors: Amitrajit Sarkar

Abstract:

The use of Electronic Commerce (EC) technologies enables Small Medium Enterprises (SMEs) to improve their efficiency and competitive position. Much of the literature proposes an extensive set of benefits for organizations that choose to adopt and implement ECommerce systems. Factors of Business –to-business (B2B) E-Commerce adoption and implementation have been extensively investigated. Despite enormous attention given to encourage Small Medium Enterprises (SMEs) to adopt and implement E-Commerce, little research has been carried out in identifying the factors of Business-to-Consumer ECommerce adoption and implementation for SMEs. To conduct the study, Tornatsky and Fleischer model was adopted and tested in four SMEs located in Christchurch, New Zealand. This paper explores the factors that impact the decision and method of adoption and implementation of ECommerce systems in automobile industry. Automobile industry was chosen because the product they deal with i.e. cars are not a common commodity to be sold online, despite this fact the eCommerce penetration in automobile industry is high. The factors that promote adoption and implementation of E-Commerce technologies are discussed, together with the barriers. This study will help SME owners to effectively handle the adoption and implementation process and will also improve the chance of successful E-Commerce implementation. The implications of the findings for managers, consultants, and government organizations engaged in promoting E-Commerce adoption and implementation in small businesses and future research are discussed.

Keywords: E-Commerce in SMEs, E-Commerce in automobile industry, B2C E-Commerce, E-Commerce adoption and Implementation, E-Commerce Website Implementation, E-Commerce Models.

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Authors: André Trudel, Haiyi Zhang

Abstract:

Over the years, many implementations have been proposed for solving IA networks. These implementations are concerned with finding a solution efficiently. The primary goal of our implementation is simplicity and ease of use. We present an IA network implementation based on finite domain non-binary CSPs, and constraint logic programming. The implementation has a GUI which permits the drawing of arbitrary IA networks. We then show how the implementation can be extended to find all the solutions to an IA network. One application of finding all the solutions, is solving probabilistic IA networks.

Keywords: Constraint logic programming, CSP, logic, temporalreasoning.

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Authors: Reem Al-Kaabi

Abstract:

The concept of e-government has begun to spread among countries. It is based on the use of information communication technology (ICT) to fully utilize government resources, as well as to provide government services to citizens, investors and foreigners. Critical factors are the factors that are determined by the senior management of each organization; the success or failure of the organization depends on the effective implementation of critical factors. These factors vary from one organization to another according to their activity, size and functions. It is very important that organizations identify them in order to avoid the risk of implementing initiatives that may fail to work, while simultaneously exploiting opportunities that may succeed in working. The main focus of this paper is to investigate the majority of critical success factors (CSFs) associated with the implementation of e-government projects. This study concentrates on both technical and nontechnical factors. This paper concludes by listing the majority of CSFs relating to successful e-government implementation in Bahrain.

Keywords: Critical success factors, e-government, ICT, implementation, Kingdom of Bahrain.

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Authors: Babak Darvish Rouhani, Mohd Naz’ri Mahrin, Fatemeh Nikpay, Pourya Nikfard, Maryam Khanian Najafabadi

Abstract:

Enterprise Architecture (EA) is a strategy that is employed by enterprises in order to align their business and Information Technology (IT). EA is managed, developed, and maintained through Enterprise Architecture Implementation Methodology (EAIM). Effectiveness of EA implementation is the degree in which EA helps to achieve the collective goals of the organization. This paper analyzes the results of a survey that aims to explore the factors that affect the effectiveness of EAIM and specifically the relationship between factors and effectiveness of the output and functionality of EA project. The exploratory factor analysis highlights a specific set of five factors: alignment, adaptiveness, support, binding, and innovation. The regression analysis shows that there is a statistically significant and positive relationship between each of the five factors and the effectiveness of EAIM. Consistent with theory and practice, the most prominent factor for developing an effective EAIM is innovation. The findings contribute to the measuring the effectiveness of EA implementation project by providing an indication of the measurement implementation approaches which is used by the Enterprise Architects, and developing an effective EAIM.

Keywords: Enterprise Architecture, Enterprise Architecture Implementation Methodology, EA, Effectiveness, Factors, Implementation Methodology.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Y. Bai, M. Bodlak, V. Frolov, S. Huber, V. Jary, I. Konorov, D. Levit, J. Novy, D. Steffen, O. Subrt, M. Virius

Abstract:

In general, state-of-the-art Data Acquisition Systems (DAQ) in high energy physics experiments must satisfy high requirements in terms of reliability, efficiency and data rate capability. This paper presents the development and deployment of a debugging tool named DAQ Debugger for the intelligent, FPGA-based Data Acquisition System (iFDAQ) of the COMPASS experiment at CERN. Utilizing a hardware event builder, the iFDAQ is designed to be able to readout data at the average maximum rate of 1.5 GB/s of the experiment. In complex softwares, such as the iFDAQ, having thousands of lines of code, the debugging process is absolutely essential to reveal all software issues. Unfortunately, conventional debugging of the iFDAQ is not possible during the real data taking. The DAQ Debugger is a tool for identifying a problem, isolating the source of the problem, and then either correcting the problem or determining a way to work around it. It provides the layer for an easy integration to any process and has no impact on the process performance. Based on handling of system signals, the DAQ Debugger represents an alternative to conventional debuggers provided by most integrated development environments. Whenever problem occurs, it generates reports containing all necessary information important for a deeper investigation and analysis. The DAQ Debugger was fully incorporated to all processes in the iFDAQ during the run 2016. It helped to reveal remaining software issues and improved significantly the stability of the system in comparison with the previous run. In the paper, we present the DAQ Debugger from several insights and discuss it in a detailed way.

Keywords: DAQ debugger, data acquisition system, FPGA, system signals, Qt framework.

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Authors: Yun Bai

Abstract:

This paper is to investigate the impplementation of security mechanism in object oriented database system. Formal methods plays an essential role in computer security due to its powerful expressiveness and concise syntax and semantics. In this paper, both issues of specification and implementation in database security environment will be considered; and the database security is achieved through the development of an efficient implementation of the specification without compromising its originality and expressiveness.

Keywords: database security, authorization policy, logic basedspecification

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