Search results for: A.Muthuramalingam
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 5

Search results for: A.Muthuramalingam

5 Performance Evaluation of a Neural Network based General Purpose Space Vector Modulator

Authors: A.Muthuramalingam, S.Himavathi

Abstract:

Space Vector Modulation (SVM) is an optimum Pulse Width Modulation (PWM) technique for an inverter used in a variable frequency drive applications. It is computationally rigorous and hence limits the inverter switching frequency. Increase in switching frequency can be achieved using Neural Network (NN) based SVM, implemented on application specific chips. This paper proposes a neural network based SVM technique for a Voltage Source Inverter (VSI). The network proposed is independent of switching frequency. Different architectures are investigated keeping the total number of neurons constant. The performance of the inverter is compared for various switching frequencies for different architectures of NN based SVM. From the results obtained, the network with minimum resource and appropriate word length is identified. The bit precision required for this application is identified. The network with 8-bit precision is implemented in the IC XCV 400 and the results are presented. The performance of NN based general purpose SVM with higher bit precision is discussed.

Keywords: NN based SVM, FPGA Implementation, LayerMultiplexing, NN structure and Resource Reduction, PerformanceEvaluation

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4 Performances Comparison of Neural Architectures for On-Line Speed Estimation in Sensorless IM Drives

Authors: K.Sedhuraman, S.Himavathi, A.Muthuramalingam

Abstract:

The performance of sensor-less controlled induction motor drive depends on the accuracy of the estimated speed. Conventional estimation techniques being mathematically complex require more execution time resulting in poor dynamic response. The nonlinear mapping capability and powerful learning algorithms of neural network provides a promising alternative for on-line speed estimation. The on-line speed estimator requires the NN model to be accurate, simpler in design, structurally compact and computationally less complex to ensure faster execution and effective control in real time implementation. This in turn to a large extent depends on the type of Neural Architecture. This paper investigates three types of neural architectures for on-line speed estimation and their performance is compared in terms of accuracy, structural compactness, computational complexity and execution time. The suitable neural architecture for on-line speed estimation is identified and the promising results obtained are presented.

Keywords: Sensorless IM drives, rotor speed estimators, artificial neural network, feed- forward architecture, single neuron cascaded architecture.

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3 Novel SNC-NN-MRAS Based Speed Estimator for Sensor-Less Vector Controlled IM Drives

Authors: A.Venkadesan, S.Himavathi, A.Muthuramalingam

Abstract:

Rotor Flux based Model Reference Adaptive System (RF-MRAS) is the most popularly used conventional speed estimation scheme for sensor-less IM drives. In this scheme, the voltage model equations are used for the reference model. This encounters major drawbacks at low frequencies/speed which leads to the poor performance of RF-MRAS. Replacing the reference model using Neural Network (NN) based flux estimator provides an alternate solution and addresses such drawbacks. This paper identifies an NN based flux estimator using Single Neuron Cascaded (SNC) Architecture. The proposed SNC-NN model replaces the conventional voltage model in RF-MRAS to form a novel MRAS scheme named as SNC-NN-MRAS. Through simulation the proposed SNC-NN-MRAS is shown to be promising in terms of all major issues and robustness to parameter variation. The suitability of the proposed SNC-NN-MRAS based speed estimator and its advantages over RF-MRAS for sensor-less induction motor drives is comprehensively presented through extensive simulations.

Keywords: Sensor-less operation, vector-controlled IM drives, SNC-NN-MRAS, single neuron cascaded architecture, RF-MRAS, artificial neural network

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2 Evaluation of Power Factor Corrected AC - DC Converters and Controllers to meet UPS Performance Index

Authors: A. Muthuramalingam, S. Himavathi

Abstract:

Harmonic pollution and low power factor in power systems caused by power converters have been of great concern. To overcome these problems several converter topologies using advanced semiconductor devices and control schemes have been proposed. This investigation is to identify a low cost, small size, efficient and reliable ac to dc converter to meet the input performance index of UPS. The performance of single phase and three phase ac to dc converter along with various control techniques are studied and compared. The half bridge converter topology with linear current control is identified as most suitable. It is simple, energy efficient because of single switch power loss and transformer-less operation of UPS. The results are validated practically using a prototype built using IGBT and analog controller. The performance for both single and three-phase system is verified. Digital implementation of closed loop control achieves higher reliability. Its cost largely depends on chosen bit precision. The minimal bit precision for optimum converter performance is identified as 16-bit with fixed-point operation. From the investigation and practical implementation it is concluded that half bridge ac – dc converter along with digital linear controller meets the performance index of UPS for single and three phase systems.

Keywords: PFC, energy efficient, half bridge, ac-dc converter, boost topology, linear current control, digital bit precision.

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1 Neural Network Implementation Using FPGA: Issues and Application

Authors: A. Muthuramalingam, S. Himavathi, E. Srinivasan

Abstract:

.Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented

Keywords: FPGA implementation, multi-input neuron, neural network, nn based space vector modulator.

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