Search results for: Generic Pipeline Network-on-Chip Router Architecture

Authors: Abdelkrim Zitouni, Mounir Zid, Sami Badrouchi, Rached Tourki

Abstract:

The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.

Keywords: Dynamic arbiter, Generic router, Spidergon NoC, SoC.

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Authors: Yahia Salah, Med Lassaad Kaddachi, Rached Tourki

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This paper presents the design, implementation and evaluation of a micro-network, or Network-on-Chip (NoC), based on a generic pipeline router architecture. The router is designed to efficiently support traffic generated by multimedia applications on embedded multi-core systems. It employs a simplest routing mechanism and implements the round-robin scheduling strategy to resolve output port contentions and minimize latency. A virtual channel flow control is applied to avoid the head-of-line blocking problem and enhance performance in the NoC. The hardware design of the router architecture has been implemented at the register transfer level; its functionality is evaluated in the case of the two dimensional Mesh/Torus topology, and performance results are derived from ModelSim simulator and Xilinx ISE 9.2i synthesis tool. An example of a multi-core image processing system utilizing the NoC structure has been implemented and validated to demonstrate the capability of the proposed micro-network architecture. To reduce complexity of the image compression and decompression architecture, the system use image processing algorithm based on classical discrete cosine transform with an efficient zonal processing approach. The experimental results have confirmed that both the proposed image compression scheme and NoC architecture can achieve a reasonable image quality with lower processing time.

Keywords: Generic Pipeline Network-on-Chip Router Architecture, JPEG Image Compression, FPGA Hardware Implementation, Performance Evaluation.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: Mohib ur Rehman, Imran Ihsan, Mobin Uddin Ahmed, Nadeem Iftikhar, Muhammad Abdul Qadir

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Multimedia, as it stands now is perhaps the most diverse and rich culture around the globe. One of the major needs of Multimedia is to have a single system that enables people to efficiently search through their multimedia catalogues. Many Domain Specific Systems and architectures have been proposed but up till now no generic and complete architecture is proposed. In this paper, we have suggested a generic architecture for Multimedia Database. The main strengths of our architecture besides being generic are Semantic Libraries to reduce semantic gap, levels of feature extraction for more specific and detailed feature extraction according to classes defined by prior level, and merging of two types of queries i.e. text and QBE (Query by Example) for more accurate yet detailed results.

Keywords: Multimedia Database Architecture, Semantics, Feature Extraction, Ontology.

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Authors: Toshimi Munehira

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In order to optimize annual IT spending and to reduce the complexity of an entire system architecture, SOA trials have been started. It is common knowledge that to design an SOA system we have to adopt the top-down approach, but in reality silo systems are being made, so these companies cannot reuse newly designed services, and cannot enjoy SOA-s economic benefits. To prevent this situation, we designed a generic SOA development process referred to as the architecture of “mass customization." To define the generic detail development processes, we did a case study on an imaginary company. Through the case study, we could define the practical development processes and found this could vastly reduce updating development costs.

Keywords: SOA, BPM, Generic Model, MassCustomization

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Authors: Su Hyung Jo, Ki Young Kim, Sang Ho Lee

Abstract:

Security management has changed from the management of security equipments and useful interface to manager. It analyzes the whole security conditions of network and preserves the network services from attacks. Secure router technology has security functions, such as intrusion detection, IPsec(IP Security) and access control, are applied to legacy router for secure networking. It controls an unauthorized router access and detects an illegal network intrusion. This paper relates to a security engine management of router based on a security policy, which is the definition of security function against a network intrusion. This paper explains the security policy and designs the structure of security engine management framework.

Keywords: Policy server, security engine, security management, security policy

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Authors: Christos Meletis, Paul Bougas, George Economakos , Paraskevas Kalivas, Kiamal Pekmestzi

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In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital signal processing, systolic circuits, FFTalgorithm.

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Authors: Anilkumar Kothalil Gopalakrishnan

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A subjectively influenced router for vehicles in a fourjunction traffic system is presented. The router is based on a 3-layer Backpropagation Neural Network (BPNN) and a greedy routing procedure. The BPNN detects priorities of vehicles based on the subjective criteria. The subjective criteria and the routing procedure depend on the routing plan towards vehicles depending on the user. The routing procedure selects vehicles from their junctions based on their priorities and route them concurrently to the traffic system. That is, when the router is provided with a desired vehicles selection criteria and routing procedure, it routes vehicles with a reasonable junction clearing time. The cost evaluation of the router determines its efficiency. In the case of a routing conflict, the router will route the vehicles in a consecutive order and quarantine faulty vehicles. The simulations presented indicate that the presented approach is an effective strategy of structuring a subjective vehicle router.

Keywords: Backpropagation Neural Network, Backpropagationalgorithm, Greedy routing procedure, Subjective criteria, Vehiclepriority, Cost evaluation, Route generation

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Authors: Wang Zijuan, Ding Wenjing, Liu Ran

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If an unsteady heat transfer or heat impulse happens in part of the cryogenic pipeline system of large space environment simulation equipment while running in vacuum environment, it will lead to abnormal flow of the cryogenic fluid in the pipeline. When the situation gets worse, the cryogenic fluid in the pipeline will have phase change and a gas block which results in the malfunction of the cryogenic pipeline system. Referring to the structural parameter of a typical cryogenic pipeline system and the basic equation, an analytical model and a calculation model for cryogenic pipeline system can be built. The various factors which influence the thermal resistance of a cryogenic pipeline system can be analyzed and calculated by using the qualitative analysis relation deduced for thermal resistance of pipeline. The research conclusion could provide theoretical support for the design and operation of a cryogenic pipeline system

Keywords: pipeline, vacuum, vapor quality

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Authors: Ondruska Marek

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The article presents the whole model of IS/IT architecture exception governance. As first, the assumptions of presented model are set. As next, there is defined a generic governance model that serves as a basis for the architecture exception governance. The architecture exception definition and its attributes follow. The model respects well known approaches to the area that are described in the text, but it adopts higher granularity in description and expands the process view with all the next necessary governance components as roles, principles and policies, tools to enable the implementation of the model into organizations. The architecture exception process is decomposed into a set of processes related to the architecture exception lifecycle consisting of set of phases and architecture exception states. Finally, there is information about my future research related to this area.

Keywords: Architecture, dispensation, exception, governance, model

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Authors: Sang Su Lee, Sang Woo Lee, Yong Sung Jeon, Ki Young Kim

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IPsec protocol[1] is a set of security extensions developed by the IETF and it provides privacy and authentication services at the IP layer by using modern cryptography. In this paper, we describe both of H/W and S/W architectures of our router system, SRS-10. The system is designed to support high performance routing and IPsec VPN. Especially, we used Cavium-s CN2560 processor to implement IPsec processing in inline-mode.

Keywords: IP, router, VPN, IPsec.

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Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

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Authors: Haytham Al-Feel, M.A.Koutb, Hoda Suoror

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There are many problems associated with the World Wide Web: getting lost in the hyperspace; the web content is still accessible only to humans and difficulties of web administration. The solution to these problems is the Semantic Web which is considered to be the extension for the current web presents information in both human readable and machine processable form. The aim of this study is to reach new generic foundation architecture for the Semantic Web because there is no clear architecture for it, there are four versions, but still up to now there is no agreement for one of these versions nor is there a clear picture for the relation between different layers and technologies inside this architecture. This can be done depending on the idea of previous versions as well as Gerber-s evaluation method as a step toward an agreement for one Semantic Web architecture.

Keywords: Semantic Web Architecture, XML, RDF and Ontology.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: A. Habiboghli, R. Mostafaei, M. R.Meybodi

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Optical network uses a tool for routing which is called Latin router. These routers use particular algorithms for routing. In this paper, we present algorithm for configuration of optical network that is optimized regarding previous algorithm. We show that by decreasing the number of hops for source-destination in lightpath number of satisfied request is less. Also we had shown that more than single-hop lightpath relating single-hop lightpath is better.

Keywords: Latin Router, Constraint Satisfied, Wavelength, Optical Network

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Authors: Madjid Meriem-Benziane, Hamou Zahloul

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The demand of hydrocarbons has increased the construction of pipelines and the protection of the physical and mechanical integrity of the already existing infrastructure. Corrosion is the main reason of failures in the pipeline and it is mostly produced by acid (HCOOCH3). In this basis, a CFD code was used, in order to study the corrosion of internal wall of hydrocarbons pipeline. In this situation, the corrosion phenomenon shows a growing deposit, which causes defect damages (welding or fabrication) at diverse positions along the pipeline. The solution of the pipeline corrosion is based on the diminution of the Naphthenic acid.

Keywords: Pipeline, corrosion, Naphthenic acid (NA), CFD.

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Authors: Zuodong Liang, Dong-Sheng Jeng

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Seabed instability around an offshore pipeline is one of key factors that need to be considered in the design of offshore infrastructures. Unlike previous investigations, a three-dimensional numerical model for the wave-induced soil response around an offshore pipeline is proposed in this paper. The numerical model was first validated with 2-D experimental data available in the literature. Then, a parametric study will be carried out to examine the effects of wave, seabed characteristics and confirmation of pipeline. Numerical examples demonstrate significant influence of wave obliquity on the wave-induced pore pressures and the resultant seabed liquefaction around the pipeline, which cannot be observed in 2-D numerical simulation.

Keywords: Pore pressure, 3D wave model, seabed liquefaction, pipeline.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: Seung You Na, Daejung Shin, Jin Young Kim, Joo Hyun Jung, Yong-Gwan Won

Abstract:

To explore pipelines is one of various bio-mimetic robot applications. The robot may work in common buildings such as between ceilings and ducts, in addition to complicated and massive pipeline systems of large industrial plants. The bio-mimetic robot finds any troubled area or malfunction and then reports its data. Importantly, it can not only prepare for but also react to any abnormal routes in the pipeline. The pipeline monitoring tasks require special types of mobile robots. For an effective movement along a pipeline, the movement of the robot will be similar to that of insects or crawling animals. During its movement along the pipelines, a pipeline monitoring robot has an important task of finding the shapes of the approaching path on the pipes. In this paper we propose an effective solution to the pipeline pattern recognition, based on the fuzzy classification rules for the measured IR distance data.

Keywords: Bio-mimetic robots, Plant pipes monitoring, Pipepattern recognition.

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Authors: Souleymane Oumtanaga, Kadjo Tanon Lambert, Koné Tiémoman, Tety Pierre, Kimou KouadioProsper

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Multicast transmissions allow an host (the source) to send only one flow bound for a group of hosts (the receivers). Any equipment eager to belong to the group may explicitly register itself to that group via its multicast router. This router will be given the responsibility to convey all information relating to the group to all registered hosts. However in an environment in which the final receiver or the source frequently moves, the multicast flows need particular treatment. This constitutes one of the multicast transmissions problems around which several proposals were made in the Mobile IPv6 case in general. In this article, we describe the problems involved in this IPv6 multicast mobility and the existing proposals for their resolution. Then architecture will be proposed aiming to satisfy and optimize these transmissions in the specific case of a mobile multicast receiver in NC-HMIPv6 environment.

Keywords: Mobile IP, NC-HMIPv6, Multicast, MLD, PIM, SSM, Rendezvous Point.

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Authors: Mohamad Azmi Haniffa, Fakhruldin Mohd Hashim

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Pipeline infrastructures normally represent high cost of investment and the pipeline must be free from risks that could cause environmental hazard and potential threats to personnel safety. Pipeline integrity such monitoring and management become very crucial to provide unimpeded transportation and avoiding unnecessary production deferment. Thus proper cleaning and inspection is the key to safe and reliable pipeline operation and plays an important role in pipeline integrity management program and has become a standard industry procedure. In view of this, understanding the motion (dynamic behavior), prediction and control of the PIG speed is important in executing pigging operation as it offers significant benefits, such as estimating PIG arrival time at receiving station, planning for suitable pigging operation, and improves efficiency of pigging tasks. The objective of this paper is to review recent developments in speed control system of pipeline PIGs. The review carried out would serve as an industrial application in a form of quick reference of recent developments in pipeline PIG speed control system, and further initiate others to add-in/update the list in the future leading to knowledge based data, and would attract active interest of others to share their view points.

Keywords: Pipeline Inspection Gauge (PIG), In Line Inspection Tools (ILI), PIG motion, PIG speed control system

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Authors: Juyoung Kim, Taegeun Park

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In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.

Keywords: discrete wavelet transform, VLSI architecture, QMF lattice filter, pipelining.

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Authors: Sitalakshmi Venkatraman, Fiona Wahr, Anthony de Souza-Daw, Samuel Kaspi

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There is a growing emphasis on generic skills in higher education to match the changing skill-set requirements of the labour market. However, researchers and policy makers have not arrived at a consensus on the generic skills that actually contribute towards workplace employability and performance that complement and/or underpin discipline-specific graduate attributes. In order to strengthen the qualifications framework, a range of ‘generic’ learning outcomes have been considered for students undergoing higher education programs and among them it is necessary to have the fundamental generic skills such as literacy and numeracy at a level appropriate to the qualification type. This warrants for curriculum design approaches to contextualise the form and scope of these fundamental generic skills for supporting both students’ learning engagement in the course, as well as the graduate attributes required for employability and to progress within their chosen profession. Little research is reported in integrating such generic skills into discipline-specific learning outcomes. This paper explores the literature of the generic skills required for graduates from the discipline of Information Technology (IT) in relation to an Australian higher education institution. The paper presents the rationale of a proposed Bachelor of IT curriculum designed to contextualize the learning of these generic skills within the students’ discipline studies.

Keywords: Curriculum, employability, generic skills, graduate attributes, higher education, information technology.

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Authors: Khine Phyu, Aung Myint Aye

Abstract:

This paper presents results of measurements campaign carried out at a carrier frequency of 24GHz with the help of TPLINK router in indoor line-of-sight (LOS) scenarios. Firstly, the radio wave propagation strategies are analyzed in some rooms with router of point to point Ad hoc network. Then floor attenuation is defined for 3 floors in experimental region. The free space model and dual slope models are modified by considering the influence of corridor conditions on each floor. Using these models, indoor signal attenuation can be estimated in modeling of indoor radio wave propagation. These results and modified models can also be used in planning the networks of future personal communications services.

Keywords: radio wave signal analyzing, LOS radio wavepropagation, indoor radio wave propagation, free space model, tworay model and indoor attenuation.

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Authors: Bhavana Prakash Shrivastava, Kavita Khare

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This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router.

Keywords: Enhanced buffer, Gate delay, NOC, VCs, VCB.

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Authors: Ali Habiboghli, Rouhollah Mostafaei, Vasif Nabiyev

Abstract:

Optical network uses a tool for routing called Latin router. These routers use particular algorithms for routing. For example, we can refer to LDF algorithm that uses backtracking (one of CSP methods) for problem solving. In this paper, we proposed new approached for completion routing table (DRA&CRA algorithm) and compare with pervious proposed ways and showed numbers of backtracking, blocking and run time for DRA algorithm less than LDF and CRA algorithm.

Keywords: Latin Router, Constraint Satisfaction Problem, Wavelength Routing.

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Authors: Vipin Saxena, Deepa Raj

Abstract:

Unified Modeling language (UML) is one of the important modeling languages used for the visual representation of the research problem. In the present paper, UML model is designed for the Instruction pipeline which is used for the evaluation of the instructions of software programs. The class and sequence diagrams are designed & performance is evaluated for instructions of a sample program through a case study.

Keywords: UML, Instruction Pipeline, Class Diagram &Sequence Diagram.

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Authors: H. Gholami, M. Jalali Azizpour

Abstract:

Stress Corrosion Crack (SCC) in pipeline is a type of environmentally assisted cracking (EAC), since its discovery in 1965 as a possible cause of failure in pipeline, SCC has caused, on average, one of two failures per year in the U.S, According to the NACE SCC DA a pipe line segment is considered susceptible to SCC if all of the following factors are met: The operating stress exceeds 60% of specified minimum yield strength (SMYS), the operating temperature exceeds 38°C, the segment is less than 32 km downstream from a compressor station, the age of the pipeline is greater than 10 years and the coating type is other than Fusion Bonded Epoxy(FBE). In this paper as a practical experience in NISOC, Direct Assessment (DA) Method is used for identification SCC defect in unpiggable pipeline located downstream of compressor station.

Keywords: Stress Corrosion Crack, Direct Assessment, Disbondment, Transgranular SCC, Compressor Station.

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Authors: T. Davitashvili, G. Gubelidze

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In this paper two mathematical models for definition of gas accidental escape localization in the gas pipelines are suggested. The first model was created for leak localization in the horizontal branched pipeline and second one for leak detection in inclined section of the main gas pipeline. The algorithm of leak localization in the branched pipeline did not demand on knowledge of corresponding initial hydraulic parameters at entrance and ending points of each sections of pipeline. For detection of the damaged section and then leak localization in this section special functions and equations have been constructed. Some results of calculations for compound pipelines having two, four and five sections are presented. Also a method and formula for the leak localization in the simple inclined section of the main gas pipeline are suggested. Some results of numerical calculations defining localization of gas escape for the inclined pipeline are presented.

Keywords: Branched and inclined gas pipelines, leak detection, mathematical modeling.

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Authors: R. Kiš, M. Malcho, M. Janovcová

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This work aims to present a numerical analysis of the natural gas which flows through a high-pressure pipeline and an orifice plate, through the use of CFD methods. The paper contains CFD calculations for the flow of natural gas in a pipe with different geometry used for the orifice plates. One of them has a standard geometry and a shape without any deformation and the other is deformed by the action of the pressure differential. It shows the behavior of natural gas in a pipeline using the velocity profiles and pressure fields of the gas in both models with their differences. The entire research is based on the elimination of any inaccuracy which should appear in the flow of the natural gas measured in the high-pressure pipelines of the gas industry and which is currently not given in the relevant standard.

Keywords: Orifice plate, high-pressure pipeline, natural gas, CFD analysis.

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