Search results for: Pipelined converter

Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

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Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

Abstract:

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.

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Authors: Consalva J. Msigwa, Beda J. Kundy, Bakari M. M. Mwinyiwiwa,

Abstract:

This paper presents a method for obtaining the desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for obtaining the best control performance of the SAPF. To improve the performance of the PI controller, the feedback path to the integral term is introduced to compensate the winding up phenomenon due to integrator. Using Reference Frame Transformation, reference signals are transformed from a - b - c stationery frame to 0 - d - q rotating frame. Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.

Keywords: Phase Locked Loop (PLL), Voltage Source Converter (VSC), Shunt Active Power Filter (SAPF), PI, Pulse Width Modulation (PWM)

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Authors: Bhavana Prakash Shrivastava, Kavita Khare

Abstract:

This paper presents a synthesis and simulation of proposed enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input VCBs. This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is reduced to 15.65% and delay is reduced to 97.88% with respect to virtual channel router.

Keywords: Enhanced buffer, Gate delay, NOC, VCs, VCB.

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Authors: Kaumil B. Shah, Hina Chandwani

Abstract:

The modular multilevel converter (MMC) is one of the advanced topologies for medium and high-voltage applications. In high-power, high-voltage MMC, a large number of switching power devices are required. These switching power devices (IGBT) considerable switching losses. This paper analyzes the performance of different discontinuous pulse width modulation (DPWM) techniques and compares the results against a conventional carrier based pulse width modulation method, in order to reduce the switching losses of an MMC. The DPWM reference wave can be generated by adding the zero-sequence component to the original (sine) reference modulation signal. The result of the addition gives the reference signal of DPWM techniques. To minimize the switching losses of the MMC, the clamping period is controlled according to the absolute value of the output load current. No switching is generated in the clamping period so overall switching of the power device is reduced. The simulation result of the different DPWM techniques is compared with conventional carrier-based pulse-width modulation technique.

Keywords: Modular multilevel converter, discontinuous pulse width modulation, switching losses, zero-sequence voltage.

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Authors: Youcef Bekakra, Djilani Ben attous

Abstract:

This paper presents the study of a variable speed wind energy conversion system based on a Doubly Fed Induction Generator (DFIG) based on a sliding mode control applied to achieve control of active and reactive powers exchanged between the stator of the DFIG and the grid to ensure a Maximum Power Point Tracking (MPPT) of a wind energy conversion system. The proposed control algorithm is applied to a DFIG whose stator is directly connected to the grid and the rotor is connected to the PWM converter. To extract a maximum of power, the rotor side converter is controlled by using a stator flux-oriented strategy. The created decoupling control between active and reactive stator power allows keeping the power factor close to unity. Simulation results show that the wind turbine can operate at its optimum energy for a wide range of wind speed.

Keywords: Doubly fed induction generator, wind energy, wind turbine, sliding mode control, maximum power point tracking (MPPT).

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Authors: Liu Yi, Bao Liyong

Abstract:

Aiming at the problem of low efficiency of pipelined scheduling in periodic query-qualified service, this paper proposes a system service resource scheduling strategy with parallel optimized qualified service polling control. The paper constructs the polling queuing system and its mathematical model; firstly, the first-order and second-order characteristic parameter equations are obtained by partial derivation of the probability mother function of the system state variables, and the complete mathematical, analytical expressions of each system parameter are deduced after the joint solution. The simulation experimental results are consistent with the theoretical calculated values. The system performance analysis shows that the average captain and average period of the system have been greatly improved, which can better adapt to the service demand of delay-sensitive data in the dense data environment.

Keywords: Polling, parallel scheduling, mean queue length, average cycle time.

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Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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Authors: Farhan Beg

Abstract:

A Space Vector based Pulse Width Modulation control technique for the three-phase PWM converter is proposed in this paper. The proposed control scheme is based on a synchronous reference frame model. High performance and efficiency is obtained with regards to the DC bus voltage and the power factor considerations of the PWM rectifier thus leading to low losses. MATLAB/SIMULINK are used as a platform for the simulations and a SIMULINK model is presented in the paper. The results show that the proposed model demonstrates better performance and properties compared to the traditional SPWM method and the method improves the dynamic performance of the closed loop drastically. For the Space Vector based Pulse Width Modulation, Sine signal is the reference waveform and triangle waveform is the carrier waveform. When the value sine signal is large than triangle signal, the pulse will start produce to high. And then when the triangular signals higher than sine signal, the pulse will come to low. SPWM output will changed by changing the value of the modulation index and frequency used in this system to produce more pulse width. The more pulse width produced, the output voltage will have lower harmonics contents and the resolution increase.

Keywords: Power Factor, SVPWM, PWM rectifier, SPWM.

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Authors: M. M. Abutaleb, A. Hamdy, M. E. Abuelwafa, E. M. Saad

Abstract:

Optical flow is a research topic of interest for many years. It has, until recently, been largely inapplicable to real-time applications due to its computationally expensive nature. This paper presents a new reliable flow technique which is combined with a motion detection algorithm, from stationary camera image streams, to allow flow-based analyses of moving entities, such as rigidity, in real-time. The combination of the optical flow analysis with motion detection technique greatly reduces the expensive computation of flow vectors as compared with standard approaches, rendering the method to be applicable in real-time implementation. This paper describes also the hardware implementation of a proposed pipelined system to estimate the flow vectors from image sequences in real time. This design can process 768 x 576 images at a very high frame rate that reaches to 156 fps in a single low cost FPGA chip, which is adequate for most real-time vision applications.

Keywords: Optical flow, motion detection, real-time systems, FPGA.

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Authors: R. M. Siddiqui, D. Z. Moghaddam, T. R. Turlapati, S. H. Khan, I. Ul Ahad

Abstract:

Quality of 2D and 3D cross-sectional images produce by Computed Tomography primarily depend upon the degree of precision of primary and secondary X-Ray intensity detection. Traditional method of primary intensity detection is apt to errors. Recently the X-Ray intensity measurement system along with smart X-Ray sensors is developed by our group which is able to detect primary X-Ray intensity unerringly. In this study a new smart X-Ray sensor is developed using Light-to-Frequency converter TSL230 from Texas Instruments which has numerous advantages in terms of noiseless data acquisition and transmission. TSL230 construction is based on a silicon photodiode which converts incoming X-Ray radiation into the proportional current signal. A current to frequency converter is attached to this photodiode on a single monolithic CMOS integrated circuit which provides proportional frequency count to incoming current signal in the form of the pulse train. The frequency count is delivered to the center of PICDEM FS USB board with PIC18F4550 microcontroller mounted on it. With highly compact electronic hardware, this Demo Board efficiently read the smart sensor output data. The frequency output approaches overcome nonlinear behavior of sensors with analog output thus un-attenuated X-Ray intensities could be measured precisely and better normalization could be acquired in order to attain high resolution.

Keywords: Computed tomography, detector technology, X-Ray intensity measurement

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

Abstract:

Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication system. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. However the price paid for this high spectral efficiency and less intensive equalization is low power efficiency. OFDM signals are very sensitive to nonlinear effects due to the high Peak-to-Average Power Ratio (PAPR), which leads to the power inefficiency in the RF section of the transmitter. This paper investigates the effect of PAPR reduction on the performance parameter of multicarrier communication system. Performance parameters considered are power consumption of Power Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier efficiency, SNR of DAC and BER performance of the system. From our analysis it is found that irrespective of PAPR reduction technique being employed, the power consumption of PA and DAC reduces and power amplifier efficiency increases due to reduction in PAPR. Moreover, it has been shown that for a given BER performance the requirement of Input-Backoff (IBO) reduces with reduction in PAPR.

Keywords: BER, Crest Factor (CF), Digital-to-Analog Converter(DAC), Input-Backoff (IBO), Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), PowerAmplifier efficiency, SNR

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Authors: S. Doyle, G. A. Aggidis

Abstract:

Wave energy converter technologies continue to show good progress in worldwide research. One of the most researched technologies, the Oscillating Water Column (OWC), is arguably one of the most popular categories within the converter technologies due to its robustness, simplicity and versatility. However, the versatility of the OWC is still largely untapped with most deployments following similar trends with respect to applications and operating systems. As the competitiveness of the energy market continues to increase, the demand for wave energy technologies to be innovative also increases. For existing wave energy technologies, this requires identifying areas to diversify for lower costs of energy with respect to applications and synergies or integrated systems. This paper provides a review of all OWCs systems integrated into alternative applications in the past and present. The aspects and variation in their design, deployment and system operation are discussed. Particular focus is given to the Multi-OWCs (M-OWCs) and their great potential to increase capture on a larger scale, especially in synergy applications. It is made clear that these steps need to be taken in order to make wave energy a competitive and viable option in the renewable energy mix as progression to date shows that stand alone single function devices are not economical. Findings reveal that the trend of development is moving toward these integrated applications in order to reduce the Levelised Cost of Energy (LCOE) and will ultimately continue in this direction in efforts to make wave energy a competitive option in the renewable energy mix.

Keywords: Ocean energy, wave energy, oscillating water column, renewable energy, review.

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Authors: Rajesh Mehra, Bharti Thakur

Abstract:

In this paper, an Infinite Impulse Response (IIR) filter has been designed and simulated on an Field Programmable Gate Arrays (FPGA). The implementation is based on Multiply Add and Accumulate (MAC) algorithm which uses multiply operations for design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of target device. The designed filter has been synthesized on Digital Signal Processor (DSP) slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The proposed design is simulated with Matlab, synthesized with Xilinx Synthesis Tool, and implemented on FPGA devices. The Virtex 5 FPGA based design can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP based design. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications.

Keywords: Butterworth, DSP, IIR, MAC, FPGA.

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Authors: F. Haghjoo, M. Sarlak, S.M. Shahrtash

Abstract:

In order to perform on-line measuring and detection of PD signals, a total solution composing of an HFCT, A/D converter and a complete software package is proposed. The software package includes compensation of HFCT contribution, filtering and noise reduction using wavelet transform and soft calibration routines. The results have shown good performance and high accuracy.

Keywords: Partial Discharge, Measurement, On-line, HFCT

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Authors: Tomyslav Sledevič, Artūras Serackis, Gintautas Tamulevičius, Dalius Navakauskas

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Paper presents an comparative evaluation of features extraction algorithm for a real-time isolated word recognition system based on FPGA. The Mel-frequency cepstral, linear frequency cepstral, linear predictive and their cepstral coefficients were implemented in hardware/software design. The proposed system was investigated in speaker dependent mode for 100 different Lithuanian words. The robustness of features extraction algorithms was tested recognizing the speech records at different signal to noise rates. The experiments on clean records show highest accuracy for Mel-frequency cepstral and linear frequency cepstral coefficients. For records with 15 dB signal to noise rate the linear predictive cepstral coefficients gives best result. The hard and soft part of the system is clocked on 50 MHz and 100 MHz accordingly. For the classification purpose the pipelined dynamic time warping core was implemented. The proposed word recognition system satisfy the real-time requirements and is suitable for applications in embedded systems.

Keywords: Isolated word recognition, features extraction, MFCC, LFCC, LPCC, LPC, FPGA, DTW.

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Authors: Hafiz ul Azad, Dragan V.Lazic, Waqar Shahid

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This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Keywords: Field Programmable gate array (FPGA), Hardwaredescriptive Language (HDL), PID, Pipelining, Retiming, XilinxSystem Generator.

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Authors: Shahram Jafari, Mohammad-Ali Nikouei Mahani, Mohammad Arabnezhad, Mahdi Sharifi

Abstract:

Car accident is one of the major causes of death in many countries. Many researchers have attempted to design and develop techniques to increase car safety in the past recent years. In spite of all the efforts, it is still challenging to design a system adaptive to the driver rather than the automotive characteristics. In this paper, the adaptive car safety system is explained which attempts to find a balance.

Keywords: Analog to Digital Converter (ADC), AdaptiveCar Safety System, Multi-Media Card (MMC).

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Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC, Programmable Reference.

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Authors: S. Farag, A. Kupeman

Abstract:

In this paper, design of solid-state battery/supercapacitor emulator based on dc-dc boost converter is described. The emulator mimics charging behavior of any storage device based on a predefined behavior set by the user. The device is operated by a two-level control structure: high-level emulating controller and low- level input voltage controller. Simulation and experimental results are shown to demonstrate the emulator operation.

Keywords: Battery, Charger, Energy, Storage, Supercapacitor.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

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This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: Farzad Abdous

Abstract:

Fuel cell's system requires regulating circuit for voltage and current in order to control power in case of connecting to other generative devices or load. In this paper Fuel cell system and convertor, which is a multi-variable system, are controlled using sliding mode method. Use of weighting matrix in design procedure made it possible to regulate speed of control. Simulation results show the robustness and accuracy of proposed controller for controlling desired of outputs.

Keywords: DC-DC converter, Fuel cell, PEM, Slides mode control.

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Authors: Siyanda S. Biyela, Willie A. Cronje

Abstract:

This paper presents a desktop study of comparing two different wave energy to electricity technologies (WECs) using a techno-economic approach. This techno-economic approach forms basis of a framework for rapid comparison of current and future technologies. The approach also seeks to assist in investment and strategic decision making expediting future deployment of wave energy harvesting in South Africa.

Keywords: Cost of energy, tool, wave energy converter, WEC-Sim.

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Authors: I. Habi, M. Bouguerra, D. Ouahdi, H. Meglouli

Abstract:

In this paper, we apply the PQ theory with shunt active power filter in an unbalanced and distorted power system voltage to compensate the perturbations generated by non linear load. The power factor is also improved in the current source. The PLL system is used to extract the fundamental component of the even sequence under conditions mentioned of the power system voltage.

Keywords: Converter, power filter, harmonies, non-linear load, pq theory, PLL, unbalanced voltages, distorted voltages.

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Authors: Rafia Akhter, Aminul Hoque

Abstract:

Solar Cells are destined to supply electric energy beginning from primary resources. It can charge a battery up to 12V dc. For residential use an inverter for 12V dc to 220Vac conversion is desired. For this a static DC-AC converter is necessarily inserted between the solar cells and the distribution network. This paper describes a new P.W.M. strategy for a voltage source inverter. This modulation strategy reduces the energy losses and harmonics in the P.W.M. voltage source inverter. This technique allows the P.W.M. voltage source inverter to become a new feasible solution for solar home application.

Keywords: Boost Inverter, inverter, duty cycle, PWM

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Authors: Sing-Han Wang, Shiang-Hwua Yu, Chih-Po Yang

Abstract:

Repetitive control and feedback dithering modulation are applied to a single-phase voltage source inverter, with an aim to eliminate harmonics and stabilize the inverter under load variations. The proposed control and modulation scheme comprise multiple loops of feedback, which helps improve inverter performance and robustness. Experimental results show that the designed inverter exhibits very low distortion at its output with THD of about 0.3% under different load variations.

Keywords: Feedback dithering modulation, repetitive control, state feedback, inverter, harmonics elimination.

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Authors: Abolfazl Jalilvand, Mohammad Reza Feyzi, Sohrab Khanmohammad, Mohammad Bagher Bana Sharifian, Ali Sajjadi

Abstract:

Nowadays the control of stator voltage at a constant frequency is one of the traditional and low expense methods in order to control the speed of induction motors near its nominal speed. The torque of induction motor is a nonlinear function of the firing angle, phase angle and speed. In this paper the speed control of induction motor regarding various load torque and under different conditions will be investigated based on a fuzzy controller with inverse training.

Keywords: Three phase induction motor, AC converter, speedcontrol, fuzzy control.

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Authors: Yu-Sheng Lee, Qi An

Abstract:

Offset mismatch, gain mismatch, and time-skew error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (TIADC). This paper focused on the time-skew error. A new technique for calibrating time-skew error in M-channels TIADC is described, and simulation results are also presented.

Keywords: Calibration, time-skew error, time-interleavedanalog-to-digital converters.

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Authors: Thiago Brito Bezerra, Mauro Lopes de Freitas, Waldir Sabino da Silva Júnior

Abstract:

The Sigma-Delta A/D converters have been proposed as a practical application for A/D conversion at high rates because of its simplicity and robustness to imperfections in the circuit, also because the traditional converters are more difficult to implement in VLSI technology. These difficulties with conventional conversion methods need precise analog components in their filters and conversion circuits, and are more vulnerable to noise and interference. This paper aims to analyze the architecture, function and application of Analog-Digital converters (A/D) Sigma-Delta to overcome these difficulties, showing some simulations using the Simulink software and Multisim.

Keywords: Analysis, Oversampling Modulator, A/D converters, Sigma-Delta.

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