Search results for: CMOS active inductor

Authors: Padmanabhan Balasubramanian, R. Chinnadurai

Abstract:

This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).

Keywords: Achilles' heel functions, AND-EXOR-Inverter logic, CMOS technology, low power design.

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Authors: Houda Bdiri Gabbouj, Néjib Hassen, Kamel Besbes

Abstract:

This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.

Keywords: Amplifier class AB, current mirror, flipped voltage follower, low voltage.

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Authors: H. Abaali, M. T. Lamchich, M. Raoufi

Abstract:

There are a variety of reference current identification methods, for the shunt active power filter (SAPF), such as the instantaneous active and reactive power, the instantaneous active and reactive current and the synchronous detection method are evaluated and compared under ideal, non sinusoidal and unbalanced voltage conditions. The SAPF performances, for the investigated identification methods, are tested for a non linear load. The simulation results, using Matlab Power System Blockset Toolbox from a complete structure, are presented and discussed.

Keywords: Shunt active power filter, Current perturbation, Non sinusoidal and unbalanced voltage conditions.

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Authors: Dzmitry M. Kabanau, Vladimir V. Kabanov, Yahor V. Lebiadok, Denis V. Shabrov, Pavel V. Shpak, Gevork T. Mikaelyan, Alexandr P. Bunichev

Abstract:

This article is deal with the experimental investigations of the laser diode matrixes (LDM) based on the AlGaAs/GaAs heterostructures (lasing wavelength 790-880 nm) to find optimal LDM parameters for active vision systems. In particular, the dependence of LDM radiation pulse power on the pulse duration and LDA active layer heating as well as the LDM radiation divergence are discussed.

Keywords: Active vision systems, laser diode matrixes, thermal properties, radiation divergence.

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Authors: Lei Yao, Jia Hao Cheong, Rui-Feng Xue, Minkyu Je

Abstract:

A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.

Keywords: Implantable biomedical devices, wireless power transfer, LDO, rectifier, closed-loop power control

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Authors: Basman Elhadidi, Islam Elqatary, Osama Mohamady, Hesham Othman

Abstract:

An active slat is developed to increase the lift and delay the separation for a DU96-W180 airfoil. The active slat is a fixed slat that can be closed, fully opened or intermittently opened by a rotating vane depending on the need. Experimental results show that the active slat has reduced the mean pressure and increased the mean velocity on the suction side of the airfoil for all positive angles of attack, indicating an increase of lift. The experimental data and numerical simulations also show that the direction of actuator vane rotation can influence the mixing of the flow streams on the suction side and hence influence the aerodynamic performance.

Keywords: Active slat, flow control.

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Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: Jong-Whoi Shin, Soon-Tai Park, Chong-Sun Hwang

Abstract:

Active network was developed to solve the problem of the current sharing-based network–difficulty in applying new technology, service or standard, and duplicated operation at several protocol layers. Active network can transport the packet loaded with the executable codes, which enables to change the state of the network node. However, if the network node is placed in the sharing-based network, security and safety issues should be resolved. To satisfy this requirement, various security aspects are required such as authentication, authorization, confidentiality and integrity. Among these security components, the core factor is the encryption key. As a result, this study is designed to propose the scheme that manages the encryption key, which is used to provide security of the comprehensive active directory, based on the domain.

Keywords: Active Network, Domain-based Key Management, Security Components.

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Authors: Ming-Hui Lee, Shou-Jen Hsu

Abstract:

This study presents an active vibration control technique to reduce the earthquake responses of a retained structural system. The proposed technique is a synthesis of the adaptive input estimation method (AIEM) and linear quadratic Gaussian (LQG) controller. The AIEM can estimate an unknown system input online. The LQG controller offers optimal control forces to suppress wall-structural system vibration. The numerical results show robust performance in the active vibration control technique.

Keywords: Active vibration control, AIEM, LQG, Optimal control

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Authors: Tayebeh Saghapour, Sara Moridpour, Russell George Thompson

Abstract:

One of the common aims of transport policy makers is to switch people’s travel to active transport. For this purpose, a variety of transport goals and investments should be programmed to increase the propensity towards active transport mode choice. This paper aims to investigate whether built environment features in neighbourhoods could enhance the odds of active transportation. The present study introduces an index measuring public transport accessibility (PTAI), and a walkability index along with socioeconomic variables to investigate mode choice behaviour. Using travel behaviour data, an ordered logit regression model is applied to examine the impacts of explanatory variables on walking trips. The findings indicated that high rates of active travel are consistently associated with higher levels of walking and public transport accessibility.

Keywords: Active transport, public transport accessibility, walkability, ordered logit model.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in First-out pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correct data transmission through this FIFO is manually performed. Firstly an existing asynchronous FIFO design is discussed and simulated. Gate-level simulation results depicted the flaw in existing design. In order to solve this problem, a novel modified asynchronous FIFO design is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations. The proposed asynchronous FIFO design outperforms the existing design in terms of accuracy and speed. In order to evaluate the performance of the FIFO designs presented in this paper, the circuits were implemented in 0.24µ TSMC CMOS technology and simulated at 2.5V using HSpice (© Avant! Corporation). The layout design of the proposed FIFO is also presented.

Keywords: Asynchronous, Clock, CMOS, C-element, FIFO, Globally Asynchronous Locally Synchronous (GALS), HSpice.

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Authors: Marrick Neri, Esmeraldo Ronnie Rey Zara

Abstract:

In this paper, we apply a semismooth active set method to image inpainting. The method exploits primal and dual features of a proposed regularized total variation model, following after the technique presented in [4]. Numerical results show that the method is fast and efficient in inpainting sufficiently thin domains.

Keywords: Active set method, image inpainting, total variation model.

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Authors: Mihaela Popescu, Alexandru Bitoleanu, Mircea Dobriceanu, Vlad Suru

Abstract:

The aim of this paper is to identify an optimum control strategy of three-phase shunt active filters to minimize the total harmonic distortion factor of the supply current. A classical PIPI cascade control solution of the output current of the active filterand the voltage across the DC capacitor based on Modulus–Optimum criterion is taken into consideration. The control system operation has been simulated using Matlab-Simulink environment and the results agree with the theoretical expectation. It is shown that there is an optimum value of the DC-bus voltage which minimizes the supply current harmonic distortion factor. It corresponds to the equality of the apparent power at the output of the active filter and the apparent power across the capacitor. Finally, predicted results are verified experimentally on a MaxSine active power filter.

Keywords: Active filtering, Controller tuning, Modulus Optimum criterion, Optimum control.

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Wahab Ali Shah, Junjia He

Abstract:

Transferring electrical power without any wiring has been a dream since late 19^th century. There were some advances in this area as to know more about microwave systems. However, this subject has recently become very attractive due to their practiScal systems. There are low power applications such as charging the batteries of contactless tooth brushes or implanted devices, and higher power applications such as charging the batteries of electrical automobiles or buses. In the first group of applications operating frequencies are in microwave range while the frequency is lower in high power applications. In the latter, the concept is also called inductive power transfer. The aim of the paper is to have an overview of the inductive power transfer for electrical vehicles with a special concentration on coil design and power converter simulation for static charging. Coil design is very important for an efficient and safe power transfer. Coil design is one of the most critical tasks. Power converters are used in both side of the system. The converter on the primary side is used to generate a high frequency voltage to excite the primary coil. The purpose of the converter in the secondary is to rectify the voltage transferred from the primary to charge the battery. In this paper, an inductive power transfer system is studied. Inductive power transfer is a promising technology with several possible applications. Operation principles of these systems are explained, and components of the system are described. Finally, a single phase 2 kW system was simulated and results were presented. The work presented in this paper is just an introduction to the concept. A reformed compensation network based on traditional inductor-capacitor-inductor (LCL) topology is proposed to realize robust reaction to large coupling variation that is common in dynamic wireless charging application. In the future, this type compensation should be studied. Also, comparison of different compensation topologies should be done for the same power level.

Keywords: Coil design, contactless charging, electrical automobiles, inductive power transfer, operating frequency.

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Authors: M.Asif, M.R.Arshad, P.A.Wilson

Abstract:

In this paper, a simple active contour based visual tracking algorithm is presented for outdoor AGV application which is currently under development at the USM robotic research group (URRG) lab. The presented algorithm is computationally low cost and able to track road boundaries in an image sequence and can easily be implemented on available low cost hardware. The proposed algorithm used an active shape modeling using the B-spline deformable template and recursive curve fitting method to track the current orientation of the road.

Keywords: Active contour, B-spline, recursive curve fitting.

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Authors: P. Nammalvar, P. Meganathan, A. Balamuguran

Abstract:

Among various active filters, shunt active filter is a viable solution for reactive power and harmonics compensation. In this paper, the SRF plan is used to generate current reference for compensation and conventional PI controllers were used as the controller to compensate the reactive power. The design of the closed loop controllers is reserved simple by modeling them as first order systems. Computationally uncomplicated and efficient SVM system is used in the present work for better utilization of dc bus voltage. The rating of shunt active filter has been finalized based on the reactive power demand of the selected reactive load. The proposed control and SVM technique are validated by simulating in MATLAB software.

Keywords: Shunt Active Filter, Space vector pulse width modulation, Voltage Source Converter, Reactive Power, Synchronous Reference Frame, Point of common coupling.

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Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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Authors: N. Wang, Y. Pan, J. Zhou, J. Lei, X. Z. Yang

Abstract:

Experimental investigations were made on the instability of supercritical kerosene flowing in active cooling channels. Two approaches were used to control the pressure in the channel. One is the back-pressure valve while the other is the venturi. In both conditions, a kind of low-frequency oscillation of pressure and temperature is observed. And the oscillation periods are calculated. By comparison with the flow time, it is concluded that the instability occurred in active cooling channels is probably one kind of density wave instability. And its period has no relationship with the cooling channel geometry, nor the pressure, but only depends on the flow time of kerosene in active cooling channels. When the mass flow rate, density and pressure drop couple with each other, the density wave instability will appear.

Keywords: scramjets, active cooling, instability, density wave

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Authors: Haridas Kuruveettil, Dongning Zhao, Cheong Jia Hao, Minkyu Je

Abstract:

We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for  a three dimensional ultrasound  bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface   a 2-D array of    high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together.  Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm² and the full chip occupies a total silicon area of 10x6.8 mm².

Keywords: Ultrasound, analog front end, medical imaging, beam forming, biomicroscope, transimpedance gain.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: P. Santiprapan, K-L. Areerak, K-N. Areerak

Abstract:

This paper presents the mathematical model and control strategy on DQ frame of shunt active power filter. The structure of the shunt active power filter is the voltage source inverter (VSI). The pulse width modulation (PWM) with PI controller is used in the paper. The concept of DQ frame to apply with the shunt active power filter is described. Moreover, the detail of the PI controller design for two current loops and one voltage loop are fully explained. The DQ axis with Fourier (DQF) method is applied to calculate the reference currents on DQ frame. The simulation results show that the control strategy and the design method presented in the paper can provide the good performance of the shunt active power filter. Moreover, the %THD of the source currents after compensation can follow the IEEE Std.519-1992.

Keywords: shunt active power filter, mathematical model, DQ control strategy, DQ axis with Fourier, pulse width modulation control.

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Authors: Amir Abbas Emadzadeh, Mohammad Haeri

Abstract:

This paper presents anti-synchronization of chaos between two different chaotic systems using active control method. The proposed technique is applied to achieve chaos antisynchronization for the Lü and Rössler dynamical systems. Numerical simulations are implemented to verify the results.

Keywords: Active control, Anti-Synchronization, Chaos, Lü system, Rössler system.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

Abstract:

While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: Zoja Raud, Valery Vodovozov

Abstract:

Modelling and simulation provide effective way to acquire engineering experience. An active approach to modelling and simulation proposed in the paper involves, beside the compulsory part directed by the traditional step-by-step instructions, the new optional part basing on the human’s habits to design thus stimulating the efforts towards success in active learning. Computer exercises as a part of engineering curriculum incorporate a set of effective activities. In addition to the knowledge acquired in theoretical training, the described educational arrangement helps to develop problem solutions, computation skills, and experimentation performance along with enhancement of practical experience and qualification.

Keywords: Modelling, simulation, engineering education, electronics, active learning.

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Authors: Düzgün Akmaz, Hüseyin Erişti

Abstract:

In the last few years, harmonics have been occurred with the increasing use of nonlinear loads, and these harmonics have been an ever increasing problem for the line systems. This situation importantly affects the quality of power and gives large losses to the network. An efficient way to solve these problems is providing harmonic compensation through parallel active power filters. Many methods can be used in the control systems of the parallel active power filters which provide the compensation. These methods efficiently affect the performance of the active power filters. For this reason, the chosen control method is significant. In this study, Fourier analysis (FA) control method and synchronous reference frame (SRF) control method are discussed. These control methods are designed for both eliminate harmonics and perform reactive power compensation in MATLAB/Simulink pack program and are tested. The results have been compared for each two methods.

Keywords: Harmonics, Harmonic compensation, Parallel active power filters, Power quality.

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Authors: R. Chakib, A. Essadki, M. Cherkaoui

Abstract:

This paper proposes the study of a robust control of the doubly fed induction generator (DFIG) used in a wind energy production. The proposed control is based on the linear active disturbance rejection control (ADRC) and it is applied to the control currents rotor of the DFIG, the DC bus voltage and active and reactive power exchanged between the DFIG and the network. The system under study and the proposed control are simulated using MATLAB/SIMULINK.

Keywords: Doubly fed induction generator DFIG, Active disturbance rejection control ADRC, Vector control, MPPT, Extended state observer, back to back converter, Wind turbine.

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Authors: Şaban Çetin, Özgür Demir

Abstract:

In this study, Fuzzy PID Control scheme is designed for an active suspension system. The main goal of an active suspension system for using in a vehicle model is reducing body deflections and handling high comfort for a passenger car. The present system was modelled as a two-degree-of-freedom (2-DOF) nonlinear vehicle model.

Keywords: Active suspension system, Fuzzy PID controller, a nonlinear quarter car model.

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