Search results for: hardware acceleration

Authors: Tadashi Watanabe

Abstract:

The two-phase flow field and the motion of the free surface in an oscillating channel are simulated numerically to assess the methodology for simulating nuclear reacotr thermal hydraulics under seismic conditions. Two numerical methods are compared: one is to model the oscillating channel directly using the moving grid of the Arbitrary Lagrangian-Eulerian method, and the other is to simulate the effect of channel motion using the oscillating acceleration acting on the fluid in the stationary channel. The two-phase flow field in the oscillating channel is simulated using the level set method in both cases. The calculated results using the oscillating acceleration are found to coinside with those using the moving grid, and the theoretical back ground and the limitation of oscillating acceleration are discussed. It is shown that the change in the interfacial area between liquid and gas phases under seismic conditions is important for nuclear reactor thermal hydraulics.

Keywords: Two-phase flow, simulation, seismic condition, moving grid, oscillating acceleration, interfacial area

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Authors: F. Smach, M. Atri, J. Mitéran, M. Abid

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Face detection and recognition has many applications in a variety of fields such as security system, videoconferencing and identification. Face classification is currently implemented in software. A hardware implementation allows real-time processing, but has higher cost and time to-market. The objective of this work is to implement a classifier based on neural networks MLP (Multi-layer Perceptron) for face detection. The MLP is used to classify face and non-face patterns. The systm is described using C language on a P4 (2.4 Ghz) to extract weight values. Then a Hardware implementation is achieved using VHDL based Methodology. We target Xilinx FPGA as the implementation support.

Keywords: Classification, Face Detection, FPGA Hardware description, MLP.

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Authors: Shubha P Bhat, Krishnamurthy, T.C.Manjunath, C. Ardil

Abstract:

In this paper, the effects of the restoring force device on the response of a space frame structure resting on sliding type of bearing with a restoring force device is studied. The NS component of the El - Centro earthquake and harmonic ground acceleration is considered for earthquake excitation. The structure is modeled by considering six-degrees of freedom (three translations and three rotations) at each node. The sliding support is modeled as a fictitious spring with two horizontal degrees of freedom. The response quantities considered for the study are the top floor acceleration, base shear, bending moment and base displacement. It is concluded from the study that the displacement of the structure reduces by the use of the restoring force device. Also, the peak values of acceleration, bending moment and base shear also decreases. The simulation results show the effectiveness of the developed and proposed method.

Keywords: DOF, Space structures, Acceleration, Excitation, Smart structure, Vibration, Isolation, Earthquakes.

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Authors: Paris Kitsos

Abstract:

In this paper the FPGA implementations for four stream ciphers are presented. The two stream ciphers, MUGI and SNOW 2.0 are recently adopted by the International Organization for Standardization ISO/IEC 18033-4:2005 standard. The other two stream ciphers, MICKEY 128 and TRIVIUM have been submitted and are under consideration for the eSTREAM, the ECRYPT (European Network of Excellence for Cryptology) Stream Cipher project. All ciphers were coded using VHDL language. For the hardware implementation, an FPGA device was used. The proposed implementations achieve throughputs range from 166 Mbps for MICKEY 128 to 6080 Mbps for MUGI.

Keywords: Cryptography, ISO/IEC 18033-4:2005 standard, Hardware implementation, Stream ciphers

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Authors: Namchul Do, Gyeongseok Chae

Abstract:

This paper proposes a framework for product development including hardware and software components. It provides separation of hardware dependent software, modifications of current product development process, and integration of software modules with existing product configuration models and assembly product structures. In order to decide the dependent software, the framework considers product configuration modules and engineering changes of associated software and hardware components. In order to support efficient integration of the two different hardware and software development, a modified product development process is proposed. The process integrates the dependent software development into product development through the interchanges of specific product information. By using existing product data models in Product Data Management (PDM), the framework represents software as modules for product configurations and software parts for product structure. The framework is applied to development of a robot system in order to show its effectiveness.

Keywords: HW and SW Development Integration, ProductDevelopment with Software.

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Authors: A. Pedram, M. R. Jamali, T. Pedram, S. M. Fakhraie, C. Lucas

Abstract:

Local Linear Neuro-Fuzzy Models (LLNFM) like other neuro- fuzzy systems are adaptive networks and provide robust learning capabilities and are widely utilized in various applications such as pattern recognition, system identification, image processing and prediction. Local linear model tree (LOLIMOT) is a type of Takagi-Sugeno-Kang neuro fuzzy algorithm which has proven its efficiency compared with other neuro fuzzy networks in learning the nonlinear systems and pattern recognition. In this paper, a dedicated reconfigurable and parallel processing hardware for LOLIMOT algorithm and its applications are presented. This hardware realizes on-chip learning which gives it the capability to work as a standalone device in a system. The synthesis results on FPGA platforms show its potential to improve the speed at least 250 of times faster than software implemented algorithms.

Keywords: LOLIMOT, hardware, neurofuzzy systems, reconfigurable, parallel.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: S. A. Razavian Amrei, G.Ghodrati Amiri, D. Rezaei

Abstract:

This paper presents probabilistic horizontal seismic hazard assessment of Naghan, Iran. It displays the probabilistic estimate of Peak Ground Horizontal Acceleration (PGHA) for the return period of 475, 950 and 2475 years. The output of the probabilistic seismic hazard analysis is based on peak ground acceleration (PGA), which is the most common criterion in designing of buildings. A catalogue of seismic events that includes both historical and instrumental events was developed and covers the period from 840 to 2009. The seismic sources that affect the hazard in Naghan were identified within the radius of 200 km and the recurrence relationships of these sources were generated by Kijko and Sellevoll. Finally Peak Ground Horizontal Acceleration (PGHA) has been prepared to indicate the earthquake hazard of Naghan for different hazard levels by using SEISRISK III software.

Keywords: Seismic Hazard Assessment, Seismicity Parameters, PGA, Naghan, Iran

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Authors: H. E. Michail, V. N. Thanasoulis, G. A. Panagiotakopoulos, A. P. Kakarountas, C. E. Goutis

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In this paper an efficient implementation of Ripemd- 160 hash function is presented. Hash functions are a special family of cryptographic algorithms, which is used in technological applications with requirements for security, confidentiality and validity. Applications like PKI, IPSec, DSA, MAC-s incorporate hash functions and are used widely today. The Ripemd-160 is emanated from the necessity for existence of very strong algorithms in cryptanalysis. The proposed hardware implementation can be synthesized easily for a variety of FPGA and ASIC technologies. Simulation results, using commercial tools, verified the efficiency of the implementation in terms of performance and throughput. Special care has been taken so that the proposed implementation doesn-t introduce extra design complexity; while in parallel functionality was kept to the required levels.

Keywords: Hardware implementation, hash functions, Ripemd-160, security.

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Authors: Jae-Yeon Song, Seung-Yerl Lee, Kyu-Yeul Wang, Byung-Soo Kim, Sang-Seol Lee, Seong-Seob Shin, Jae-Young Choi, Chong Ho Lee, Jeahyun Park, Duck-Jin Chung

Abstract:

In this paper, we propose disease diagnosis hardware architecture by using Hypernetworks technique. It can be used to diagnose 3 different diseases (SPECT Heart, Leukemia, Prostate cancer). Generally, the disparate diseases require specified diagnosis hardware model for each disease. Using similarities of three diseases diagnosis processor, we design diagnosis processor that can diagnose three different diseases. Our proposed architecture that is combining three processors to one processor can reduce hardware size without decrease of the accuracy.

Keywords: Diagnosis processor, Hypernetworks, Leukemia, Mask, Prostate cancer, SPECT Heart data

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Authors: Youn-Sung Kim, Jin-Ho Jo, Mi-Sung Kim, Jae-Kun Lee

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Accelerated life cycle test is applied to various products or components in order to reduce the time of life cycle test in industry. It must be considered for many test conditions according to the product characteristics for the test and the selection of acceleration parameter is especially very important. We have carried out the general life cycle test and the accelerated life cycle test by applying the acceleration factor (AF) considering the characteristics of brushless DC (BLDC) motor for washing machine. The final purpose of this study is to verify the validity by analyzing the results of the general life cycle test and the accelerated life cycle test. It will make it possible to reduce the life test time through the reasonable accelerated life cycle test.

Keywords: Accelerated life cycle test, reliability test, motor for washing machine, brushless dc motor test.

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Authors: M. Z Md Zain, M. O. Tokhi, M. S. Alam

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This paper describes a practical approach to design and develop a hybrid learning with acceleration feedback control (HLC) scheme for input tracking and end-point vibration suppression of flexible manipulator systems. Initially, a collocated proportionalderivative (PD) control scheme using hub-angle and hub-velocity feedback is developed for control of rigid-body motion of the system. This is then extended to incorporate a further hybrid control scheme of the collocated PD control and iterative learning control with acceleration feedback using genetic algorithms (GAs) to optimize the learning parameters. Experimental results of the response of the manipulator with the control schemes are presented in the time and frequency domains. The performance of the HLC is assessed in terms of input tracking, level of vibration reduction at resonance modes and robustness with various payloads.

Keywords: Flexible manipulator, iterative learning control, vibration suppression.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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Authors: Rizwan Asghar, Dake Liu

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A hardware efficient, multi mode, re-configurable architecture of interleaver/de-interleaver for multiple standards, like DVB, WiMAX and WLAN is presented. The interleavers consume a large part of silicon area when implemented by using conventional methods as they use memories to store permutation patterns. In addition, different types of interleavers in different standards cannot share the hardware due to different construction methodologies. The novelty of the work presented in this paper is threefold: 1) Mapping of vital types of interleavers including convolutional interleaver onto a single architecture with flexibility to change interleaver size; 2) Hardware complexity for channel interleaving in WiMAX is reduced by using 2-D realization of the interleaver functions; and 3) Silicon cost overheads reduced by avoiding the use of small memories. The proposed architecture consumes 0.18mm2 silicon area for 0.12μm process and can operate at a frequency of 140 MHz. The reduced complexity helps in minimizing the memory utilization, and at the same time provides strong support to on-the-fly computation of permutation patterns.

Keywords: Hardware interleaver implementation, WiMAX, DVB, block interleaver, convolutional interleaver, hardwaremultiplexing.

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Authors: Ming-Hui Lee, Iau-Teh Wang

Abstract:

The innovative fuzzy estimator is used to estimate the ground motion acceleration of the retaining structure in this study. The Kalman filter without the input term and the fuzzy weighting recursive least square estimator are two main portions of this method. The innovation vector can be produced by the Kalman filter, and be applied to the fuzzy weighting recursive least square estimator to estimate the acceleration input over time. The excellent performance of this estimator is demonstrated by comparing it with the use of difference weighting function, the distinct levels of the measurement noise covariance and the initial process noise covariance. The availability and the precision of the proposed method proposed in this study can be verified by comparing the actual value and the one obtained by numerical simulation.

Keywords: Earthquake, Fuzzy Estimator, Kalman Filter, Recursive Least Square Estimator.

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Authors: M. Breška, I. Peruš, V. Stankovski

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The number of Ground Motion Prediction Equations (GMPEs) used for predicting peak ground acceleration (PGA) and the number of earthquake recordings that have been used for fitting these equations has increased in the past decades. The current PF-L database contains 3550 recordings. Since the GMPEs frequently model the peak ground acceleration the goal of the present study was to refit a selection of 44 of the existing equation models for PGA in light of the latest data. The algorithm Levenberg-Marquardt was used for fitting the coefficients of the equations and the results are evaluated both quantitatively by presenting the root mean squared error (RMSE) and qualitatively by drawing graphs of the five best fitted equations. The RMSE was found to be as low as 0.08 for the best equation models. The newly estimated coefficients vary from the values published in the original works.

Keywords: Ground Motion Prediction Equations, Levenberg-Marquardt algorithm, refitting PF-L database.

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Authors: V. H. Mankar, T. S. Das, S. K. Sarkar

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In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implementation because of its modularity, parallelism, high performance and reliability. The hardware realizable multiresolution spread spectrum watermarking techniques are very few in numbers in spite of their best ever resiliency against signal impairments. This is because of the computational cost and complexity associated with their different filter banks and lifting techniques. The concept of cellular automata theory in order to form a new transform domain technique i.e. Cellular Automata Transform (CAT) have been incorporated. Since CA provides spreading sequences having very low cross-correlation properties, the CA based pseudorandom sequence generator is considered in the present work. Considering the watermarking technique as a digital communication process, an error control coding (ECC) must be incorporated in the data hiding schemes. Besides the hardware implementation of entire CA based data hiding technique, the individual blocks of the algorithm using CA provide the best result than that of some other methods irrespective of the hardware and software technique. The Cellular Automata Transform, CA based PN sequence generator, and CA ECC are the requisite blocks that are developed not only to meet the reliable hardware requirements but also for the basic spread spectrum watermarking features. The proposed algorithm shows statistical invisibility and resiliency against various common signal-processing operations. This algorithmic design utilizes the existing allocated bandwidth in the data transmission channel in a more efficient manner.

Keywords: Cellular automata, watermarking, error control coding, PN sequence, VLSI.

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Authors: Petri Solanti, Russell Klein

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Many designers are asking for an automated path from an abstract mathematical MATLAB model to a high-quality Register-Transfer Level (RTL) hardware description. Manual transformations of MATLAB or intermediate code are needed, when the design abstraction is changed. Design conversion is problematic as it is multidimensional and it requires many different design steps to translate the mathematical representation of the desired functionality to an efficient hardware description with the same behavior and configurability. Yet, a manual model conversion is not an insurmountable task. Using currently available design tools and an appropriate design methodology, converting a MATLAB model to efficient hardware is a reasonable effort. This paper describes a simple and flexible design methodology that was developed together with several design teams.

Keywords: Design methodology, high-level synthesis, MATLAB, verification.

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Authors: Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan

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Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Keywords: Cross moments, Cumulants, FPGA, Hardware Implementation.

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Authors: H. Mat Kiah, Rafiziana M. Kasmani, Norazana Ibrahim, Roshafima R. Ali, Aziatul N.Sadikin

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An experimental study has been done to investigate the flame acceleration in a closed pipe. A horizontal steel pipe, 2m long and 0.1m in diameter (L/D of 20), was used in this work. For tests with 90 degree bends, the bend had a radius of 0.1m and thus, the pipe was lengthened 1m (based on the centreline length of the segment). Ignition was affected at one end of the vessel while the other end was closed. Only stoichiometric concentration (Ф, = 1.0) of natural gas/air mixtures will be reported in this paper. It was demonstrated that bend pipe configuration gave three times higher in maximum overpressure (5.5 bars) compared to straight pipe (2.0 bars). From the results, the highest flame speed, of 63ms^-1, was observed in a gas explosion with bent pipe; greater by a factor of ~3 as compared with straight pipe (23ms^-1). This occurs because bending acts similar to an obstacle, in which this mechanism can induce more turbulence, initiating combustion in an unburned pocket at the corner region and causing a high mass burning rate, which increases the flame speed.

Keywords: Bending, gas explosion, bending, flame acceleration, overpressure.

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Authors: Dawei Cai

Abstract:

In this paper, we present an autonomous guidance service by combinating the position information from NFC and the orientation information from 6 a 6 axis acceleration and terrestrial magnetism sensor. We developed an algorithm to calculate the device orientation  based on the data from acceleration and terrestrial magnetism sensor.With this function, a autonomous guidance service can be provided, according the visitors's position and orientation. This service may be convient for old people or disables or children.

Keywords: NFC, Ubiquitous Computing, Guide Sysem, MEMS.

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Authors: M. Qorbani

Abstract:

Neuromuscular control of posture as understood through studies of responses to mechanical sudden acceleration automatically has been previously demonstrated in individuals with chronic ankle instability (CAI), but the presence of acute condition has not been previously explored specially in a sudden acceleration. The aim of this study was to determine neuromuscular control pattern in those with and without unilateral acute ankle sprains. Design: Case - control. Setting: University research laboratory. The sinker–card protocol with surface translation was be used as a sudden acceleration protocol with study of EMG upon 4 posture stabilizer muscles in two sides of the body in response to sudden acceleration in forward and backward directions. 20 young adult women in two groups (10 LAS; 23.9 ± 2.03 yrs and 10 normal; 26.4 ± 3.2 yrs). The data of EMG were assessed by using multivariate test and one-way repeated measures 2×2×4 ANOVA (P< 0.05). The results showed a significant muscle by direction interaction. Higher TA activity of left and right side in LAS group than normal group in forward direction significantly be showed. Higher MGR activity in normal group than LAS group in backward direction significantly showed. These findings suggest that compared two sides of the body in two directions for 4 muscles EMG activities between and within group for neuromuscular control of posture in avoiding fall. EMG activations of two sides of the body in lateral ankle sprain (LAS) patients were symmetric significantly. Acute ankle instability following once ankle sprains caused to coordinated temporal spatial patterns and strategy selection.

Keywords: Neuromuscular response, sEMG, Lateral Ankle Sprain, posture.

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Authors: Nurzaki Ikhsan, Ahmad Saifizul Abdullah, Rahizar Ramli

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One of the functions of the commercial heavy vehicle is to safely and efficiently transport goods and people. Due to its size and carrying capacity, it is important to study the vehicle dynamic stability during cornering. Study has shown that there are a number of overloaded heavy vehicles or permissible Gross Vehicle Weight (GVW) violations recorded at selected areas in Malaysia assigned by its type and category. Thus, the objective of this study is to investigate the correlation and effect of the GVW on heavy vehicle stability during cornering event using simulation. Various selected heavy vehicle types and category are simulated using IPG/Truck Maker® with different GVW and road condition (coefficient of friction of road surface), while the speed, driver characteristic, center of gravity of load and road geometry are constant. Based on the analysis, the relationship between GVW and lateral acceleration were established. As expected, on the same value of coefficient of friction, the maximum lateral acceleration would be increased as the GVW increases.

Keywords: Heavy Vehicle, Road Safety, Vehicle Stability, Lateral Acceleration, Gross Vehicle Weight.

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Authors: Suguru Ochiai, Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama

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In this paper, we propose a Connect6 solver which adopts a hybrid approach based on a tree-search algorithm and image processing techniques. The solver must deal with the complicated computation and provide high performance in order to make real-time decisions. The proposed approach enables the solver to be implemented on a single Spartan-6 XC6SLX45 FPGA produced by XILINX without using any external devices. The compact implementation is achieved through image processing techniques to optimize a tree-search algorithm of the Connect6 game. The tree search is widely used in computer games and the optimal search brings the best move in every turn of a computer game. Thus, many tree-search algorithms such as Minimax algorithm and artificial intelligence approaches have been widely proposed in this field. However, there is one fundamental problem in this area; the computation time increases rapidly in response to the growth of the game tree. It means the larger the game tree is, the bigger the circuit size is because of their highly parallel computation characteristics. Here, this paper aims to reduce the size of a Connect6 game tree using image processing techniques and its position symmetric property. The proposed solver is composed of four computational modules: a two-dimensional checkmate strategy checker, a template matching module, a skilful-line predictor, and a next-move selector. These modules work well together in selecting next moves from some candidates and the total amount of their circuits is small. The details of the hardware design for an FPGA implementation are described and the performance of this design is also shown in this paper.

Keywords: Connect6, pattern matching, game-tree reduction, hardware direct computation

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Authors: Peng Shen Ong, Yoong Choon Chang, Chee Pun Ooi, Ettikan K. Karuppiah, Shahirina Mohd Tahir

Abstract:

Falling has been one of the major concerns and threats to the independence of the elderly in their daily lives. With the worldwide significant growth of the aging population, it is essential to have a promising solution of fall detection which is able to operate at high accuracy in real-time and supports large scale implementation using multiple cameras. Field Programmable Gate Array (FPGA) is a highly promising tool to be used as a hardware accelerator in many emerging embedded vision based system. Thus, it is the main objective of this paper to present an FPGA-based solution of visual based fall detection to meet stringent real-time requirements with high accuracy. The hardware architecture of visual based fall detection which utilizes the pixel locality to reduce memory accesses is proposed. By exploiting the parallel and pipeline architecture of FPGA, our hardware implementation of visual based fall detection using FGPA is able to achieve a performance of 60fps for a series of video analytical functions at VGA resolutions (640x480). The results of this work show that FPGA has great potentials and impacts in enabling large scale vision system in the future healthcare industry due to its flexibility and scalability.

Keywords: Fall detection, FPGA, hardware implementation.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

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The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: R. Damaševičius

Abstract:

System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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Authors: Kar Foo Chong, Andreas Lee Astuti, Pradeep K. Gopalakrishnan, T. Hui Teo

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This paper describes design of a digital feedback loop for a low switching frequency dc-dc switching converters. Low switching frequencies were selected in this design. A look up table for the digital PID (proportional integrator differentiator) compensator was implemented using Altera Stratix II with built-in ADC (analog-to-digital converter) to achieve this hardware realization. Design guidelines are given for the PID compensator, high frequency DPWM (digital pulse width modulator) and moving average filter.

Keywords: dc-dc converter, FPGA, PID, power management, .

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Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

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High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

Abstract:

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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