Search results for: smoothing circuit synchronization..

Authors: Andrés Gomez-Casseres, Rubén Contreras

Abstract:

In this paper, a bidirectional boost converter operated in Discontinuous Conduction Mode (DCM) is presented as a suitable power conditioning circuit for tuning of kinetic energy harvesters without the need of a battery. A nonlinear control scheme, composed by two linear controllers, is used to control the average value of the input current, enabling the synthesization of complex loads. The converter, along with the control system, is validated through SPICE simulations using the LTspice tool. The converter model and the controller transfer functions are derived. From the simulation results, it was found that the input current distortion increases with the introduced phase shift and that, such distortion, is almost entirely present at the zero-crossing point of the input voltage.

Keywords: Average current control, boost converter, electrical tuning, energy harvesting.

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Authors: Jin-Lung Guan, Jyh-Cherng Gu, Ming-Ta Yang, Hsin-Hung Chang, Chun-Wei Huang, Shao-Yu Huang

Abstract:

One of the most important power quality issues is voltage flicker. Nowadays this issue also impacts the power system all over the world. The fact of the matter is that the more and the larger capacity of wind generator has been installed. Under unstable wind power situation, the variation of output current and voltage have caused trouble to voltage flicker. Hence, the major purpose of this study is to analyze the impact of wind generator on voltage flicker of power system. First of all, digital simulation and analysis are carried out based on wind generator operating under various system short circuit capacity, impedance angle, loading, and power factor of load. The simulation results have been confirmed by field measurements.

Keywords: Wind Generator, Voltage Flicker

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Authors: Sungsik Jo, Hyeonwoo Kim, Iksu Choi, Hunmo Kim

Abstract:

In the SHP, LVDT sensor is for detecting the length changes of the EHA output, and the thrust of the EHA is controlled by the pressure sensor. Sensor is possible to cause hardware fault by internal problem or external disturbance. The EHA of SHP is able to be uncontrollable due to control by feedback from uncertain information, on this paper; the sliding mode observer algorithm estimates the original sensor output information in permanent sensor fault. The proposed algorithm shows performance to recovery fault of disconnection and short circuit basically, also the algorithm detect various of sensor fault mode.

Keywords: Smart Hybrid Powerpack (SHP), Electro Hydraulic Actuator (EHA), Permanent Sensor fault tolerance, Sliding mode observer (SMO), Graphic User Interface (GUI).

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Authors: Yerbol Sapargaliyev, Tatiana Kalganova

Abstract:

Evolvable Hardware (EHW) has been regarded as adaptive system acquired by wide application market. Consumer market of any good requires diversity to satisfy consumers- preferences. Adaptation of EHW is a key technology that could provide individual approach to every particular user. This situation raises a question: how to set target for evolutionary algorithm? The existing techniques do not allow consumer to influence evolutionary process. Only designer at the moment is capable to influence the evolution. The proposed consumer-triggered evolution overcomes this problem by introducing new features to EHW that help adaptive system to obtain targets during consumer stage. Classification of EHW is given according to responsiveness, imitation of human behavior and target circuit response. Home intelligent water heating system is considered as an example.

Keywords: Actuators, consumer-triggered evolution, evolvable hardware, sensors.

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Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

Abstract:

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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Authors: A. AlKalbany, H. Al hassan, M. Saeb

Abstract:

The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: FPGA, VHDL, micro-architecture, encryption, cryptography, algorithm, data communication security.

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Authors: S. Pattnaik, A. K. Panda, Aroul K., K. K. Mahapatra

Abstract:

This paper proposes a zero-voltage transition (ZVT) PWM synchronous buck converter, which is designed to operate at low output voltage and high efficiency typically required for portable systems. To make the DC-DC converter efficient at lower voltage, synchronous converter is an obvious choice because of lower conduction loss in the diode. The high-side MOSFET is dominated by the switching losses and it is eliminated by the soft switching technique. Additionally, the resonant auxiliary circuit designed is also devoid of the switching losses. The suggested procedure ensures an efficient converter. Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes.

Keywords: DC-DC Converter, Switching loss, Synchronous Buck, Soft switching, ZVT.

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Authors: O. Kratochvíl, J. Križan

Abstract:

The paper deals with the analysis of the dynamic response of footbridges under human - induced dynamic loads. This is a frequently occurring and often dominant load for footbridges as it stems from the very purpose of a footbridge - to convey pedestrian. Due to the emergence of new materials and advanced engineering technology, slender footbridges are increasingly becoming popular to satisfy the modern transportation needs and the aesthetical requirements of the society. These structures however are always lively with low stiffness, low mass, low damping and low natural frequencies. As a consequence, they are prone to vibration induced by human activities and can suffer severe vibration serviceability problems, particularly in the lateral direction. Pedestrian bridges are designed according to first and second limit states, these are the criteria involved in response to static design load. However, it is necessary to assess the dynamic response of bridge design load on pedestrians and assess it impact on the comfort of the user movement. Usually the load is considered a person or a small group which can be assumed in perfect motion synchronization. Already one person or small group can excite significant vibration of the deck. In order to calculate the dynamic response to the movement of people, designer needs available and suitable computational model and criteria. For the calculation program ANSYS based on finite element method was used.

Keywords: Footbridge, dynamic analysis, vibration serviceability of footbridges, lateral vibration, stiffness, dynamic force, walking force, slender suspension footbridges, natural frequencies and vibration modes, rhythm jumping, normal walking.

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Authors: İsmail Aksoy, Hacı Bodur, Nihan Altıntas

Abstract:

This paper introduces a boost converter with a new active snubber cell. In this circuit, all of the semiconductor components in the converter softly turns on and turns off with the help of the active snubber cell. Compared to the other converters, the proposed converter has advantages of size, number of components and cost. The main feature of proposed converter is that the extra voltage stresses do not occur on the main switches and main diodes. Also, the current stress on the main switch is acceptable level. Moreover, the proposed converter can operates under light load conditions and wide input line voltage. In this study, the operating principle of the proposed converter is presented and its operation is verified with the Proteus simulation software for a 1 kW and 100 kHz model.

Keywords: Active snubber cell, boost converter, zero current switching, zero voltage switching.

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Authors: Buket Turan Azizoğlu

Abstract:

In switch mode power inverters, small sized inverters can be obtained by increasing the switching frequency. Switching frequency increment causes high driver losses. Also, high dt di and dt dv produced by the switching action creates high Electromagnetic Interference (EMI) and Radio Frequency Interference (RFI). In this paper, a series half bridge series resonant inverter circuit is simulated and evaluated practically to demonstrate the turn-on and turn-off conditions during zero or close to zero voltage switching. Also, the reverse recovery current effects of the body diode of the MOSFETs were investigated by operating above and below resonant frequency.

Keywords: Driver losses, Half Bridge series resonant inverter, Zero Voltage Switching

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Authors: Jae-Chang Kwak, Yong-Seo Koo

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The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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Authors: M. S. Sreejith, Steffy Joy, Abhishesh Pal, Beom-Sahng Ryuh, V. R. Sanal Kumar

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In this paper, an attempt has been made for the design of a robotic library using an intelligent system. The robot works on the ARM microprocessor, motor driver circuit with 5 degrees of freedom with Wi-Fi and GPS based communication protocol. The authenticity of the library books is controlled by RFID. The proposed robotic library system is facilitated with embedded system and ARM. In this library issuance system, the previous potential readers’ authentic review reports have been taken into consideration for recommending suitable books to the deserving new users and the issuance of books or periodicals is based on the users’ decision. We have conjectured that the Wi-Fi based robotic library management system would allow fast transaction of books issuance and it also produces quality readers.

Keywords: GPS based based robotic library, library management system, robotic library, Wi-Fi library.

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Authors: Pujarini Ghosh A, Rishu Chaujar B, Subhasis Haldar C, R.S Gupta D, Mridula Gupta E

Abstract:

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material work function difference on drain current noise spectral density of the device reflecting its applicability for circuit design applications.

Keywords: Cylindrical/Surrounded gate (SGT/CGT) MOSFET, Gate Material Engineering (GME), Spectral Noise and short channeleffect (SCE).

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Authors: A.O. Ladjedel, B.T.Yahiaoui, C.L.Adjlout, D.O.Imine

Abstract:

In the present paper; an experimental and numerical investigations of drag reduction on a grooved circular cylinder have been performed. The experiments were carried out in closed circuit subsonic wind tunnel (TE44); the pressure distribution on the cylinder was conducted using a TE44DPS differential pressure scanner and the drag forces were measured using the TE81 balance. The display unit is linked to a computer, loaded with DATASLIM software for data analysis and logging of result. The numerical study was performed using the code ANSYS FLUENT solving the Reynolds Averaged Navier-Stokes (RANS) equations. The k-ε and k- ω SST models were tested. The results obtained from the experimental and numerical investigations have showed a reduction in the drag when using longitudinal grooves namely 2 and 6 on the cylinder.

Keywords: Circular cylinder, Drag, grooves, pressure distribution

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Authors: Ian A. Grout

Abstract:

In this paper, the design and development of a system to provide hand motion and gesture control of laboratory test equipment is considered and discussed. The Leap Motion controller is used to provide an input to control a laboratory power supply as part of an electronic circuit experiment. By suitable hand motions and gestures, control of the power supply is provided remotely and without the need to physically touch the equipment used. As such, it provides an alternative manner in which to control electronic equipment via a PC and is considered here within the field of human computer interaction (HCI).

Keywords: Control, hand gesture, human computer interaction, test equipment.

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

Abstract:

Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: H. Sediki, S. Djennoune

Abstract:

The switching lag-time and the voltage drop across the power devices cause serious waveform distortions and fundamental voltage drop in pulse width-modulated inverter output. These phenomenons are conspicuous when both the output frequency and voltage are low. To estimate the output voltage from the PWM reference signal it is essential to take account of these imperfections and to correct them. In this paper, on-line compensation method is presented. It needs three simple blocs to add at the ideal reference voltages. This method does not require any additional hardware circuit and off- line experimental measurement. The paper includes experimental results to demonstrate the validity of the proposed method. It is applied, finally, in case of indirect vector controlled induction machine and implemented using dSpace card.

Keywords: Dead time, field-oriented control, Induction motor, PWM inverter, voltage drop.

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Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: CMOS transistor, direct-tunneling current, floatinggate, gate-leakage current, simulation model.

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Authors: A. Hossain, M. A. Gafur, F. Gulshan, A. S. W. Kurny

Abstract:

Al-Si-Mg-Ni(-Cu) alloys are widely used in the automotive industry. They have the advantage of low weight associated with low coefficient of thermal expansion and excellent mechanical properties – mainly at high temperatures. The corrosion resistance of these alloys in coastal area, particularly sea water, however is not yet known. In this investigation, electrochemical impedance spectroscopy (EIS) and potentiodynamic polarization have been used to evaluate the corrosion resistance of Al-6Si-0.5Mg-2Ni (-2Cu) alloys in simulated sea water environments. The potentiodynamic polarization curves reveal that 2 wt% Cu content alloy (Alloy-2) is more prone to corrosion than the Cu free alloy (Alloy-1). But the EIS test results showed that corrosion resistance or charge transfer resistance (Rct) increases with the addition of Cu. Due to addition of Cu and thermal treatment, the magnitude of open circuit potential (OCP), corrosion potential (Ecorr) and pitting corrosion potential (Epit) of Al-6Si-0.5Mg-2Ni alloy in NaCl solution were shifted to the more noble direction.

Keywords: Al-Si alloy, potentiodynamic polarization, EIS, SEM.

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Authors: J. B. V. Subrahmanyam, C. Radhakrishna

Abstract:

This paper presents a simple three phase power flow method for solution of three-phase unbalanced radial distribution system (RDN) with voltage dependent loads. It solves a simple algebraic recursive expression of voltage magnitude, and all the data are stored in vector form. The algorithm uses basic principles of circuit theory and can be easily understood. Mutual coupling between the phases has been included in the mathematical model. The proposed algorithm has been tested with several unbalanced radial distribution networks and the results are presented in the article. 8- bus and IEEE 13 bus unbalanced radial distribution system results are in agreements with the literature and show that the proposed model is valid and reliable.

Keywords: radial distribution networks, load flow, circuitmodel, three-phase four-wire, unbalance.

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Authors: Fatma Belghith, Hassen Loukil, Nouri Masmoudi

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This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Keywords: HEVC, Modified Integer Transform, FPGA.

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Authors: A. Alghanim, J. Benedikt, P. J. Tasker

Abstract:

The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behavior of the intermodulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. These investigations are performed on a 12W LDMOS device characterised at 2.1 GHz within a purpose built, high-power measurement system.

Keywords: Low Frequency Memory, IntermodulationDistortion (IMD).

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Authors: Khaled M. El Naggar

Abstract:

This paper introduces a digital method for fault section identification in transmission lines. The method uses digital set of the measured short circuit current to locate faults in electrical power systems. The digitized current is used to construct a set of overdetermined system of equations. The problem is then constructed and solved using the proposed digital optimization technique to find the fault distance. The proposed optimization methodology is an application of simulated annealing optimization technique. The method is tested using practical case study to evaluate the proposed method. The accurate results obtained show that the algorithm can be used as a powerful tool in the area of power system protection.

Keywords: Optimization, estimation, faults, measurement, high voltage, simulated annealing.

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Authors: Jingling Li, Yi Zhang, Wei Liang, Tao Cui, Jun Li

Abstract:

Compared with terrestrial network, the traffic of spatial information network has both self-similarity and short correlation characteristics. By studying its traffic prediction method, the resource utilization of spatial information network can be improved, and the method can provide an important basis for traffic planning of a spatial information network. In this paper, considering the accuracy and complexity of the algorithm, the spatial information network traffic is decomposed into approximate component with long correlation and detail component with short correlation, and a time series hybrid prediction model based on wavelet decomposition is proposed to predict the spatial network traffic. Firstly, the original traffic data are decomposed to approximate components and detail components by using wavelet decomposition algorithm. According to the autocorrelation and partial correlation smearing and truncation characteristics of each component, the corresponding model (AR/MA/ARMA) of each detail component can be directly established, while the type of approximate component modeling can be established by ARIMA model after smoothing. Finally, the prediction results of the multiple models are fitted to obtain the prediction results of the original data. The method not only considers the self-similarity of a spatial information network, but also takes into account the short correlation caused by network burst information, which is verified by using the measured data of a certain back bone network released by the MAWI working group in 2018. Compared with the typical time series model, the predicted data of hybrid model is closer to the real traffic data and has a smaller relative root means square error, which is more suitable for a spatial information network.

Keywords: Spatial Information Network, Traffic prediction, Wavelet decomposition, Time series model.

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Authors: Santirat Nansaarng, Sittichai Kaewkuekool, Supreeya Siripattanakunkajorn

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This research was to study a comparison of inspector-s performance between regular and complex visual inspection task. Visual task was simulated on DVD read control circuit. Inspection task was performed by using computer. Subjects were 10 undergraduate randomly selected and test for 20/20. Then, subjects were divided into two groups, five for regular inspection (control group) and five for complex inspection (treatment group) tasks. Result was showed that performance on regular and complex inspectors was significantly difference at the level of 0.05. Inspector performance on regular inspection was showed high percentage on defects detected by using equal time to complex inspection. This would be indicated that inspector performance was affected by visual inspection task.

Keywords: Visual inspection task, regular and complex task.

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Authors: Jingjing Lan, Jun Zhou, Xin Liu

Abstract:

In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach. 

Keywords: Buck converter, DC-DC power conversion, digital control, proportional-integral (PI) controller.

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Authors: Kanhu Charan Bhuyan, Subhransu Padhee, Rajesh Kumar Patjoshi, Kamalakanta Mahapatra

Abstract:

Fuel cell is an emerging technology in the field of renewable energy sources which has the capacity to replace conventional energy generation sources. Fuel cell utilizes hydrogen energy to produce electricity. The electricity generated by the fuel cell can’t be directly used for a specific application as it needs proper power conditioning. Moreover, the output power fluctuates with different operating conditions. To get a stable output power at an economic rate, power conditioning circuit is essential for fuel cell. This paper implements a two-staged power conditioning unit for fuel cell based distributed generation using hysteresis current control technique.

Keywords: Fuel cell, power conditioning unit, hysteresis control.

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Authors: A. Chinig, J. Zbitou, A. Errkik, L. Elabdellaoui, A. Tajmouati, A. Tribak, M. Latrach

Abstract:

This paper presents a new structure of microstrip band pass filter (BPF) based on coupled stepped impedance resonators. Each filter consists of two coupled stepped impedance resonators connected to microstrip feed lines. The coupled junction is utilized to connect the two BPFs to the antenna. This two band pass filters are designed and simulated to operate for the digital communication system (DCS) and Industrial Scientific and Medical (ISM) bands at 1.8 GHz and 2.45 GHz respectively. The proposed circuit presents good performances with an insertion loss lower than 2.3 dB and isolation between the two channels greater than 21 dB. The prototype of the optimized diplexer have been investigated numerically by using ADS Agilent and verified with CST microwave software.

Keywords: Band Pass Filter, coupled junction, coupled stepped impedance resonators, diplexer, insertion loss, isolation.

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Authors: Ashutosh Kumar Singh, Anand Mohan

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This paper deals with efficient computation of probability coefficients which offers computational simplicity as compared to spectral coefficients. It eliminates the need of inner product evaluations in determination of signature of a combinational circuit realizing given Boolean function. The method for computation of probability coefficients using transform matrix, fast transform method and using BDD is given. Theoretical relations for achievable computational advantage in terms of required additions in computing all 2n probability coefficients of n variable function have been developed. It is shown that for n ≥ 5, only 50% additions are needed to compute all probability coefficients as compared to spectral coefficients. The fault detection techniques based on spectral signature can be used with probability signature also to offer computational advantage.

Keywords: Binary Decision Diagrams, Spectral Coefficients, Fault detection

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Authors: Alexander N. Savostyanov, Tatiana A. Dolgorukova, Elena A. Esipenko, Mikhail S. Zaleshin, Margherita Malanchini, Anna V. Budakova, Alexander E. Saprygin, Tatiana A. Golovko, Yulia V. Kovas

Abstract:

EEG correlates of mathematical and trait anxiety level were studied in 52 healthy Russian-speakers during execution of error-recognition tasks with lexical, arithmetic and algebraic conditions. Event-related spectral perturbations were used as a measure of brain activity. The ERSP plots revealed alpha/beta desynchronizations within a 500-3000 ms interval after task onset and slow-wave synchronization within an interval of 150-350 ms. Amplitudes of these intervals reflected the accuracy of error recognition, and were differently associated with the three conditions. The correlates of anxiety were found in theta (4-8 Hz) and beta2 (16- 20 Hz) frequency bands. In theta band the effects of mathematical anxiety were stronger expressed in lexical, than in arithmetic and algebraic condition. The mathematical anxiety effects in theta band were associated with differences between anterior and posterior cortical areas, whereas the effects of trait anxiety were associated with inter-hemispherical differences. In beta1 and beta2 bands effects of trait and mathematical anxiety were directed oppositely. The trait anxiety was associated with increase of amplitude of desynchronization, whereas the mathematical anxiety was associated with decrease of this amplitude. The effect of mathematical anxiety in beta2 band was insignificant for lexical condition but was the strongest in algebraic condition. EEG correlates of anxiety in theta band could be interpreted as indexes of task emotionality, whereas the reaction in beta2 band is related to tension of intellectual resources.

Keywords: EEG, brain activity, lexical and numerical error-recognition tasks, mathematical and trait anxiety.

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