Search results for: ripple carry adder

Authors: Mahendrapal Singh Pachlaniya, Laxmi Kumre

Abstract:

The AOI (AND – OR- INVERTER) based design of XOR gate is proposed in this paper with less number of gates. This new XOR gate required four basic gates and basic gate include only AND, OR, Inverter (AOI). Conventional XOR gate required five basic gates. Ripple Carry Adder (RCA) used in parallel addition but propagation delay time is large. RCA replaced with Carry Select Adder (CSLA) to reduce propagation delay time. CSLA design with dual RCA considering carry = ‘0’ and carry = ‘1’, so it is not an area efficient adder. To make area efficient, modified CSLA is designed with single RCA considering carry = ‘0’ and another RCA considering carry = ‘1’ replaced with Binary to Excess 1 Converter (BEC). Now replacement of conventional XOR gate by new design of XOR gate in modified CSLA reduces much area compared to regular CSLA and modified CSLA.

Keywords: CSLA, BEC, XOR gate, area efficient

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Authors: T. Angeline Priyanka, R. Ganesan

Abstract:

Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

Abstract:

At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

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Authors: Kala Bharathan, R. Seshasayanan

Abstract:

In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

Abstract:

In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

Abstract:

In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Tayab D. Memon, Shahji Farooque, Marvi Deshi, Imtiaz Hussain Kalwar, B. S. Chowdhry

Abstract:

Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this paper, an optimized adder module for ternary quantized sigma-delta modulated signal is presented. The adder is simulated using ModelSim for functional verification the area-performance of the proposed adder were obtained through synthesis in Xilinx and compared to conventional adder trees. The synthesis results show that the proposed adder tree achieves higher clock rates and lower chip area at higher inputs to the adder block; whereas conventional adder tree achieves better performance and lower chip area at lower number of inputs to the same adder block. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Keywords: short word length (SWL), DSP algorithms, FPGA, SBTFF, VHDL

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Authors: Ch. Ashok Babu, J. V. R. Ravindra, K. Lalkishore

Abstract:

Power has became a burning issue in modern VLSI design. As the technology advances especially below 45nm, technology of leakage power became a big problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder, DTMOS full adder. This paper shows different types of adders and their power consumption, area, and delay. All the experiments have been carried out using Cadence® Virtuoso® design lay out editor which shows power consumption of different types of adders.

Keywords: average power, leakage power, delay, DTMOS, PDP

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Authors: S. Padmapriya, V. Lakshmi Prabha

Abstract:

In this paper, an efficient reconfigurable fixed-point Least Mean Square Adaptive FIR filter is proposed. The proposed architecture has two methods of operation: one is area efficient design and the other is optimized power. Pipelining of the adder blocks and partial product generator are used to achieve low area and reversible logic is used to obtain low power design. Depending upon the input samples and filter coefficients, one of the techniques is chosen. Least-Mean-Square adaptation is performed to update the weights. The architecture is coded using Verilog and synthesized in cadence encounter 0.18μm technology. The synthesized results show that the area reduction ratio of the proposed when compared with conventional technique is about 1.2%.

Keywords: adaptive filter, carry select adder, least mean square algorithm, reversible logic

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Authors: Yasunori Kobori, Li Quan, Shu Wu, Nizam Mohyar, Zachary Nosker, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi

Abstract:

This paper proposes an electrolytic capacitor-less transformer-less AC-DC LED driver with a current ripple canceller. The proposed LED driver includes a diode bridge, a buck-boost converter, a negative feedback controller and a current ripple cancellation circuit. The current ripple canceller works as a bi-directional current converter using a sub-inductor, a sub-capacitor and two switches for controlling current flow. LED voltage is controlled in order to regulate LED current by the negative feedback controller using a current sense resistor. There are two capacitors which capacitance of 5 uF. We describe circuit topologies, operation principles and simulation results for our proposed circuit. In addition, we show the line regulation for input voltage variation from 85V to 130V. The output voltage ripple is 2V and the LED current ripple is 65 mA which is less than 20% of the typical current of 350 mA. We are now making the proposed circuit on a universal board in order to measure the experimental characteristics.

Keywords: LED driver, electrolytic, capacitor-less, AC-DC converter, buck-boost converter, current ripple canceller

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Authors: Hadi Aghazadeh, Mohammadreza Naeimi, Seyed Ebrahim Afjei, Alireza Siadatan

Abstract:

Torque ripple, maximum torque and high efficiency are important issues in synchronous reluctance machine (SynRM). This paper presents a view on design of a high efficiency, low torque ripple and high torque density SynRM. To achieve this goal SynRM parameters is calculated (such as insulation ratios in the d-and q-axes and the rotor slot pitch), while the torque ripple can be minimized by determining the best rotor slot pitch in the d-axis. The presented analytical-finite element method (FEM) approach gives the optimum distribution of air gap and iron portion for the maximizing torque density with minimum torque ripple.

Keywords: torque ripple, efficiency, insulation ratio, FEM, synchronous reluctance machine (SynRM), induction motor (IM)

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: T. Mohammed Chikouche, K. Hartani

Abstract:

In order to solve the instantaneous power ripple and achieve better performance of direct power control (DPC) for a three-phase PWM rectifier, a control method is proposed in this paper. This control method is applied to overcome the instantaneous power ripple, to eliminate line current harmonics and therefore reduce the total harmonic distortion and to improve the power factor. A switching table is based on the analysis on the change of instantaneous active and reactive power, to select the optimum switching state of the three-phase PWM rectifier. The simulation result shows feasibility of this control method.

Keywords: power quality, direct power control, power ripple, switching table, unity power factor

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Authors: Yasunori Kobori, Murong Li, Feng Zhao, Shu Wu, Nobukazu Takai, Haruo Kobayashi

Abstract:

This paper proposes an electrolytic capacitor-less transformer-less AC-DC LED driver with a current ripple canceller. The proposed LED driver includes a diode bridge, a buck-boost converter, a negative feedback controller and a current ripple cancellation circuit. The current ripple canceller works as a bi-directional current converter using a sub-inductor, a sub-capacitor and two switches for controlling current flow. LED voltage is controlled in order to regulate LED current by the negative feedback controller using a current sense resistor. There are two capacitors with capacitance of 5 uF. We describe circuit topologies, operation principles and simulation results for our proposed circuit. In addition, we show the line regulation for input voltage variation from 85V to 130V. The output voltage ripple is 2V and the LED current ripple is 65 mA which is less than 20% of the average of LED current of 350 mA.

Keywords: DC-DC buck converter, four-level output voltage, single inductor multi output (SIMO), switching converter

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Authors: S. Jalaja, A. M. Vijaya Prakash

Abstract:

Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.

Keywords: carry save adder Karatsuba multiplication, mid range Karatsuba multiplication, modified FFA and transposed filter, retiming

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Authors: Mengjie Shen, Jianhua Wu, Chun Gan, Lifeng Zhang, Qingguo Sun

Abstract:

Switching flux permanent magnet (SFPM) motor has doubly salient structure which lead to high torque ripple, and also has cogging torque as a permanent magnet motor. Torque ripple and cogging torque have impact on the motor performance. A novel stator structure SFPM motor is presented in this paper. A triangular shape silicon steel sheet is put in the stator slot to reduce the torque ripple, which will not deteriorate the cogging torque. The simulation of proposed motor is analyzed using 2-D finite element method (FEM) based on Ansoft and Simplorer software, and the result show a good performance of the proposed SFPM motor.

Keywords: switching flux permanent magnet (SFPM) motor, torque ripple, Ansoft, FEM

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Authors: T. Abdelkrim, K. Benamrane, B. Bezza, Aeh Benkhelifa, A. Borni

Abstract:

This paper proposes a regulation method of back-to-back connected three-level converters in order to reduce the torque ripple in induction motor. First part is dedicated to the presentation of the feedback control of three-level PWM rectifier. In the second part, three-level NPC voltage source inverter balancing DC bus algorithm is presented. A theoretical analysis with a complete simulation of the system is presented to prove the excellent performance of the proposed technique.

Keywords: back-to-back connection, feedback control, neutral-point balance, three-level converter, torque ripple

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Authors: T. Vamsee Kiran, A. Gopi

Abstract:

The undesired torque and flux ripple may occur in conventional direct torque control (DTC) induction motor drive. DTC can improve the system performance at low speeds by continuously tuning the regulator by adjusting the Kp, Ki values. In this differential evolution (DE) is proposed to adjust the parameters (Kp, Ki) of the speed controller in order to minimize torque ripple, flux ripple, and stator current distortion.The DE based PI controller has resulted is maintaining a constant speed of the motor irrespective of the load torque fluctuations.

Keywords: differential evolution, direct torque control, PI controller

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: P. Srinivas, P. V. N. Prasad

Abstract:

Since torque ripple is the main cause of noise and vibrations, the performance of Switched Reluctance Motor (SRM) can be improved by minimizing its torque ripple using a novel control technique called Direct Torque Control (DTC). In DTC technique, torque is controlled directly through control of magnitude of the flux and change in speed of the stator flux vector. The flux and torque are maintained within set hysteresis bands. The DTC of SRM is analysed by two methods. In one of the methods, the actual torque is computed by conducting Finite Element Analysis (FEA) on the design specifications of the motor. In the other method, the torque is computed by Simplified Torque Equation. The variation of peak current, average current, torque ripple and speed settling time with Simplified Torque Equation model is compared with FEA based model.

Keywords: direct toque control, simplified torque equation, finite element analysis, torque ripple

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Authors: Mayank Mundhra, Chester Rebeiro

Abstract:

Cryptocurrencies are rapidly finding wide application in areas such as Real Time Gross Settlements and Payments Systems. Ripple is a cryptocurrency that has gained prominence with banks and payment providers. It solves the Byzantine General’s Problem with its Ripple Protocol Consensus Algorithm (RPCA), where each server maintains a list of servers, called Unique Node List (UNL) that represents the network for the server, and will not collectively defraud it. The server believes that the network has come to a consensus when members of the UNL come to a consensus on a transaction. In this paper we improve Ripple to achieve better speed, security, last mile connectivity and ease of use. We implement guidelines and automated systems for building and maintaining UNLs for resilience, robustness, improved security, and efficient information propagation. We enhance the system so as to ensure that each server receives information from across the whole network rather than just from the UNL members. We also introduce the paradigm of UNL overlap as a function of information propagation and the trust a server assigns to its own UNL. Our design not only reduces vulnerabilities such as eclipse attacks, but also makes it easier to identify malicious behaviour and entities attempting to fraudulently Double Spend or stall the system. We provide experimental evidence of the benefits of our approach over the current Ripple scheme. We observe ≥ 4.97x and 98.22x in speedup and success rate for information propagation respectively, and ≥ 3.16x and 51.70x in speedup and success rate in consensus.

Keywords: Ripple, Kelips, unique node list, consensus, information propagation

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Authors: Anam Gopi

Abstract:

The undesired torque and flux ripple may occur in conventional direct torque control (DTC) induction motor drive. DTC can improve the system performance at low speeds by continuously tuning the regulator by adjusting the Kp, Ki values. In this Teaching Learning Based Optimization (TLBO) is proposed to adjust the parameters (Kp, Ki) of the speed controller in order to minimize torque ripple, flux ripple, and stator current distortion. The TLBO based PI controller has resulted is maintaining a constant speed of the motor irrespective of the load torque fluctuations.

Keywords: teaching learning based optimization, direct torque control, PI controller

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Authors: Yong Min You

Abstract:

The study on the torque ripple of Permanent Magnet Synchronous Motors (PMSMs) has been rapidly progressed, which effects on the noise and vibration of the electric vehicle. There are several ways to reduce torque ripple, which are the increase in the number of slots and poles, the notch of the rotor and stator teeth, and the skew of the rotor and stator. However, the conventional methods have the disadvantage in terms of material cost and productivity. The demagnetization characteristic of PMSMs must be attained for electric vehicle application. Due to rare earth supply issue, the demand for Dy-free permanent magnet has been increasing, which can be applied to PMSMs for the electric vehicle. Dy-free permanent magnet has lower the coercivity; the demagnetization characteristic has become more significant. To improve the torque ripple as well as the demagnetization characteristics, which are significant parameters for electric vehicle application, an unequal air-gap model is proposed for a PMSM. A shape optimization is performed to optimize the design variables of an unequal air-gap model. Optimal design variables are the shape of an unequal air-gap and the angle between V-shape magnets. An optimization process is performed by Latin Hypercube Sampling (LHS), Kriging Method, and Genetic Algorithm (GA). Finite element analysis (FEA) is also utilized to analyze the torque and demagnetization characteristics. The torque ripple and the demagnetization temperature of the initial model of 45kW PMSM with unequal air-gap are 10 % and 146.8 degrees, respectively, which are reaching a critical level for electric vehicle application. Therefore, the unequal air-gap model is proposed, and then an optimization process is conducted. Compared to the initial model, the torque ripple of the optimized unequal air-gap model was reduced by 7.7 %. In addition, the demagnetization temperature of the optimized model was also increased by 1.8 % while maintaining the efficiency. From these results, a shape optimized unequal air-gap PMSM has shown the usefulness of an improvement in the torque ripple and demagnetization temperature for the electric vehicle.

Keywords: permanent magnet synchronous motor, optimal design, finite element method, torque ripple

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Authors: Hwayeon Song

Abstract:

The long-term purpose of research and development (R&D) programs is to strengthen national competitiveness by developing new knowledge and technologies. Thus, it is important to determine a proper budget for government programs to maintain the vigor of R&D when the total funding is tight due to the national deficit. In this regard, a ripple effect analysis for the budgetary changes in R&D programs is necessary as well as an investigation of the current status. This study proposes a new approach using Artificial Neural Networks (ANN) for both tasks. It particularly focuses on R&D programs related to Construction and Transportation (C&T) technology in Korea. First, key factors in C&T technology are explored to draw impact indicators in three areas: economy, society, and science and technology (S&T). Simultaneously, ANN is employed to evaluate the relationship between data variables. From this process, four major components in R&D including research personnel, expenses, management, and equipment are assessed. Then the ripple effect analysis is performed to see the changes in the hypothetical future by modifying current data. Any research findings can offer an alternative strategy about R&D programs as well as a new analysis tool.

Keywords: Artificial Neural Networks, construction and transportation technology, Government Research and Development, Ripple Effect

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Authors: Ahmad Zahran, Ahmed Herzallah, Ahmad Ahmad, Mahran Quraan

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Generation of high DC voltages is necessary for testing the insulation material of high voltage AC transmission lines with long lengths. The harmonic and ripple contents of the output DC voltage supplied by high voltage DC circuits require the use of costly capacitors to smooth the output voltage after rectification. This paper proposes a new modular multiplier high voltage DC generator with embedded Cockcroft-Walton circuits that achieve a negligible harmonic and ripple contents of the output DC voltage without the need for costly filters to produce a nearly constant output voltage. In this new topology, Cockcroft-Walton modules are connected in series to produce a high DC output voltage. The modules are supplied by low input AC voltage sources that have the same magnitude and frequency and shifted from each other by a certain angle to eliminate the harmonics from the output voltage. The small ripple factor is provided by the smoothing column capacitors and the phase shifted input voltages of the cascaded modules. The constituent harmonics within each module are determined using Fourier analysis. The viability of the proposed DC generator for testing purposes and the effectiveness of the cascaded connection are confirmed by numerical simulations using MATLAB/Simulink.

Keywords: Cockcroft-Walton circuit, harmonics, ripple factor, HVDC generator

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Authors: V. K. Lamba, Abhinandan Bharti

Abstract:

We investigate the electronic transport properties across the graphene/ pentacene and gold/pentacene interface. Further, we studied the effect of ripples/bends in pentacene using NEGF-DFT approach. Current transport across the pentacene/graphene interface is found to be remarkably different from transport across pentacene/Gold interfaces. We found that current across these interfaces could be accurately modeled by a combination of thermionic and Poole–Frenkel emission. Further, the degree of bend or degrees of the curve formed during ripple formation strongly change the optimized geometric structures, charge distributions, energy bands, and DOS. The misorientation and hybridization of carbon orbitals are associated with a variation in bond lengths and carrier densities, and are the causes of the dramatic changes in the electronic structure during ripple formation. The electrical conductivity decreases with increase in curvature during ripple formation or due to bending of pentacene molecule and a decrease in conductivity is directly proportional to the increase in curvature angle and given by quadratic relation.

Keywords: hetero-junction, grapheme, NEGF-DFT, pentacene, gold/pentacene

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Authors: Bingjie Wu, C. Q. Ru

Abstract:

The present work studies several reasonably expected candidate integral forms for self-attractive potential energy of a free monolayer graphene sheet. The admissibility of a specific integral form for ripple formation is verified, while all others most of the candidate integral forms are rejected based on the non-existence of stable periodic ripples. Based on the selected integral form of self-attractive potential energy, some mechanical behavior, including ripple formation and buckling, of a free monolayer grapheme sheet are discussed in details

Keywords: graphene, monolayer, ripples, van der Waals energy

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Authors: Sandeep Kumar, Naveen Gupta

Abstract:

Terahertz (THz) generation has been investigated by beating two cosh-Gaussian laser beams of the same amplitude but different wavenumbers and frequencies through rippled collisionless plasma. The ponderomotive force is operative which is induced due to the intensity gradient of the laser beam over the cross-section area of the wavefront. The electrons evacuate towards a low-intensity regime, which modifies the dielectric function of the medium and results in cross focusing of cosh-Gaussian laser beams. The evolution of spot size of laser beams has been studied by solving nonlinear Schrodinger wave equation (NLSE) with variational technique. The laser beams impart oscillations to electrons which are enhanced with ripple density. The nonlinear oscillatory motion of electrons gives rise to a nonlinear current density driving THz radiation. It has been observed that the periodicity of the ripple density helps to enhance the THz radiation.

Keywords: rippled collisionless plasma, cosh-gaussian laser beam, ponderomotive force, variational technique, nonlinear current density

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Authors: Marulasiddappa H. B., Pushparajesh Viswanathan

Abstract:

Day by day, the uses of internal combustion engines (ICE) are deteriorating because of pollution and less fuel availability. In the present scenario, the electric vehicle (EV) plays a major role in the place of an ICE vehicle. The performance of EVs can be improved by the proper selection of electric motors. Initially, EV preferred induction motors for traction purposes, but due to complexity in controlling induction motor, permanent magnet synchronous motor (PMSM) is replacing induction motor in EV due to its advantages. Direct torque control (DTC) is one of the known techniques for PMSM drive in EV to control the torque and speed. However, the presence of torque ripple is the main drawback of this technique. Many control strategies are followed to reduce the torque ripples in PMSM. In this paper, the adaptive neuro-fuzzy inference system (ANFIS) controller technique is proposed to reduce torque ripples and settling time. Here the performance parameters like torque, speed and settling time are compared between conventional proportional-integral (PI) controller with ANFIS controller.

Keywords: direct torque control, electric vehicle, torque ripple, PMSM

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Authors: Y. Kobori, S. Tanaka, N. Tsukiji, N. Takai, H. Kobayashi

Abstract:

This paper proposes two kinds of new single-inductor dual-output (SIDO) DC-DC switching converters with ripple-based hysteretic control. First SIDO converters of type 1 utilize the triangular signal generated by the CR-circuit connected across the inductor. This triangular signal is used for generating the PWM signal instead of the saw-tooth signal used in the conventional converters. Second SIDO converters of type 2 utilize the triangular signal generated by the CR-circuit connected across the voltage error amplifier. This paper describes circuit topologies, Operation principles, simulation results and experimental results of the proposed SIDO converters. In simulation results of both type of SIDO converters, static output voltage ripples are less than 5mVpp and over/under shoots of the dynamic load regulations for the output current step are less than +/- 10mV. In experimental results of single output converter of type 2, static output voltage ripples are about 20mVpp. Output ripples of SIDO type 1 converter are about 80mVpp.

Keywords: DC-DC converter, switching converter, SIDO converter, hysteretic control, ripple-based control

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