Search results for: BPX – Block to Processor Interface part of the Interconnection Network
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 5462

Search results for: BPX – Block to Processor Interface part of the Interconnection Network

5372 The Decentralized Nonlinear Controller of Robot Manipulator with External Load Compensation

Authors: Sun Lim, Il-Kyun Jung

Abstract:

This paper describes a newly designed decentralized nonlinear control strategy to control a robot manipulator. Based on the concept of the nonlinear state feedback theory and decentralized concept is developed to improve the drawbacks in previous works concerned with complicate intelligent control and low cost effective sensor. The control methodology is derived in the sense of Lyapunov theorem so that the stability of the control system is guaranteed. The decentralized algorithm does not require other joint angle and velocity information. Individual Joint controller is implemented using a digital processor with nearly actuator to make it possible to achieve good dynamics and modular. Computer simulation result has been conducted to validate the effectiveness of the proposed control scheme under the occurrence of possible uncertainties and different reference trajectories. The merit of the proposed control system is indicated in comparison with a classical control system.

Keywords: Robot manipulator control, nonlinear controller, Lyapunov based stability, Interconnection compensation.

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5371 Security Engine Management of Router based on Security Policy

Authors: Su Hyung Jo, Ki Young Kim, Sang Ho Lee

Abstract:

Security management has changed from the management of security equipments and useful interface to manager. It analyzes the whole security conditions of network and preserves the network services from attacks. Secure router technology has security functions, such as intrusion detection, IPsec(IP Security) and access control, are applied to legacy router for secure networking. It controls an unauthorized router access and detects an illegal network intrusion. This paper relates to a security engine management of router based on a security policy, which is the definition of security function against a network intrusion. This paper explains the security policy and designs the structure of security engine management framework.

Keywords: Policy server, security engine, security management, security policy

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5370 A New Block-based NLMS Algorithm and Its Realization in Block Floating Point Format

Authors: Abhijit Mitra

Abstract:

we propose a new normalized LMS (NLMS) algorithm, which gives satisfactory performance in certain applications in comaprison with con-ventional NLMS recursion. This new algorithm can be treated as a block based simplification of NLMS algorithm with significantly reduced number of multi¬ply and accumulate as well as division operations. It is also shown that such a recursion can be easily implemented in block floating point (BFP) arithmetic, treating the implementational issues much efficiently. In particular, the core challenges of a BFP realization to such adaptive filters are mainly considered in this regard. A global upper bound on the step size control parameter of the new algorithm due to BFP implementation is also proposed to prevent overflow in filtering as well as weight updating operations jointly.

Keywords: Adaptive algorithm, Block floating point arithmetic, Implementation issues, Normalized least mean square methods

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5369 Optimized Brain Computer Interface System for Unspoken Speech Recognition: Role of Wernicke Area

Authors: Nassib Abdallah, Pierre Chauvet, Abd El Salam Hajjar, Bassam Daya

Abstract:

In this paper, we propose an optimized brain computer interface (BCI) system for unspoken speech recognition, based on the fact that the constructions of unspoken words rely strongly on the Wernicke area, situated in the temporal lobe. Our BCI system has four modules: (i) the EEG Acquisition module based on a non-invasive headset with 14 electrodes; (ii) the Preprocessing module to remove noise and artifacts, using the Common Average Reference method; (iii) the Features Extraction module, using Wavelet Packet Transform (WPT); (iv) the Classification module based on a one-hidden layer artificial neural network. The present study consists of comparing the recognition accuracy of 5 Arabic words, when using all the headset electrodes or only the 4 electrodes situated near the Wernicke area, as well as the selection effect of the subbands produced by the WPT module. After applying the articial neural network on the produced database, we obtain, on the test dataset, an accuracy of 83.4% with all the electrodes and all the subbands of 8 levels of the WPT decomposition. However, by using only the 4 electrodes near Wernicke Area and the 6 middle subbands of the WPT, we obtain a high reduction of the dataset size, equal to approximately 19% of the total dataset, with 67.5% of accuracy rate. This reduction appears particularly important to improve the design of a low cost and simple to use BCI, trained for several words.

Keywords: Brain-computer interface, speech recognition, electroencephalography EEG, Wernicke area, artificial neural network.

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5368 Implementation of Parallel Interface for Microprocessor Trainer

Authors: Moe Moe Htun, Khin Htar Nwe

Abstract:

In this paper, parallel interface for microprocessor trainer was implemented. A programmable parallel–port device such as the IC 8255A is initialized for simple input or output and for handshake input or output by choosing kinds of modes. The hardware connections and the programs can be used to interface microprocessor trainer and a personal computer by using IC 8255A. The assembly programs edited on PC-s editor can be downloaded to the trainer.

Keywords: Parallel I/O ports, parallel interface, trainer, two 8255 ICs.

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5367 2 – Block 3 - Point Modified Numerov Block Methods for Solving Ordinary Differential Equations

Authors: Abdu Masanawa Sagir

Abstract:

In this paper, linear multistep technique using power series as the basis function is used to develop the block methods which are suitable for generating direct solution of the special second order ordinary differential equations of the form y′′ = f(x,y), a < = x < = b with associated initial or boundary conditions. The continuaous hybrid formulations enable us to differentiate and evaluate at some grids and off – grid points to obtain two different three discrete schemes, each of order (4,4,4)T, which were used in block form for parallel or sequential solutions of the problems. The computational burden and computer time wastage involved in the usual reduction of second order problem into system of first order equations are avoided by this approach. Furthermore, a stability analysis and efficiency of the block method are tested on linear and non-linear ordinary differential equations whose solutions are oscillatory or nearly periodic in nature, and the results obtained compared favourably with the exact solution.

Keywords: Block Method, Hybrid, Linear Multistep Method, Self – starting, Special Second Order.

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5366 Performance of Hybrid-MIMO Receiver Scheme in Cognitive Radio Network

Authors: Tanapong Khomyat, Peerapong Uthansakul, Monthippa Uthansakul

Abstract:

In this paper, we evaluate the performance of the Hybrid-MIMO Receiver Scheme (HMRS) in Cognitive Radio network (CR-network). We investigate the efficiency of the proposed scheme which the energy level and user number of primary user are varied according to the characteristic of CR-network. HMRS can allow users to transmit either Space-Time Block Code (STBC) or Spatial-Multiplexing (SM) streams simultaneously by using Successive Interference Cancellation (SIC) and Maximum Likelihood Detection (MLD). From simulation, the results indicate that the interference level effects to the performance of HMRS. Moreover, the exact closed-form capacity of the proposed scheme is derived and compared with STBC scheme.

Keywords: Hybrid-MIMO, Cognitive radio network (CRnetwork), Symbol Error Rate (SER), Successive interference cancellation (SIC), Maximum likelihood detection (MLD).

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5365 Sequential Straightforward Clustering for Local Image Block Matching

Authors: Mohammad Akbarpour Sekeh, Mohd. Aizaini Maarof, Mohd. Foad Rohani, Malihe Motiei

Abstract:

Duplicated region detection is a technical method to expose copy-paste forgeries on digital images. Copy-paste is one of the common types of forgeries to clone portion of an image in order to conceal or duplicate special object. In this type of forgery detection, extracting robust block feature and also high time complexity of matching step are two main open problems. This paper concentrates on computational time and proposes a local block matching algorithm based on block clustering to enhance time complexity. Time complexity of the proposed algorithm is formulated and effects of two parameter, block size and number of cluster, on efficiency of this algorithm are considered. The experimental results and mathematical analysis demonstrate this algorithm is more costeffective than lexicographically algorithms in time complexity issue when the image is complex.

Keywords: Copy-paste forgery detection, Duplicated region, Timecomplexity, Local block matching, Sequential block clustering.

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5364 Maximum Induced Subgraph of an Augmented Cube

Authors: Meng-Jou Chien, Jheng-Cheng Chen, Chang-Hsiung Tsai

Abstract:

Let maxζG(m) denote the maximum number of edges in a subgraph of graph G induced by m nodes. The n-dimensional augmented cube, denoted as AQn, a variation of the hypercube, possesses some properties superior to those of the hypercube. We study the cases when G is the augmented cube AQn.

Keywords: Interconnection network, Augmented cube, Induced subgraph, Bisection width.

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5363 Interface Location in Single Phase Stirred Tanks

Authors: I. Mahdavi, R. Janamiri, A. Sinkakarimi, M. Safdari, M. H. Sedaghat, A. Zamani, A. Hoseini, M. Karimi

Abstract:

In this work, study the location of interface in a stirred vessel with Rushton impeller by computational fluid dynamic was presented. To modeling rotating the impeller, sliding mesh (SM) technique was used and standard k-ε model was selected for turbulence closure. Mean tangential, radial and axial velocities and also turbulent kinetic energy (k) and turbulent dissipation rate (ε) in various points of tank was investigated. Results show sensitivity of system to location of interface and radius of 7 to 10cm for interface in the vessel with existence characteristics cause to increase the accuracy of simulation.

Keywords: CFD, Interface, Rushton impeller, Turbulence model.

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5362 Urban Ecological Interaction: Air, Water, Light and New Transit at the Human Scale of Barcelona’s Superilles

Authors: Philip Speranza

Abstract:

As everyday transit options are shifting from autocentric to pedestrian and bicycle oriented modes for healthy living, downtown streets are becoming more attractive places to live. However, tools and methods to measure the natural environment at the small scale of streets do not exist. Fortunately, a combination of mobile data collection technology and parametric urban design software now allows an interface to relate urban ecological conditions. This paper describes creation of an interactive tool to measure urban phenomena of air, water, and heat/light at the scale of new three-by-three block pedestrianized areas in Barcelona called Superilles. Each Superilla limits transit to the exterior of the blocks and to create more walkable and bikeable interior streets for healthy living. The research will describe the integration of data collection, analysis, and design output via a live interface using parametric software Rhino Grasshopper and the Human User Interface (UI) plugin.

Keywords: Transit, urban design, GIS, parametric design, Superilles, Barcelona, urban ecology.

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5361 A Literature Survey of Neural Network Applications for Shunt Active Power Filters

Authors: S. Janpong, K-L. Areerak, K-N. Areerak

Abstract:

This paper aims to present the reviews of the application of neural network in shunt active power filter (SAPF). From the review, three out of four components of SAPF structure, which are harmonic detection component, compensating current control, and DC bus voltage control, have been adopted some of neural network architecture as part of its component or even substitution. The objectives of most papers in using neural network in SAPF are to increase the efficiency, stability, accuracy, robustness, tracking ability of the systems of each component. Moreover, minimizing unneeded signal due to the distortion is the ultimate goal in applying neural network to the SAPF. The most famous architecture of neural network in SAPF applications are ADALINE and Backpropagation (BP).

Keywords: Active power filter, neural network, harmonic distortion, harmonic detection and compensation, non-linear load.

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5360 Development of Optimized User Interface of Public Transit Navigator for a Smartphone

Authors: Masahiro Taketa, Masaki Ito, Takao Kawamura, Kazunori Sugahara

Abstract:

We develop a new interface for Bus-Net which is optimized for a smartphone. We are continuing to develop the shortest path planning system of public transportation called "Bus-Net" in Tottori prefecture as web application to improve the usability of public transportation. Recent trend of computing platform, however has shifted to an advanced mobile device called a smartphone such as iPhone and Android in Japan. A smartphone has different characters with existing feature phone in terms of OS, large touche panel, and several other features. We derive a guideline to design the new interface for a smartphone to full use of the functionality. The guideline is about simplicity of user-s operation, location awareness and usability. We developed the new interface for “Bus-Net" on iPhone referring to the guideline. Due to the evaluation, the application interface we developed is better than the existing web-based interface in terms of the usability.

Keywords: Path Planning, Public Transportation, Smartphone, User Interface

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5359 Viability of Rice Husk Ash Concrete Brick/Block from Green Electricity in Bangladesh

Authors: Mohammad A. N. M. Shafiqul Karim

Abstract:

As a developing country, Bangladesh has to face numerous challenges. Self Independence in electricity, contributing to climate change by reducing carbon emission and bringing the backward population of society to the mainstream is more challenging for them. Therefore, it is essential to ensure recycled use of local products to the maximum level in every sector. Some private organizations have already worked alongside government to bring the backward population to the mainstream by developing their financial capacities. As rice husk is the largest single category of the total energy supply in Bangladesh. As part of this strategy, rice husk can play a great as a promising renewable energy source, which is readily available, has considerable environmental benefits and can produce electricity and ensure multiple uses of byproducts in construction technology. For the first time in Bangladesh, an experimental multidimensional project depending on Rice Husk Electricity and Rice Husk Ash (RHA) concrete brick/block under Green Eco-Tech Limited has already been started. Project analysis, opportunity, sustainability, the high monitoring component, limitations and finally evaluated data reflecting the viability of establishing more projects using rice husk are discussed in this paper. The by-product of rice husk from the production of green electricity, RHA, can be used for making, in particular, RHA concrete brick/block in Bangladeshi aspects is also discussed here.

Keywords: Project analysis, rice husk, rice husk ash concrete brick/block, compressive strength of rice husk ash concrete brick/block.

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5358 CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers

Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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5357 CFD Investigation of Interface Location in Stirred Tanks with a Concave Impeller

Authors: P. Parvasi, R. Janamiri, A. Sinkakarimi, I. Mahdavi, M. Safdari, M. H. Sedaghat, A. Hosseini, M. Karimi

Abstract:

In this work study the location of interface in a stirred vessel with a Concave impeller by computational fluid dynamic was presented. To modeling rotating the impeller, sliding mesh (SM) technique was used and standard k-ε model was selected for turbulence closure. Mean tangential, radial and axial velocities and also turbulent kinetic energy (k) and turbulent dissipation rate (ε) in various points of tank was investigated. Results show sensitivity of system to location of interface and radius of 7 to 10cm for interface in the vessel with existence characteristics cause to increase the accuracy of simulation.

Keywords: CFD, Interface, Concave impeller, turbulence model.

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5356 A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic

Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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5355 A Novel Optimized JTAG Interface Circuit Design

Authors: Chenguang Guo, Lei Chen, Yanlong Zhang

Abstract:

This paper describes a novel optimized JTAG interface circuit between a JTAG controller and target IC. Being able to access JTAG using only one or two pins, this circuit does not change the original boundary scanning test frequency of target IC. Compared with the traditional JTAG interface which based on IEEE std. 1149.1, this reduced pin technology is more applicability in pin limited devices, and it is easier to control the scale of target IC for the designer.

Keywords: Boundary scan, JTAG interface, Test frequency, Reduced pin

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5354 Magnetic Field Based Near Surface Haptic and Pointing Interface

Authors: Kasun Karunanayaka, Sanath Siriwardana, Chamari Edirisinghe, Ryohei Nakatsu, PonnampalamGopalakrishnakone

Abstract:

In this paper, we are presenting a new type of pointing interface for computers which provides mouse functionalities with near surface haptic feedback. Further, it can be configured as a haptic display where users may feel the basic geometrical shapes in the GUI by moving the finger on top of the device surface. These functionalities are achieved by tracking three dimensional positions of the neodymium magnet using Hall Effect sensors grid and generating like polarity haptic feedback using an electromagnet array. This interface brings the haptic sensations to the 3D space where previously it is felt only on top of the buttons of the haptic mouse implementations.

Keywords: Pointing interface, near surface haptic feedback, tactile display, tangible user interface.

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5353 Techno-Economic Prospects of High Wind Energy Share in Remote vs. Interconnected Island Grids

Authors: Marina Kapsali, John S. Anagnostopoulos

Abstract:

On the basis of comparative analysis of alternative “development scenarios” for electricity generation, the main objective of the present study is to investigate the techno-economic viability of high wind energy (WE) use at the local (island) level. An integrated theoretical model is developed based on first principles assuming two main possible scenarios for covering future electrification needs of a medium–sized Greek island, i.e. Lesbos. The first scenario (S1), assumes that the island will keep using oil products as the main source for electricity generation. The second scenario (S2) involves the interconnection of the island with the mainland grid to satisfy part of the electricity demand, while remarkable WE penetration is also achieved. The economic feasibility of the above solutions is investigated in terms of determining their Levelized Cost of Energy (LCOE) for the time-period 2020-2045, including also a sensitivity analysis on the worst/reference/best Cases. According to the results obtained, interconnection of Lesbos Island with the mainland grid (S2) presents considerable economic interest in comparison to autonomous development (S1) with WE having a prominent role to this effect.

Keywords: Electricity generation cost, levelized cost of energy, mainland, wind energy surplus.

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5352 Diffusion Analysis of a Scalable Feistel Network

Authors: Subariah Ibrahim, Mohd Aizaini Maarof

Abstract:

A generalization of the concepts of Feistel Networks (FN), known as Extended Feistel Network (EFN) is examined. EFN splits the input blocks into n > 2 sub-blocks. Like conventional FN, EFN consists of a series of rounds whereby at least one sub-block is subjected to an F function. The function plays a key role in the diffusion process due to its completeness property. It is also important to note that in EFN the F-function is the most computationally expensive operation in a round. The aim of this paper is to determine a suitable type of EFN for a scalable cipher. This is done by analyzing the threshold number of rounds for different types of EFN to achieve the completeness property as well as the number of F-function required in the network. The work focuses on EFN-Type I, Type II and Type III only. In the analysis it is found that EFN-Type II and Type III diffuses at the same rate and both are faster than Type-I EFN. Since EFN-Type-II uses less F functions as compared to EFN-Type III, therefore Type II is the most suitable EFN for use in a scalable cipher.

Keywords: Cryptography, Extended Feistel Network, Diffusion Analysis.

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5351 Packing and Covering Radii of Linear Error-Block Codes

Authors: Rabiˆı DARITI, El Mamoun SOUIDI

Abstract:

Linear error-block codes are a natural generalization of linear error correcting codes. The purpose of this paper is to generalize some results on the packing and the covering radii to the error-block case. We study their properties when a code undergoes some specific modifications and combinations with another code. We give a few bounds on the packing and the covering radii of these codes.

Keywords: Linear error-block codes, π-distance, Correction capacity, Packing radius, Covering radius.

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5350 Dual-Link Hierarchical Cluster-Based Interconnect Architecture for 3D Network on Chip

Authors: Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin, Lieguang zeng

Abstract:

Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Keywords: Network on Chip (NoC), interconnect architecture, performance, area, Three Dimensional Integrate Circuit (3D IC).

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5349 A Finite Precision Block Floating Point Treatment to Direct Form, Cascaded and Parallel FIR Digital Filters

Authors: Abhijit Mitra

Abstract:

This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.

Keywords: Finite impulse response digital filters, Cascade structure, Parallel structure, Block floating point arithmetic, Roundoff error.

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5348 Development of Gas Chromatography Model: Propylene Concentration Using Neural Network

Authors: Areej Babiker Idris Babiker, Rosdiazli Ibrahim

Abstract:

Gas chromatography (GC) is the most widely used technique in analytical chemistry. However, GC has high initial cost and requires frequent maintenance. This paper examines the feasibility and potential of using a neural network model as an alternative whenever GC is unvailable. It can also be part of system verification on the performance of GC for preventive maintenance activities. It shows the performance of MultiLayer Perceptron (MLP) with Backpropagation structure. Results demonstrate that neural network model when trained using this structure provides an adequate result and is suitable for this purpose. cm.

Keywords: Analyzer, Levenberg-Marquardt, Gas chromatography, Neural network

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5347 Effect of Preloading on the Contact Stress Distribution of a Dovetail Interface

Authors: Kaliyaperumal Anandavel, Raghu V. Prakash, Antonio Davis

Abstract:

This paper presents the influence of preloading on a) the contact tractions, b) slip levels and c) stresses at the dovetail blade-disc interface of an aero-engine through a three-dimensional (3D) finite element (FE) modeling and analysis. The preloading is applied by an interference fit at the dovetail interface and the bulk loading is applied through the rotational speed of rotor. Preloading at the dovetail interface reduces the peak contact pressure developed due to bulk loading up to 35%, and reduces the peak contact pressure and stress difference between top and bottom contact edges. Increasing the level of preloading reduces the cyclic stress amplitude at the interface up to certain values of preload and as a consequence, an improvement in fatigue life could be expected. Fretting damage, due to vibration and wind milling effect during engine ground condition, can be minimized by preloading the dovetail interface.

Keywords: Dovetail interface, Preload, Interference fit, ContactStress, Fretting Fatigue.

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5346 Performance of Block Codes Using the Eigenstructure of the Code Correlation Matrixand Soft-Decision Decoding of BPSK

Authors: Vitalice K. Oduol, C. Ardil

Abstract:

A method is presented for obtaining the error probability for block codes. The method is based on the eigenvalueeigenvector properties of the code correlation matrix. It is found that under a unary transformation and for an additive white Gaussian noise environment, the performance evaluation of a block code becomes a one-dimensional problem in which only one eigenvalue and its corresponding eigenvector are needed in the computation. The obtained error rate results show remarkable agreement between simulations and analysis.

Keywords: bit error rate, block codes, code correlation matrix, eigenstructure, soft-decision decoding, weight vector.

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5345 Implementation of TinyHash based on Hash Algorithm for Sensor Network

Authors: HangRok Lee, YongJe Choi, HoWon Kim

Abstract:

In recent years, it has been proposed security architecture for sensor network.[2][4]. One of these, TinySec by Chris Kalof, Naveen Sastry, David Wagner had proposed Link layer security architecture, considering some problems of sensor network. (i.e : energy, bandwidth, computation capability,etc). The TinySec employs CBC_mode of encryption and CBC-MAC for authentication based on SkipJack Block Cipher. Currently, This TinySec is incorporated in the TinyOS for sensor network security. This paper introduces TinyHash based on general hash algorithm. TinyHash is the module in order to replace parts of authentication and integrity in the TinySec. it implies that apply hash algorithm on TinySec architecture. For compatibility about TinySec, Components in TinyHash is constructed as similar structure of TinySec. And TinyHash implements the HMAC component for authentication and the Digest component for integrity of messages. Additionally, we define the some interfaces for service associated with hash algorithm.

Keywords: sensor network security, nesC, TinySec, TinyOS, Hash, HMAC, integrity

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5344 Interconnection of Autonomous PROFIBUS Segments through IEEE 802.16 WMAN

Authors: M. İskefiyeli, İ. Özçelik

Abstract:

PROFIBUS (PROcess FIeld BUS) which is defined with international standarts (IEC61158, EN50170) is the most popular fieldbus, and provides a communication between industrial applications which are located in different control environment and location in manufacturing, process and building automation. Its communication speed is from 9.6 Kbps to 12 Mbps over distances from 100 to 1200 meters, and so it is to be often necessary to interconnect them in order to break these limits. Unfortunately this interconnection raises several issues and the solutions found so far are not very satisfactory. In this paper, we propose a new solution to interconnect PROFIBUS segments, which uses a wireless MAN based on the IEEE 802.16 standard as a backbone system. Also, the solution which is described a model for internetworking unit integrates the traffic generated by PROFIBUS segments into IEEE 802.16 wireless MAN using encapsulation technique.

Keywords: Internetworking Unit, PROFIBUS, WiMAX, WMAN, 802.16.

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5343 A Family of Zero Stable Block Integrator for the Solutions of Ordinary Differential Equations

Authors: A. M. Sagir

Abstract:

In this paper, linear multistep technique using power series as the basis function is used to develop the block methods which are suitable for generating direct solution of the special second order ordinary differential equations with associated initial or boundary conditions. The continuous hybrid formulations enable us to differentiate and evaluate at some grids and off – grid points to obtain two different four discrete schemes, each of order (5,5,5,5)T, which were used in block form for parallel or sequential solutions of the problems. The computational burden and computer time wastage involved in the usual reduction of second order problem into system of first order equations are avoided by this approach. Furthermore, a stability analysis and efficiency of the block methods are tested on linear and non-linear ordinary differential equations and the results obtained compared favorably with the exact solution.

Keywords: Block Method, Hybrid, Linear Multistep Method, Self – starting, Special Second Order.

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