Search results for: Active logic.

Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

Abstract:

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Cecília Reis, J. A. Tenreiro Machado, J. Boaventura Cunha

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This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. The experiments reveal superior results in terms of speed and convergence to achieve a solution.

Keywords: Circuit design, fractional-order systems, genetic algorithms, logic circuits

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Authors: Fayssal Amrane, Azeddine Chaiba

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In this paper, type-2 fuzzy logic control (T2FLC) and neuro-fuzzy control (NFC) for a doubly fed induction generator (DFIG) based on direct power control (DPC) with a fixed switching frequency is proposed for wind generation application. First, a mathematical model of the doubly-fed induction generator implemented in d-q reference frame is achieved. Then, a DPC algorithm approach for controlling active and reactive power of DFIG via fixed switching frequency is incorporated using PID. The performance of T2FLC and NFC, which is based on the DPC algorithm, are investigated and compared to those obtained from the PID controller. Finally, simulation results demonstrate that the NFC is more robust, superior dynamic performance for wind power generation system applications.

Keywords: Doubly fed induction generetor, direct power control, space vector modulation, type-2 fuzzy logic control, neuro-fuzzy control, maximum power point tracking.

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Authors: Padmanabhan Balasubramanian, R. Chinnadurai

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This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).

Keywords: Achilles' heel functions, AND-EXOR-Inverter logic, CMOS technology, low power design.

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Authors: Noura Boudiaf, Abdelhamid Djebbar

Abstract:

Colored Petri Nets (CPN) are very known kind of high level Petri nets. With sound and complete semantics, rewriting logic is one of very powerful logics in description and verification of non-deterministic concurrent systems. Recently, CPN semantics are defined in terms of rewriting logic, allowing us to built models by formal reasoning. In this paper, we propose an automatic translation of CPN to the rewriting logic language Maude. This tool allows graphical editing and simulating CPN. The tool allows the user drawing a CPN graphically and automatic translating the graphical representation of the drawn CPN to Maude specification. Then, Maude language is used to perform the simulation of the resulted Maude specification. It is the first rewriting logic based environment for this category of Petri Nets.

Keywords: Colored Petri Nets, Rewriting Logic, Maude, Graphical Edition, Automatic Translation, Simulation.

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Authors: Daniel Stamate

Abstract:

We introduce a logic-based framework for database updating under constraints. In our framework, the constraints are represented as an instantiated extended logic program. When performing an update, database consistency may be violated. We provide an approach of maintaining database consistency, and study the conditions under which the maintenance process is deterministic. We show that the complexity of the computations and decision problems presented in our framework is in each case polynomial time.

Keywords: Databases, knowledge bases, constraints, updates, minimal change, consistency.

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Authors: V. K. Banga, R. Kumar, Y. Singh

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In this paper, we present optimal control for movement and trajectory planning for four degrees-of-freedom robot using Fuzzy Logic (FL) and Genetic Algorithms (GAs). We have evaluated using Fuzzy Logic (FL) and Genetic Algorithms (GAs) for four degree-of-freedom (4 DOF) robotics arm, Uncertainties like; Movement, Friction and Settling Time in robotic arm movement have been compensated using Fuzzy logic and Genetic Algorithms. The development of a fuzzy genetic optimization algorithm is presented and discussed. The result are compared only GA and Fuzzy GA. This paper describes genetic algorithms, which is designed to optimize robot movement and trajectory. Though the model represents is a general model for redundant structures and could represent any n-link structures. The result is a complete trajectory planning with Fuzzy logic and Genetic algorithms demonstrating the flexibility of this technique of artificial intelligence.

Keywords: Inverse kinematics, Genetic algorithms (GAs), Fuzzy logic (FL), Trajectory planning.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA-s components for solving different “test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

Keywords: Design of logic circuit, evolutionary computation, evolvable hardware, mutation rate.

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Authors: N. A. Muhamad, S.A.M. Ali

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Condition monitoring of electrical power equipment has attracted considerable attention for many years. The aim of this paper is to use Labview with Fuzzy Logic controller to build a simulation system to diagnose transformer faults and monitor its condition. The front panel of the system was designed using LabVIEW to enable computer to act as customer-designed instrument. The dissolved gas-in-oil analysis (DGA) method was used as technique for oil type transformer diagnosis; meanwhile terminal voltages and currents analysis method was used for dry type transformer. Fuzzy Logic was used as expert system that assesses all information keyed in at the front panel to diagnose and predict the condition of the transformer. The outcome of the Fuzzy Logic interpretation will be displayed at front panel of LabVIEW to show the user the conditions of the transformer at any time.

Keywords: LabVIEW, Fuzzy Logic, condition monitoring, oiltransformer, dry transformer, DGA, terminal values.

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Authors: T. Juhana Hashim, A. Mohamed

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This paper discusses the implementation of a fuzzy logic based coordinated voltage control for a distribution system connected with distributed generations (DGs). The connection of DGs has created a challenge for the distribution network operators to keep the voltage in the system within its acceptable limits. Intelligent centralized or coordinated voltage control schemes have proven to be more reliable due to its ability to provide more control and coordination with the communication with other network devices. In this work, voltage control using fuzzy logic by coordinating three methods of control, power factor control, on load tap changer and generation curtailment is implemented on a distribution network test system. The results show that the fuzzy logic based coordination is able to keep the voltage within its allowable limits. 

Keywords: Coordinated control, Distributed generation, Fuzzy logic, Voltage control.

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Authors: Man Li, Wanting Zhou, Lei Li

Abstract:

Communication stability is the primary concern of communication satellites. Communication satellites are easily affected by particle radiation to generate single event effects (SEE), which leads to soft errors (SE) of combinational logic circuit. The existing research on soft error rates (SER) of combined logic circuit is mostly based on the assumption that the logic gates being bombarded have the same pulse width. However, in the actual radiation environment, the pulse widths of the logic gates being bombarded are different due to different linear energy transfers (LET). In order to improve the accuracy of SER evaluation model, this paper proposes a soft error rates evaluation method based on LET. In this paper, we analyze the influence of LET on the pulse width of combinational logic and establish the pulse width model based on LET. Based on this model, the error rate of test circuit ISCAS’85 is calculated. Experimental results show that this model can be used for SER evaluation.

Keywords: Communication satellite, pulse width, soft error rates, linear energy transfer, LET.

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Authors: İres İskender, Ahmet Karaarslan

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In this study, the performance of a high-frequency arc welding machine including a two-switch inverter is analyzed. The control of the system is achieved using two different control techniques i- fuzzy logic control (FLC) ii- state space averaging based sliding control. Fuzzy logic control does not need accurate mathematical model of a plant and can be used in nonlinear applications. The second method needs the mathematical model of the system. In this method the state space equations of the system are derived for two different “on" and “off" states of the switches. The derived state equations are combined with the sliding control rule considering the duty-cycle of the converter. The performance of the system is analyzed by simulating the system using SIMULINK tool box of MATLAB. The simulation results show that fuzzy logic controller is more robust and less sensitive to parameter variations.

Keywords: Fuzzy logic, arc welding, sliding state space control, PWM, current control.

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Authors: A. Bellar, M.K. Fellah, A.M. Si Mohammed, M. Bensaada, L. Boukhris

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This paper presents the use of the predictive fuzzy logic controller (PFLC) applied to attitude control system for agile micro-satellite. In order to reduce the effect of unpredictable time delays and large uncertainties, the algorithm employs predictive control to predict the attitude of the satellite. Comparison of the PFLC and conventional fuzzy logic controller (FLC) is presented to evaluate the performance of the control system during attitude maneuver. The two proposed models have been analyzed with the same level of noise and external disturbances. Simulation results demonstrated the feasibility and advantages of the PFLC on the attitude determination and control system (ADCS) of agile satellite.

Keywords: Agile micro-satellite, Attitude control, fuzzy logic, predictive control

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Sheroz Khan, I. Adam, A. H. M. Zahirul Alam, Mohd Rafiqul Islam, Othman O. Khalifa

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This paper attempts to model and design a simple fuzzy logic controller with Variable Reference. The Variable Reference (VR) is featured as an adaptability element which is obtained from two known variables – desired system-input and actual system-output. A simple fuzzy rule-based technique is simulated to show how the actual system-input is gradually tuned in to a value that closely matches the desired input. The designed controller is implemented and verified on a simple heater which is controlled by PIC Microcontroller harnessed by a code developed in embedded C. The output response of the PIC-controlled heater is analyzed and compared to the performances by conventional fuzzy logic controllers. The novelty of this work lies in the fact that it gives better performance by using less number of rules compared to conventional fuzzy logic controllers.

Keywords: Fuzzy logic controller, Variable reference, Adaptability, Rule-based.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

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The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: Manisha Dubey, Aalok Dubey

Abstract:

This paper presents an approach for the design of fuzzy logic power system stabilizers using genetic algorithms. In the proposed fuzzy expert system, speed deviation and its derivative have been selected as fuzzy inputs. In this approach the parameters of the fuzzy logic controllers have been tuned using genetic algorithm. Incorporation of GA in the design of fuzzy logic power system stabilizer will add an intelligent dimension to the stabilizer and significantly reduces computational time in the design process. It is shown in this paper that the system dynamic performance can be improved significantly by incorporating a genetic-based searching mechanism. To demonstrate the robustness of the genetic based fuzzy logic power system stabilizer (GFLPSS), simulation studies on multimachine system subjected to small perturbation and three-phase fault have been carried out. Simulation results show the superiority and robustness of GA based power system stabilizer as compare to conventionally tuned controller to enhance system dynamic performance over a wide range of operating conditions.

Keywords: Dynamic stability, Fuzzy logic power systemstabilizer, Genetic Algorithms, Genetic based power systemstabilizer

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Authors: Noura Boudiaf, Allaoua Chaoui

Abstract:

To analyze the behavior of Petri nets, the accessibility graph and Model Checking are widely used. However, if the analyzed Petri net is unbounded then the accessibility graph becomes infinite and Model Checking can not be used even for small Petri nets. ECATNets [2] are a category of algebraic Petri nets. The main feature of ECATNets is their sound and complete semantics based on rewriting logic [8] and its language Maude [9]. ECATNets analysis may be done by using techniques of accessibility analysis and Model Checking defined in Maude. But, these two techniques supported by Maude do not work also with infinite-states systems. As a category of Petri nets, ECATNets can be unbounded and so infinite systems. In order to know if we can apply accessibility analysis and Model Checking of Maude to an ECATNet, we propose in this paper an algorithm allowing the detection if the ECATNet is bounded or not. Moreover, we propose a rewriting logic based tool implementing this algorithm. We show that the development of this tool using the Maude system is facilitated thanks to the reflectivity of the rewriting logic. Indeed, the self-interpretation of this logic allows us both the modelling of an ECATNet and acting on it.

Keywords: ECATNets, Rewriting Logic, Maude, Finite-stateSystems, Infinite-state Systems, Boundness Property Checking.

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Authors: Swathi Sampath, V. Kalaichelvi

Abstract:

The assessment of the risk posed by a borrower to a lender is one of the common problems that financial institutions have to deal with. Consumers vying for a mortgage are generally compared to each other by the use of a number called the Credit Score, which is generated by applying a mathematical algorithm to information in the applicant’s credit report. The higher the credit score, the lower the risk posed by the candidate, and the better he is to be taken on by the lender. The objective of the present work is to use fuzzy logic and linguistic rules to create a model that generates Credit Scores.

Keywords: Credit scoring, fuzzy logic, mortgage, risk assessment.

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Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Applications of reversible logic gates in the design of complex integrated circuits provide power optimization.  This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, shift register, signed division.

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Authors: Shih-Ching Lo, Hsieh-Chu Huang

Abstract:

Mostly, pedestrian-car accidents occurred at a signalized interaction is because pedestrians cannot across the intersection safely within the green light. From the viewpoint of pedestrian, there might have two reasons. The first one is pedestrians cannot speed up to across the intersection, such as the elders. The other reason is pedestrians do not sense that the signal phase is going to change and their right-of-way is going to lose. Developing signal logic to protect pedestrian, who is crossing an intersection is the first purpose of this study. Another purpose of this study is improving the reliability and reduce delay of public transportation service. Therefore, bus preemption is also considered in the designed signal logic. In this study, the traffic data of the intersection of Chong-Qing North Road and Min-Zu West Road, Taipei, Taiwan, is employed to calibrate and validate the signal logic by simulation. VISSIM 5.20, which is a microscopic traffic simulation software, is employed to simulate the signal logic. From the simulated results, the signal logic presented in this study can protect pedestrians crossing the intersection successfully. The design of bus preemption can reduce the average delay. However, the pedestrian safety and bus preemptive signal will influence the average delay of cars largely. Thus, whether applying the pedestrian safety and bus preemption signal logic to an isolated intersection or not should be evaluated carefully.

Keywords: vulnerable road user, bus preemption, signal design.

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Authors: Zhen Cheng, Xinyu Dai, Shujian Huang, Jiajun Chen

Abstract:

Recently, explanatory natural language inference has attracted much attention for the interpretability of logic relationship prediction, which is also known as explanation generation for Natural Language Inference (NLI). Existing explanation generators based on discriminative Encoder-Decoder architecture have achieved noticeable results. However, we find that these discriminative generators usually generate explanations with correct evidence but incorrect logic semantic. It is due to that logic information is implicitly encoded in the premise-hypothesis pairs and difficult to model. Actually, logic information identically exists between premise-hypothesis pair and explanation. And it is easy to extract logic information that is explicitly contained in the target explanation. Hence we assume that there exists a latent space of logic information while generating explanations. Specifically, we propose a generative model called Variational Explanation Generator (VariationalEG) with a latent variable to model this space. Training with the guide of explicit logic information in target explanations, latent variable in VariationalEG could capture the implicit logic information in premise-hypothesis pairs effectively. Additionally, to tackle the problem of posterior collapse while training VariaztionalEG, we propose a simple yet effective approach called Logic Supervision on the latent variable to force it to encode logic information. Experiments on explanation generation benchmark—explanation-Stanford Natural Language Inference (e-SNLI) demonstrate that the proposed VariationalEG achieves significant improvement compared to previous studies and yields a state-of-the-art result. Furthermore, we perform the analysis of generated explanations to demonstrate the effect of the latent variable.

Keywords: Natural Language Inference, explanation generation, variational auto-encoder, generative model.

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Authors: Mubarak Alhajri

Abstract:

This paper addresses certain inherent limitations of local priority hysteresis switching logic. Our main result establishes that under persistent excitation assumption, it is possible to relax constraints requiring strict positivity of local priority and hysteresis switching constants. Relaxing these constraints allows the adaptive system to reach optimality which implies the performance improvement. The unconstrained local priority hysteresis switching logic is examined and conditions for global convergence are derived.

Keywords: Adaptive control, convergence, hysteresis constant, hysteresis switching.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

Keywords: Evolvable hardware, genotype size, computational intelligence, design of logic circuits.

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Authors: C. Ardil

Abstract:

Neutrosophic logic decision analysis is proposed as a method of stealth fighter aircraft selection for Turkish Air Force. The opinion of experts is employed to rank the alternatives across a set of criteria. The analyst uses neutrosophic logic numbers to describe the experts' preferences. This approach can handle the situation in the case of unavailability of precise data, which is most commonly the case in stealth fighter aircraft selection. Neutrosophic logic numbers can consider the imprecision of the factors affecting decision making such as stealth analysis, survivability analysis, and performance analysis. Neutrosophic logic ranking is achieved using weighted arithmetic operator and weighted geometric operator and the alternatives are ranked from best to worst. An example is also presented to illustrate the applicability and effectiveness of the proposed method. 

Keywords: Neutrosophic set theory, stealth fighter aircraft selection, multiple criteria decision-making, neutrosophic logic decision making, Turkish Air Force, MCDM

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Authors: André Trudel, Haiyi Zhang

Abstract:

Over the years, many implementations have been proposed for solving IA networks. These implementations are concerned with finding a solution efficiently. The primary goal of our implementation is simplicity and ease of use. We present an IA network implementation based on finite domain non-binary CSPs, and constraint logic programming. The implementation has a GUI which permits the drawing of arbitrary IA networks. We then show how the implementation can be extended to find all the solutions to an IA network. One application of finding all the solutions, is solving probabilistic IA networks.

Keywords: Constraint logic programming, CSP, logic, temporalreasoning.

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Authors: H.S. Kim

Abstract:

In this study, control performance of a smart base isolation system consisting of a friction pendulum system (FPS) and a magnetorheological (MR) damper has been investigated. A fuzzy logic controller (FLC) is used to modulate the MR damper so as to minimize structural acceleration while maintaining acceptable base displacement levels. To this end, a multi-objective optimization scheme is used to optimize parameters of membership functions and find appropriate fuzzy rules. To demonstrate effectiveness of the proposed multi-objective genetic algorithm for FLC, a numerical study of a smart base isolation system is conducted using several historical earthquakes. It is shown that the proposed method can find optimal fuzzy rules and that the optimized FLC outperforms not only a passive control strategy but also a human-designed FLC and a conventional semi-active control algorithm.

Keywords: Fuzzy logic controller, genetic algorithm, MR damper, smart base isolation system

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Authors: Rafat Alshorman, Walter Hussak

Abstract:

Existing work in temporal logic on representing the execution of infinitely many transactions, uses linear-time temporal logic (LTL) and only models two-step transactions. In this paper, we use the comparatively efficient branching-time computational tree logic CTL and extend the transaction model to a class of multistep transactions, by introducing distinguished propositional variables to represent the read and write steps of n multi-step transactions accessing m data items infinitely many times. We prove that the well known correspondence between acyclicity of conflict graphs and serializability for finite schedules, extends to infinite schedules. Furthermore, in the case of transactions accessing the same set of data items in (possibly) different orders, serializability corresponds to the absence of cycles of length two. This result is used to give an efficient encoding of the serializability condition into CTL.

Keywords: computational tree logic, serializability, multi-step transactions.

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Authors: Ahmed Abdulghani Taha, Mohammad Abdulghani Taha

Abstract:

This study aims at being acquainted with the using the body fat percentage (%BF) with body Mass Index (BMI) as input parameters in fuzzy logic decision support system to predict properly the lifted weight for students at weightlifting class lift according to his abilities instead of traditional manner. The sample included 53 male students (age = 21.38 ± 0.71 yrs, height (Hgt) = 173.17 ± 5.28 cm, body weight (BW) = 70.34 ± 7.87.6 kg, Body mass index (BMI) 23.42 ± 2.06 kg.m-2, fat mass (FM) = 9.96 ± 3.15 kg and fat percentage (% BF) = 13.98 ± 3.51 %.) experienced the weightlifting class as a credit and has variance at BW, Hgt and BMI and FM. BMI and % BF were taken as input parameters in FUZZY logic whereas the output parameter was the lifted weight (LW). There were statistical differences between LW values before and after using fuzzy logic (Diff 3.55± 2.21, P > 0.001). The percentages of the LW categories proposed by fuzzy logic were 3.77% of students to lift 1.0 fold of their bodies; 50.94% of students to lift 0.95 fold of their bodies; 33.96% of students to lift 0.9 fold of their bodies; 3.77% of students to lift 0.85 fold of their bodies and 7.55% of students to lift 0.8 fold of their bodies. The study concluded that the characteristic changes in body composition experienced by students when undergoing weightlifting could be utilized side by side with the Fuzzy logic decision support system to determine the proper workloads consistent with the abilities of students.

Keywords: Fuzzy logic, body mass index, body fat percentage, weightlifting.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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