Search results for: CMOS amplifier

Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, Ali Sarchami

Abstract:

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.

Keywords: SRAM, write Operation, read Operation, capacitances, dynamic energy consumption.

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Authors: Jie Jin

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In this paper, a new CMOS current-mode single input and multi-outputs (SIMO) universal filter and quadrature oscillator with a similar circuit are proposed. The circuits only consist of three Current differencing transconductance amplifiers (CDTA) and two grounded capacitors, which are resistorless, and they are suitable for monolithic integration. The universal filter uses minimum CDTAs and passive elements to realize SIMO type low-pass (LP), high-pass (HP), band-pass (BP) band-stop (BS) and all-pass (AP) filter functions simultaneously without any component matching conditions. The angular frequency (ω0) and the quality factor (Q) of the proposed filter can be electronically controlled and tuned orthogonal. By some modifications of the filter, a new current-mode four-phase quadrature oscillator (QO) can be obtained easily. The condition of oscillation (CO) and frequency of oscillation (FO) of the QO can be controlled electronically and independently through the bias current of the CDTAs, and it is suitable for variable frequency oscillator. Moreover, all the passive and active sensitivities of the circuits are low. SPICE simulation results are included to confirm the theory.

Keywords: Universal Filter, Quadrature Oscillator, Current mode, Current differencing transconductance amplifiers.

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Authors: Nawang Chhunid, Gagnesh Kumar

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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

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Authors: A. Thomas, B. John Oommen

Abstract:

Although the field of parametric Pattern Recognition (PR) has been thoroughly studied for over five decades, the use of the Order Statistics (OS) of the distributions to achieve this has not been reported. The pioneering work on using OS for classification was presented in [1] for the Uniform distribution, where it was shown that optimal PR can be achieved in a counter-intuitive manner, diametrically opposed to the Bayesian paradigm, i.e., by comparing the testing sample to a few samples distant from the mean. This must be contrasted with the Bayesian paradigm in which, if we are allowed to compare the testing sample with only a single point in the feature space from each class, the optimal strategy would be to achieve this based on the (Mahalanobis) distance from the corresponding central points, for example, the means. In [2], we showed that the results could be extended for a few symmetric distributions within the exponential family. In this paper, we attempt to extend these results significantly by considering asymmetric distributions within the exponential family, for some of which even the closed form expressions of the cumulative distribution functions are not available. These distributions include the Rayleigh, Gamma and certain Beta distributions. As in [1] and [2], the new scheme, referred to as Classification by Moments of Order Statistics (CMOS), attains an accuracy very close to the optimal Bayes’ bound, as has been shown both theoretically and by rigorous experimental testing.

Keywords: Classification using Order Statistics (OS), Exponential family, Moments of OS

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Authors: Pepin Magnangana Zoko Goyoro, Ibrahim James Moumouni, Sroy Abouty

Abstract:

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient method of data transmission for high speed communication systems. However, the main drawback of OFDM systems is that, it suffers from the problem of high Peak-to-Average Power Ratio (PAPR) which causes inefficient use of the High Power Amplifier and could limit transmission efficiency. OFDM consist of large number of independent subcarriers, as a result of which the amplitude of such a signal can have high peak values. In this paper, we propose an effective reduction scheme that combines DCT and SLM techniques. The scheme is composed of the DCT followed by the SLM using the Riemann matrix to obtain phase sequences for the SLM technique. The simulation results show PAPR can be greatly reduced by applying the proposed scheme. In comparison with OFDM, while OFDM had high values of PAPR –about 10.4dB our proposed method achieved about 4.7dB reduction of the PAPR with low complexities computation. This approach also avoids randomness in phase sequence selection, which makes it simpler to decode at the receiver. As an added benefit, the matrices can be generated at the receiver end to obtain the data signal and hence it is not required to transmit side information (SI).

Keywords: DCT transform, OFDM, PAPR, Riemann matrix, SLM.

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Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: Amplifier class D, FPGA, protective relay, tester.

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

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An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: M. Chitsazi, B. Maraghechi, M. H. Rouhani

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Three-dimensional simulation of harmonic up generation in free electron laser amplifier operating simultaneously with a cold and relativistic electron beam is presented in steady-state regime where the slippage of the electromagnetic wave with respect to the electron beam is ignored. By using slowly varying envelope approximation and applying the source-dependent expansion to wave equations, electromagnetic fields are represented in terms of the Hermit Gaussian modes which are well suited for the planar wiggler configuration. The electron dynamics is described by the fully threedimensional Lorentz force equation in presence of the realistic planar magnetostatic wiggler and electromagnetic fields. A set of coupled nonlinear first-order differential equations is derived and solved numerically. The fundamental and third harmonic radiation of the beam is considered. In addition to uniform beam, prebunched electron beam has also been studied. For this effect of sinusoidal distribution of entry times for the electron beam on the evolution of radiation is compared with uniform distribution. It is shown that prebunching reduces the saturation length substantially. For efficiency enhancement the wiggler is set to decrease linearly when the radiation of the third harmonic saturates. The optimum starting point of tapering and the slope of radiation in the amplitude of wiggler are found by successive run of the code.

Keywords: Free electron laser, Prebunching, Undulator, Wiggler.

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Authors: Li Long, Thomas Ortlepp

Abstract:

A theoretical model for the optimization of thermopile sensor performance is developed for thermoelectric-based infrared radiation detection. It is shown that the performance of polycrystalline silicon film thermopile sensor can be optimized according to the thermoelectric quality factor, sensor layer structure factor and sensor layout shape factor. Based on the properties of electrons, phonons, grain boundaries and their interactions, the thermoelectric quality factor of polycrystalline silicon is analyzed with the relaxation time approximation of Boltzmann transport equation. The model includes the effects of grain structure, grain boundary trap properties and doping concentration. The layer structure factor of sensor is analyzed with respect to infrared absorption coefficient. The effect of layout design is characterized with the shape factor, which is calculated for different sensor designs. Double layer polycrystalline silicon thermopile infrared sensors on suspended support membrane have been designed and fabricated with a CMOS-compatible process. The theoretical approach is confirmed with measurement results.

Keywords: Polycrystalline silicon film, relaxation time approximation, specific detectivity, thermal conductivity, thermopile infrared sensor.

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Authors: A. Leelasantitham, B. Srisuchinwong

Abstract:

A high-frequency low-power sinusoidal quadrature oscillator is presented through the use of two 2nd-order low-pass current-mirror (CM)-based filters, a 1st-order CM low-pass filter and a CM bilinear transfer function. The technique is relatively simple based on (i) inherent time constants of current mirrors, i.e. the internal capacitances and the transconductance of a diode-connected NMOS, (ii) a simple negative resistance RN formed by a resistor load RL of a current mirror. Neither external capacitances nor inductances are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz and is current-tunable over a range of 370 MHz or 21.6 %. The power consumption is at approximately 0.45 mW. The amplitude matching and the quadrature phase matching are better than 0.05 dB and 0.15°, respectively. Total harmonic distortions (THD) are less than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The ratio of the oscillation frequency (f0) to the unity-gain frequency (fT) of a transistor is 0.25. Comparisons to other approaches are also included.

Keywords: Sinusoidal quadrature oscillator, low-pass-filterbased, current-mirror bilinear transfer function, all-current-mirror, negative resistance, low power, high frequency, low distortion.

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Authors: Maurizio Dapor, Isabel Abril, Pablo de Vera, Rafael Garcia-Molina

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The ionization yield of ion tracks in polymers and bio-molecular systems reaches a maximum, known as the Bragg peak, close to the end of the ion trajectories. Along the path of the ions through the materials, many electrons are generated, which produce a cascade of further ionizations and, consequently, a shower of secondary electrons. Among these, very low energy secondary electrons can produce damage in the biomolecules by dissociative electron attachment. This work deals with the calculation of the energy distribution of electrons produced by protons in a sample of polymethylmethacrylate (PMMA), a material that is used as a phantom for living tissues in hadron therapy. PMMA is also of relevance for microelectronics in CMOS technologies and as a photoresist mask in electron beam lithography. We present a Monte Carlo code that, starting from a realistic description of the energy distribution of the electrons ejected by protons moving through PMMA, simulates the entire cascade of generated secondary electrons. By following in detail the motion of all these electrons, we find the radial distribution of the energy that they deposit in PMMA for several initial proton energies characteristic of the Bragg peak.

Keywords: Monte Carlo method, secondary electrons, energetic ions, ion-beam cancer therapy, ionization cross section, polymethylmethacrylate, proton beams, secondary electrons, radial energy distribution.

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

Abstract:

A synchronous network-on-chip using wormhole packet switching and supporting guaranteed-completion best-effort with low-priority (LP) and high-priority (HP) wormhole packet delivery service is presented in this paper. Both our proposed LP and HP message services deliver a good quality of service in term of lossless packet completion and in-order message data delivery. However, the LP message service does not guarantee minimal completion bound. The HP packets will absolutely use 100% bandwidth of their reserved links if the HP packets are injected from the source node with maximum injection. Hence, the service are suitable for small size messages (less than hundred bytes). Otherwise the other HP and LP messages, which require also the links, will experience relatively high latency depending on the size of the HP message. The LP packets are routed using a minimal adaptive routing, while the HP packets are routed using a non-minimal adaptive routing algorithm. Therefore, an additional 3-bit field, identifying the packet type, is introduced in their packet headers to classify and to determine the type of service committed to the packet. Our NoC prototypes have been also synthesized using a 180-nm CMOS standard-cell technology to evaluate the cost of implementing the combination of both services.

Keywords: Network-on-Chip, Parallel Pipeline Router Architecture, Wormhole Switching, Two-Level Priority Service.

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Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: K. Machida, H. Yamada

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Displacement measurement was conducted on compact normal and shear specimens made of acrylic homogeneous material subjected to mixed-mode loading by digital image correlation. The intelligent hybrid method proposed by Nishioka et al. was applied to the stress-strain analysis near the crack tip. The accuracy of stress-intensity factor at the free surface was discussed from the viewpoint of both the experiment and 3-D finite element analysis. The surface images before and after deformation were taken by a CMOS camera, and we developed the system which enabled the real time stress analysis based on digital image correlation and inverse problem analysis. The great portion of processing time of this system was spent on displacement analysis. Then, we tried improvement in speed of this portion. In the case of cracked body, it is also possible to evaluate fracture mechanics parameters such as the J integral, the strain energy release rate, and the stress-intensity factor of mixed-mode. The 9-points elliptic paraboloid approximation could not analyze the displacement of submicron order with high accuracy. The analysis accuracy of displacement was improved considerably by introducing the Newton-Raphson method in consideration of deformation of a subset. The stress-intensity factor was evaluated with high accuracy of less than 1% of the error.

Keywords: Digital image correlation, mixed mode, Newton-Raphson method, stress intensity factor.

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Authors: R. M. Siddiqui, D. Z. Moghaddam, T. R. Turlapati, S. H. Khan, I. Ul Ahad

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Quality of 2D and 3D cross-sectional images produce by Computed Tomography primarily depend upon the degree of precision of primary and secondary X-Ray intensity detection. Traditional method of primary intensity detection is apt to errors. Recently the X-Ray intensity measurement system along with smart X-Ray sensors is developed by our group which is able to detect primary X-Ray intensity unerringly. In this study a new smart X-Ray sensor is developed using Light-to-Frequency converter TSL230 from Texas Instruments which has numerous advantages in terms of noiseless data acquisition and transmission. TSL230 construction is based on a silicon photodiode which converts incoming X-Ray radiation into the proportional current signal. A current to frequency converter is attached to this photodiode on a single monolithic CMOS integrated circuit which provides proportional frequency count to incoming current signal in the form of the pulse train. The frequency count is delivered to the center of PICDEM FS USB board with PIC18F4550 microcontroller mounted on it. With highly compact electronic hardware, this Demo Board efficiently read the smart sensor output data. The frequency output approaches overcome nonlinear behavior of sensors with analog output thus un-attenuated X-Ray intensities could be measured precisely and better normalization could be acquired in order to attain high resolution.

Keywords: Computed tomography, detector technology, X-Ray intensity measurement

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Authors: Faizal A. Samman, Thomas Hollstein, Manfred Glesner

Abstract:

This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between two- and one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data communications between on-chip routers are implemented synchronously and for quality of service, the inter-router data transports are controlled by using a link-level congestion control to avoid lose of data because of an overflow. The trade-off between the area (logic cell area) and the performance (bandwidth gain) of two proposed NoC router microarchitectures are presented in this paper. The performance evaluation is made by using a traffic scenario with different number of workloads under 2D mesh NoC topology using a static routing algorithm. By using a 130-nm CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz, resulting in a high speed network link and high router bandwidth capacity of about 320 Gbit/s. Based on our experiments, the amount of control path pipeline stages gives more significant impact on the NoC performance than the impact on the logic area of the NoC router.

Keywords: Network-on-Chip, Synchronous Parallel Pipeline, Router Architecture, Wormhole Switching

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Authors: A. Fayad, Q. Alqhazaly, T. Cinkler

Abstract:

In light of the substantial increase in end-user requirements and the incessant need of network operators to upgrade the capabilities of access networks, in this paper, the performance of the different modulation formats on eight-channels Time and Wavelength Division Multiplexing Passive Optical Network (TWDM-PON) transmission system has been examined and compared. Limitations and features of modulation formats have been determined to outline the most suitable design to enhance the data rate and transmission reach to obtain the best performance of the network. The considered modulation formats are On-Off Keying Non-Return-to-Zero (NRZ-OOK), Carrier Suppressed Return to Zero (CSRZ), Duo Binary (DB), Modified Duo Binary (MODB), Quadrature Phase Shift Keying (QPSK), and Differential Quadrature Phase Shift Keying (DQPSK). The performance has been analyzed by varying transmission distances and bit rates under different channel spacing. Furthermore, the system is evaluated in terms of minimum Bit Error Rate (BER) and Quality factor (Qf) without applying any dispersion compensation technique, or any optical amplifier. Optisystem software was used for simulation purposes.

Keywords: Bit Error Rate, BER, Carrier Suppressed Return to Zero, CSRZ, Duo Binary, DB, Differential Quadrature Phase Shift Keying, DQPSK, Modified Duo Binary, MODB, On-Off Keying Non-Return-to-Zero, NRZ-OOK, Quality factor, Qf, Time and Wavelength Division Multiplexing Passive Optical Network, TWDM-PON.

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Authors: Jung-Chuan Chou, Cheng-Wei Chen

Abstract:

The hard clam (meretrix lusoria) cultivated industry has been developed vigorously for recent years in Taiwan, and seawater quality determines the cultivated environment. The pH concentration variation affects survival rate of meretrix lusoria immediately. In order to monitor seawater quality, solid-state sensing electrode of ruthenium-doped titanium dioxide (TiO2:Ru) is developed to measure hydrogen ion concentration in different cultivated solutions. Because the TiO2:Ru sensing electrode has high chemical stability and superior sensing characteristics, thus it is applied as a pH sensor. Response voltages of TiO2:Ru sensing electrode are readout by instrument amplifier in different sample solutions. Mean sensitivity and linearity of TiO2:Ru sensing electrode are 55.20 mV/pH and 0.999 from pH1 to pH13, respectively. We expect that the TiO2:Ru sensing electrode can be applied to real environment measurement, therefore we collect two sample solutions by different meretrix lusoria cultivated ponds in the Yunlin, Taiwan. The two sample solutions are both measured for 200 seconds after calibration of standard pH buffer solutions (pH7, pH8 and pH 9). Mean response voltages of sample 1 and sample 2 are -178.758 mV (Standard deviation=0.427 mV) and -180.206 mV (Standard deviation =0.399 mV), respectively. Response voltages of the two sample solutions are between pH 8 and pH 9 which conform to weak alkali range and suitable meretrix lusoria growth. For long-term monitoring, drift of cultivated solutions (sample 1 and sample 2) are 1.16 mV/hour and 1.03 mV/hour, respectively.

Keywords: Co-sputtering system, Hard clam (meretrix lusoria), Ruthenium-doped titanium dioxide, Solid-state sensing electrode.

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Authors: Yi-Feng Su, Chia-Tseng Chen, Hsueh-Lung Liao

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The objective of this research is to develop an advanced driver assistance system characterized with the functions of lane departure warning (LDW), forward collision warning (FCW) and adaptive front-lighting system (AFS). The system is mainly configured a CCD/CMOS camera to acquire the images of roadway ahead in association with the analysis made by an image-processing unit concerning the lane ahead and the preceding vehicles. The input image captured by a camera is used to recognize the lane and the preceding vehicle positions by image detection and DROI (Dynamic Range of Interesting) algorithms. Therefore, the system is able to issue real-time auditory and visual outputs of warning when a driver is departing the lane or driving too close to approach the preceding vehicle unwittingly so that the danger could be prevented from occurring. During the nighttime, in addition to the foregoing warning functions, the system is able to control the bending light of headlamp to provide an immediate light illumination when making a turn at a curved lane and adjust the level automatically to reduce the lighting interference against the oncoming vehicles driving in the opposite direction by the curvature of lane and the vanishing point estimations. The experimental results show that the integrated vehicle image system is robust to most environments such as the lane detection and preceding vehicle detection average accuracy performances are both above 90 %.

Keywords: Lane mark detection, lane departure warning (LDW), dynamic range of interesting (DROI), forward collision warning (FCW), adaptive front-lighting system (AFS).

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Authors: Padmanabhan Balasubramanian, Ryuta Arisaka

Abstract:

Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.

Keywords: Factorization, Set theory, Logic function, Standardcell based design, Low power.

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Authors: Syahril Ridzuan Ab Rahim, Ibrahim Ahmad, Mohd Azizi Chik, Ahmad Zafir Md. Rejab, and U. Hashim

Abstract:

This research presents the development of simulation modeling for WIP management in semiconductor fabrication. Manufacturing simulation modeling is needed for productivity optimization analysis due to the complex process flows involved more than 35 percent re-entrance processing steps more than 15 times at same equipment. Furthermore, semiconductor fabrication required to produce high product mixed with total processing steps varies from 300 to 800 steps and cycle time between 30 to 70 days. Besides the complexity, expansive wafer cost that potentially impact the company profits margin once miss due date is another motivation to explore options to experiment any analysis using simulation modeling. In this paper, the simulation model is developed using existing commercial software platform AutoSched AP, with customized integration with Manufacturing Execution Systems (MES) and Advanced Productivity Family (APF) for data collections used to configure the model parameters and data source. Model parameters such as processing steps cycle time, equipment performance, handling time, efficiency of operator are collected through this customization. Once the parameters are validated, few customizations are made to ensure the prior model is executed. The accuracy for the simulation model is validated with the actual output per day for all equipments. The comparison analysis from result of the simulation model compared to actual for achieved 95 percent accuracy for 30 days. This model later was used to perform various what if analysis to understand impacts on cycle time and overall output. By using this simulation model, complex manufacturing environment like semiconductor fabrication (fab) now have alternative source of validation for any new requirements impact analysis.

Keywords: Advanced Productivity Family (APF), Complementary Metal Oxide Semiconductor (CMOS), Manufacturing Execution Systems (MES), Work In Progress (WIP).

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Authors: Padmanabhan Balasubramanian, C. Hari Narayanan

Abstract:

This paper discusses a new, systematic approach to the synthesis of a NP-hard class of non-regenerative Boolean networks, described by FON[FOFF]={mi}[{Mi}], where for every mj[Mj]∈{mi}[{Mi}], there exists another mk[Mk]∈{mi}[{Mi}], such that their Hamming distance HD(mj, mk)=HD(Mj, Mk)=O(n), (where 'n' represents the number of distinct primary inputs). The method automatically ensures exact minimization for certain important selfdual functions with 2n-1 points in its one-set. The elements meant for grouping are determined from a newly proposed weighted incidence matrix. Then the binary value corresponding to the candidate pair is correlated with the proposed binary value matrix to enable direct synthesis. We recommend algebraic factorization operations as a post processing step to enable reduction in literal count. The algorithm can be implemented in any high level language and achieves best cost optimization for the problem dealt with, irrespective of the number of inputs. For other cases, the method is iterated to subsequently reduce it to a problem of O(n-1), O(n-2),.... and then solved. In addition, it leads to optimal results for problems exhibiting higher degree of adjacency, with a different interpretation of the heuristic, and the results are comparable with other methods. In terms of literal cost, at the technology independent stage, the circuits synthesized using our algorithm enabled net savings over AOI (AND-OR-Invert) logic, AND-EXOR logic (EXOR Sum-of- Products or ESOP forms) and AND-OR-EXOR logic by 45.57%, 41.78% and 41.78% respectively for the various problems. Circuit level simulations were performed for a wide variety of case studies at 3.3V and 2.5V supply to validate the performance of the proposed method and the quality of the resulting synthesized circuits at two different voltage corners. Power estimation was carried out for a 0.35micron TSMC CMOS process technology. In comparison with AOI logic, the proposed method enabled mean savings in power by 42.46%. With respect to AND-EXOR logic, the proposed method yielded power savings to the tune of 31.88%, while in comparison with AND-OR-EXOR level networks; average power savings of 33.23% was obtained.

Keywords: AOI logic, ESOP, AND-OR-EXOR, Incidencematrix, Hamming distance.

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Authors: Naoto Suzuki

Abstract:

A decline in visual sensitivity at arbitrary points on the retina can be measured using a precise perimetry apparatus along with a fundus camera. However, the retinal layer associated with this decline cannot be identified accurately with current medical technology. To investigate cryptogenic diseases, such as macular dystrophy, acute zonal occult outer retinopathy (AZOOR), and multiple evanescent white dot syndrome (MEWDS), we evaluated an electroretinogram (ERG) function that allows moving the center of the multifocal hexagonal stimulus array to a chosen position. Macular dystrophy is a generalized term used for a variety of functional disorders of the macula lutea, and the ERG shows a diminution of the b-wave in these disorders. AZOOR causes an acute functional disorder to an outer layer of the retina, and the ERG shows a-wave and b-wave amplitude reduction as well as delayed 30 Hz flicker responses. MEWDS causes acute visual loss and the ERG shows a decrease in a-wave amplitude. We combined an electroretinographic optical system and a perimetric optical system into an experimental apparatus that has the same optical system as that of a fundus camera. We also deployed an EO-50231 Edmund infrared camera, a 45-degree cold mirror, a lens with a 25-mm focal length, a halogen lamp, and an 8-inch monitor. Then, we also employed a differential amplifier with gain 10, a 50 Hz notch filter, a high-pass filter with a 21.2 Hz cut-off frequency, and two non-inverting amplifiers with gains 1001 and 11. In addition, we used a USB-6216 National Instruments I/O device, a NE-113A Nihon Kohden plate electrode, a SCB-68A shielded connector block, and LabVIEW 2017 software for data retrieval. The software was used to generate the multifocal hexagonal stimulus array on the computer monitor with C++Builder 10.2 and to move the center of the array toward the left and right and up and down. Cone and bright flash ERG results were observed using the moving ERG function. The a-wave, b-wave, c-wave, and the photopic negative response were identified with cone ERG. The moving ERG function allowed the identification of the retinal layer causing visual alterations.

Keywords: Moving ERG, multifocal ERG, precise perimetry, retinal layers, visual sensitivity

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