Search results for: Hardware

Authors: Faisal Amin, Abdul Mueed, Xu Jiadong

Abstract:

This paper describes the development of a fully automated measurement software for antenna radiation pattern measurements in a Compact Antenna Test Range (CATR). The CATR has a frequency range from 2-40 GHz and the measurement hardware includes a Network Analyzer for transmitting and Receiving the microwave signal and a Positioner controller to control the motion of the Styrofoam column. The measurement process includes Calibration of CATR with a Standard Gain Horn (SGH) antenna followed by Gain versus angle measurement of the Antenna under test (AUT). The software is designed to control a variety of microwave transmitter / receiver and two axis Positioner controllers through the standard General Purpose interface bus (GPIB) interface. Addition of new Network Analyzers is supported through a slight modification of hardware control module. Time-domain gating is implemented to remove the unwanted signals and get the isolated response of AUT. The gated response of the AUT is compared with the calibration data in the frequency domain to obtain the desired results. The data acquisition and processing is implemented in Agilent VEE and Matlab. A variety of experimental measurements with SGH antennas were performed to validate the accuracy of software. A comparison of results with existing commercial softwares is presented and the measured results are found to be within .2 dBm.

Keywords: Antenna measurement, calibration, time-domain gating, VNA, Positioner controller

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Authors: N. Muthukumaran, R. Ravi

Abstract:

The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

Keywords: Image compression, Pixel, Compression Ratio, Adjusted Binary code, Golumb Rice code, High Definition display, VLSI Implementation.

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Authors: Shiji Hu, Lei Li, Wanting Zhou, Daohong Yang

Abstract:

The data encryption is the foundation of today’s communication. On this basis, to improve the speed of data encryption and decryption is always an important goal for high-speed applications. This paper proposed an elliptic curve crypto processor architecture based on SM2 prime field. Regarding hardware implementation, we optimized the algorithms in different stages of the structure. For modulo operation on finite field, we proposed an optimized improvement of the Karatsuba-Ofman multiplication algorithm and shortened the critical path through the pipeline structure in the algorithm implementation. Based on SM2 recommended prime field, a fast modular reduction algorithm is used to reduce 512-bit data obtained from the multiplication unit. The radix-4 extended Euclidean algorithm was used to realize the conversion between the affine coordinate system and the Jacobi projective coordinate system. In the parallel scheduling point operations on elliptic curves, we proposed a three-level parallel structure of point addition and point double based on the Jacobian projective coordinate system. Combined with the scalar multiplication algorithm, we added mutual pre-operation to the point addition and double point operation to improve the efficiency of the scalar point multiplication. The proposed ECC hardware architecture was verified and implemented on Xilinx Virtex-7 and ZYNQ-7 platforms, and each 256-bit scalar multiplication operation took 0.275ms. The performance for handling scalar multiplication is 32 times that of CPU (dual-core ARM Cortex-A9).

Keywords: Elliptic curve cryptosystems, SM2, modular multiplication, point multiplication.

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Authors: Arne Koschel, Irina Astrova, Elena Deutschkämer, Jacob Ester, Johannes Feldmann

Abstract:

In this paper various techniques in relation to large-scale systems are presented. At first, explanation of large-scale systems and differences from traditional systems are given. Next, possible specifications and requirements on hardware and software are listed. Finally, examples of large-scale systems are presented.

Keywords: Distributed file systems, cashing, large scale systems, MapReduce algorithm, NoSQL databases.

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Authors: Amin Chegenizadeh, Hamid Nikraz

Abstract:

The use of computer hardware and software in education and training dates to the early 1940s, when American researchers developed flight simulators which used analog computers to generate simulated onboard instrument data.Computer software is widely used to help engineers and undergraduate student solve their problems quickly and more accurately. This paper presents the list of computer software in geotechnical engineering.

Keywords: Geotechnical, Teaching, Courseware

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Authors: Rangsipan Marukatat, Pongmanat Manaspaibool, Benjawan Khaiprapay, Pornpimon Plienjai

Abstract:

We developed a GPS-based navigation device for the blind, with audio guidance in Thai language. The device is composed of simple and inexpensive hardware components. Its user interface is quite simple. It determines optimal routes to various landmarks in our university campus by using heuristic search for the next waypoints. We tested the device and made note of its limitations and possible extensions.

Keywords: Blind, global positioning system (GPS), navigation

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Authors: V.K.Ananthashayana, Geetha.K.S

Abstract:

In this paper, a recursive algorithm for the computation of 2-D DCT using Ramanujan Numbers is proposed. With this algorithm, the floating-point multiplication is completely eliminated and hence the multiplierless algorithm can be implemented using shifts and additions only. The orthogonality of the recursive kernel is well maintained through matrix factorization to reduce the computational complexity. The inherent parallel structure yields simpler programming and hardware implementation and provides log 1 2 3 2 N N-N+ additions and N N 2 log 2 shifts which is very much less complex when compared to other recent multiplierless algorithms.

Keywords: DCT, Multilplerless, Ramanujan Number, Recursive.

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Authors: Suguru Ochiai, Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama

Abstract:

In this paper, we propose a Connect6 solver which adopts a hybrid approach based on a tree-search algorithm and image processing techniques. The solver must deal with the complicated computation and provide high performance in order to make real-time decisions. The proposed approach enables the solver to be implemented on a single Spartan-6 XC6SLX45 FPGA produced by XILINX without using any external devices. The compact implementation is achieved through image processing techniques to optimize a tree-search algorithm of the Connect6 game. The tree search is widely used in computer games and the optimal search brings the best move in every turn of a computer game. Thus, many tree-search algorithms such as Minimax algorithm and artificial intelligence approaches have been widely proposed in this field. However, there is one fundamental problem in this area; the computation time increases rapidly in response to the growth of the game tree. It means the larger the game tree is, the bigger the circuit size is because of their highly parallel computation characteristics. Here, this paper aims to reduce the size of a Connect6 game tree using image processing techniques and its position symmetric property. The proposed solver is composed of four computational modules: a two-dimensional checkmate strategy checker, a template matching module, a skilful-line predictor, and a next-move selector. These modules work well together in selecting next moves from some candidates and the total amount of their circuits is small. The details of the hardware design for an FPGA implementation are described and the performance of this design is also shown in this paper.

Keywords: Connect6, pattern matching, game-tree reduction, hardware direct computation

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Authors: Galeano R. Katherine, Rincon L. David, Luengas C. Lely

Abstract:

This paper describes the development of an electronic instrument that looks like a flute, which is able to sense the basic musical notes being executed by a specific user. The principal function of the instrument is to teach how to play a flute. This device will generate a significant academic impact, in a field of virtual reality interactive that combine art and technology. With this example is expected to contribute in research and implementation of teaching devices around the world.

Keywords: Flute, Hardware, Learning, Virtual Reality.

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Authors: Ibrahim A. Khorwat, Nabil Naas

Abstract:

In this paper, we present a simple circuit for Manchester decoding and without using any complicated or programmable devices. This circuit can decode 90kbps of transmitted encoded data; however, greater than this transmission rate can be decoded if high speed devices were used. We also present a new method for extracting the embedded clock from Manchester data in order to use it for serial-to-parallel conversion. All of our experimental measurements have been done using simulation.

Keywords: High threshold level, level segregation, lowthreshold level, smoothing circuit synchronization..

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Authors: Moe Moe Htun, Khin Htar Nwe

Abstract:

In this paper, parallel interface for microprocessor trainer was implemented. A programmable parallel–port device such as the IC 8255A is initialized for simple input or output and for handshake input or output by choosing kinds of modes. The hardware connections and the programs can be used to interface microprocessor trainer and a personal computer by using IC 8255A. The assembly programs edited on PC-s editor can be downloaded to the trainer.

Keywords: Parallel I/O ports, parallel interface, trainer, two 8255 ICs.

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Authors: David L. Olson, Stephen B. H. Bruder, Adam S. Watkins, Cleon E. Davis

Abstract:

In global navigation satellite system (GNSS) denied settings, such as indoor environments, autonomous mobile robots are often limited to dead-reckoning navigation techniques to determine their position, velocity, and attitude (PVA). Localization is typically accomplished by employing an inertial measurement unit (IMU), which, while precise in nature, accumulates errors rapidly and severely degrades the localization solution. Standard sensor fusion methods, such as Kalman filtering, aim to fuse precise IMU measurements with accurate aiding sensors to establish a precise and accurate solution. In indoor environments, where GNSS and no other a priori information is known about the environment, effective sensor fusion is difficult to achieve, as accurate aiding sensor choices are sparse. However, an opportunity arises by employing a depth camera in the indoor environment. A depth camera can capture point clouds of the surrounding floors and walls. Extracting attitude from these surfaces can serve as an accurate aiding source, which directly combats errors that arise due to gyroscope imperfections. This configuration for sensor fusion leads to a dramatic reduction of PVA error compared to traditional aiding sensor configurations. This paper provides the theoretical basis for the depth camera aiding sensor method, initial expectations of performance benefit via simulation, and hardware implementation thus verifying its veracity. Hardware implementation is performed on the Quanser Qbot 2™ mobile robot, with a Vector-Nav VN-200™ IMU and Kinect™ camera from Microsoft.

Keywords: Autonomous mobile robotics, dead reckoning, depth camera, inertial navigation, Kalman filtering, localization, sensor fusion.

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Authors: Qiuyu Dai, Haochong Zhang, Xiangrong Liu

Abstract:

Efficient matrix-vector multiplication with diagonal sparse matrices is pivotal in a multitude of computational domains, ranging from scientific simulations to machine learning workloads. When encoded in the conventional Diagonal (DIA) format, these matrices often induce computational overheads due to extensive zero-padding and non-linear memory accesses, which can hamper the computational throughput, and elevate the usage of precious compute and memory resources beyond necessity. The ’DIA-Adaptive’ approach, a methodological enhancement introduced in this paper, confronts these challenges head-on by leveraging the advanced parallel instruction sets embedded within Machine Learning Units (MLUs). This research presents a thorough analysis of the DIA-Adaptive scheme’s efficacy in optimizing Sparse Matrix-Vector Multiplication (SpMV) operations. The scope of the evaluation extends to a variety of hardware architectures, examining the repercussions of distinct thread allocation strategies and cluster configurations across multiple storage formats. A dedicated computational kernel, intrinsic to the DIA-Adaptive approach, has been meticulously developed to synchronize with the nuanced performance characteristics of MLUs. Empirical results, derived from rigorous experimentation, reveal that the DIA-Adaptive methodology not only diminishes the performance bottlenecks associated with the DIA format but also exhibits pronounced enhancements in execution speed and resource utilization. The analysis delineates a marked improvement in parallelism, showcasing the DIA-Adaptive scheme’s ability to adeptly manage the interplay between storage formats, hardware capabilities, and algorithmic design. The findings suggest that this approach could set a precedent for accelerating SpMV tasks, thereby contributing significantly to the broader domain of high-performance computing and data-intensive applications.

Keywords: Adaptive method, DIA, diagonal sparse matrices, MLU, sparse matrix-vector multiplication.

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Authors: Andrea Gelmini

Abstract:

This paper considers the advent of 5G and the use of it in a Based Control System (BCS), posing as a basic concept the question of what the real differences and practical improvements are compared to 4G. To this purpose, a testbed hardware simulator has been designed and built where identical machines with the same sensors and management systems will communicate with different radio access network connections. This allows an objective statistical comparison of performance on the real functioning and improvement of the infrastructure with the Industrial Internet of Things (IIoT) connected to it.

Keywords: 4G, 5G, BCS, eSIM, IIoT, SCADA, Testbed.

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Authors: Essam Al-Daoud

Abstract:

A potentially serious problem with current payment systems is that their underlying hard problems from number theory may be solved by either a quantum computer or unanticipated future advances in algorithms and hardware. A new quantum payment system is proposed in this paper. The suggested system makes use of fundamental principles of quantum mechanics to ensure the unconditional security without prior arrangements between customers and vendors. More specifically, the new system uses Greenberger-Home-Zeilinger (GHZ) states and Quantum Key Distribution to authenticate the vendors and guarantee the transaction integrity.

Keywords: Bell state, GHZ state, Quantum key distribution, Quantum payment system.

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Authors: Mahdi Masoumi, Mehrdad Ardebilipoor, Seyed Aidin Bassam

Abstract:

This paper proposes a novel frequency offset (FO) estimator for orthogonal frequency division multiplexing. Simplicity is most significant feature of this algorithm and can be repeated to achieve acceptable accuracy. Also fractional and integer part of FO is estimated jointly with use of the same algorithm. To do so, instead of using conventional algorithms that usually use correlation function, we use DFT of received signal. Therefore, complexity will be reduced and we can do synchronization procedure by the same hardware that is used to demodulate OFDM symbol. Finally, computer simulation shows that the accuracy of this method is better than other conventional methods.

Keywords: DFT, Estimator, Frequency Offset, IEEE802.11a, OFDM.

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Authors: Qinyi Mei, Li-Ping Wang

Abstract:

MDS matrices are of great significance in the design of block ciphers and hash functions. In the present paper, we investigate the problem of constructing MDS matrices which are both lightweight and low-latency. We propose a new method of constructing lightweight MDS matrices using circulant matrices which can be implemented efficiently in hardware. Furthermore, we provide circulant MDS matrices with as few bit XOR operations as possible for the classical dimensions 4 × 4, 8 × 8 over the space of linear transformations over finite field F42 . In contrast to previous constructions of MDS matrices, our constructions have achieved fewer XORs.

Keywords: Linear diffusion layer, circulant matrix, lightweight, MDS matrix.

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Authors: Kyu Han Kim, Soon Kyu Kwon, Heung Sun Yoon, Jong Tae Kim

Abstract:

In this paper, we demonstrate the adaptive least-mean-square (LMS) filter modeling using SystemC. SystemC is a modeling language that allows designer to model both hardware and software component and makes it possible to design from high level system of abstraction to low level system of abstraction. We produced five adaptive least-mean-square filter models that are classed as five abstraction levels using SystemC proceeding from the abstract model to the more concrete model.

Keywords: Adaptive Filter, Least-Mean-Square Algorithm, SystemC, Transversal Fir Filter.

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Authors: Ahmad Ghayoumi, Mehdi Ghayoumi

Abstract:

Intelligent schools are those which use IT devices and technologies as media software, hardware and networks to improve learning process. On the other hand management improvement is best described as the process from which managers learn and improve their skills not only to benefit themselves but also their employing organizations Here, we present a model Management improvement System that has been applied on some schools and have made strict improvement.

Keywords: Intelligent school, Management development system, Learning station, Teaching station

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Authors: Ahmad Ghayoumi, Mehdi Ghayoumi

Abstract:

Intelligent schools are those which use IT devices and technologies as media software, hardware and networks to improve learning process. On the other hand Strategic management is a field that deals with the major intended and emergent initiatives taken by general managers on behalf of owners, involving utilization of resources, to enhance the performance of firms in their external environments. Here, we present a model Strategic Management System that has been applied on some schools and have made strict improvement.

Keywords: Intelligent school, Strategic management system, Learning station, Teaching station

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Authors: Myat Su Mon Win

Abstract:

The pseudorandom number generators based on linear feedback shift registers (LFSRs), are very quick, easy and secure in the implementation of hardware and software. Thus they are very popular and widely used. But LFSRs lead to fairly easy cryptanalysis due to their completely linearity properties. In this paper, we propose a stochastic generator, which is called Random Feedback Shift Register (RFSR), using stochastic transformation (Random block) with one-way and non-linearity properties.

Keywords: Linear Feedback Shift Register, Non Linearity, R_Block, Random Feedback Shift Register

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Authors: Kyu-Yeul Wang, Sang-Seol Lee, Jea-Yeon Song, Jea-Young Choi, Seong-Seob Shin, Dong-Sun Kim, Duck-Jin Chung

Abstract:

In this paper, we propose the low-MAC FEC controller for practical implementation of JPEG2000 image transmission using IEEE 802.15.4. The proposed low-MAC FEC controller has very small HW size and spends little computation to estimate channel state. Because of this advantage, it is acceptable to apply IEEE 802.15.4 which has to operate more than 1 year with battery. For the image transmission, we integrate the low-MAC FEC controller and RCPC coder in sensor node of LR-WPAN. The modified sensor node has increase of 3% hardware size than conventional zigbee sensor node.

Keywords: FEC, IEEE 802.15.4, JPEG2000, low-MAC.

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Authors: Yanting Cao, Kazumitsu Nawata

Abstract:

As smartphones are continually upgrading, their software and hardware are getting smarter, so the smartphone-based human activity recognition will be described more refined, complex and detailed. In this context, we analyzed a set of experimental data, obtained by observing and measuring 30 volunteers with six activities of daily living (ADL). Due to the large sample size, especially a 561-feature vector with time and frequency domain variables, cleaning these intractable features and training a proper model become extremely challenging. After a series of feature selection and parameters adjustments, a well-performed SVM classifier has been trained. 

Keywords: smart sensors, human activity recognition, artificial intelligence, SVM

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Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: Galeano R. Katherine, Rincon L. David, Luengas. Lely, Guevara. Juan Carlos

Abstract:

The following paper shows an interactive tool which main purpose is to teach how to play a flute. It consists of three stages the first one is the instruction and teaching process through a software application, the second is the practice part when the user starts to play the flute (hardware specially designed for this application) this flute is capable of capturing how is being played the flute and the final stage is the one in which the data captured are sent to the software and the user is evaluated in order to give him / she a correction or an acceptance

Keywords: acoustoelectric devices, computer applications, learning systems, music, technological innovation, virtual reality

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Authors: Christian Mayr, Matthias Ehrlich, Stephan Henker, Karsten Wendt, René Schüffny

Abstract:

Traditionally, VLSI implementations of spiking neural nets have featured large neuron counts for fixed computations or small exploratory, configurable nets. This paper presents the system architecture of a large configurable neural net system employing a dedicated mapping algorithm for projecting the targeted biology-analog nets and dynamics onto the hardware with its attendant constraints.

Keywords: Large scale VLSI neural net, topology mapping, complex pulse communication.

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Authors: Edward Paul Guillen, Diego Alejandro Chacon

Abstract:

The VoIP networks as alternative method to traditional PSTN system has been implemented in a wide variety of structures with multiple protocols, codecs, software and hardware–based distributions. The use of cryptographic techniques let the users to have a secure communication, but the calculate throughput as well as the QoS parameters are affected according to the used algorithm. This paper analyzes the VoIP throughput and the QoS parameters with different commercial encryption methods. The measurement–based approach uses lab scenarios to simulate LAN and WAN environments. Security mechanisms such as TLS, SIAX2, SRTP, IPSEC and ZRTP are analyzed with μ-LAW and GSM codecs.

Keywords: VoIP, Secure VoIP, Throughput Analysis, VoIP QoS evaluation

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Authors: Kaiwan S. Ismael, Ergun Ercelebi, Majeed Nader

Abstract:

This paper describes the design and implementation of a hardware setup for online monitoring of 24 refrigerators inside blood bank center using the microcontroller and CAN bus for communications between each node. Due to the security of locations in the blood bank hall and difficulty of monitoring of each refrigerator separately, this work proposes a solution to monitor all the blood bank refrigerators in one location. CAN-bus system is used because it has many applications and advantages, especially for this system due to easy in use, low cost, providing a reduction in wiring, fast to repair and easily expanding the project without a problem.

Keywords: Control Area Network (CAN), monitoring blood bank center, PIC microcontroller, MPLAB IDE.

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Authors: Ghada Abdelmouez M., Fathy S. Helail, Abdellatif A. Elkouny

Abstract:

It is known that symmetric encryption algorithms are fast and easy to implement in hardware. Also elliptic curves have proved to be a good choice for building encryption system. Although most of the symmetric systems have been broken, we can create a hybrid system that has the same properties of the symmetric encryption systems and in the same time, it has the strength of elliptic curves in encryption. As DES algorithm is considered the core of all successive symmetric encryption systems, we modified DES using elliptic curves and built a new DES algorithm that is hard to be broken and will be the core for all other symmetric systems.

Keywords: DES, Elliptic Curves, hybrid system, symmetricencryption.

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Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: Local interconnect network, controller, transceiver, processor.

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