Search results for: cross-layer architectures

Authors: Akhilesh G. Naik, Dipankar Pal

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In today’s scenario, the complexity of digital signal processing (DSP) applications and various microcontroller architectures have been increasing to such an extent that the traditional approaches to multiplier design in most processors are becoming outdated for being comparatively slow. Modern processing applications require suitable pipelined approaches, and therefore, algorithms that are friendlier with pipelined architectures. Traditional algorithms like Wallace Tree, Radix-4 Booth, Radix-8 Booth, Dadda architectures have been proven to be comparatively slow for pipelined architectures. These architectures, therefore, need to be optimized or combined with other architectures amongst them to enhance its performances and to be made suitable for pipelined hardware/architectures. Recently, Vedic algorithm mathematically has proven to be efficient by appearing to be less complex and with fewer steps for its output establishment and have assumed renewed importance. This paper describes and shows how the Vedic algorithm can be better suited for pipelined architectures and also can be combined with traditional architectures and algorithms for enhancing its ability even further. In this paper, we also established that for complex applications on DSP and other microcontroller architectures, using Vedic approach for multiplication proves to be the best available and efficient option.

Keywords: Wallace tree, Radix-4 Booth, Radix-8 Booth, Dadda, Vedic, Single-Stage Karatsuba, Looped Karatsuba.

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Authors: A. Schuster

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Many artificial intelligence (AI) techniques are inspired by problem-solving strategies found in nature. Robustness is a key feature in many natural systems. This paper studies robustness in artificial neural networks (ANNs) and proposes several novel, nature inspired ANN architectures. The paper includes encouraging results from experimental studies on these networks showing increased robustness.

Keywords: robustness, robust artificial neural networks architectures.

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Authors: Y. Lacroix, J.-F. Malbranque

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We present a chronological evolution for naval telecommunication networks. We distinguish periods: with or without multiplexers, with switch systems, with federative systems, with medium switching, and with medium switching with wireless networks. This highlights the introduction of new layers and technology in the architecture. These architectures are presented using layer models of transmission, in a unified way, which enables us to integrate pre-existing models. A ship of a naval fleet has internal communications (i.e. applications' networks of the edge) and external communications (i.e. the use of the means of transmission between edges). We propose architectures, deduced from the layer model, which are the point of convergence between the networks on board and the HF, UHF radio, and satellite resources. This modelling allows to consider end-to-end naval communications, and in a more global way, that is from the user on board towards the user on shore, including transmission and networks on the shore side. The new architectures need take care of quality of services for end-to-end communications, the more remote control develops a lot and will do so in the future. Naval telecommunications will be more and more complex and will use more and more advanced technologies, it will thus be necessary to establish clear global communication schemes to grant consistency of the architectures. Our latest model has been implemented in a military naval situation, and serves as the basic architecture for the RIFAN2 network.

Keywords: Equilibrium beach profile, eastern tombolo of Giens, potential function, erosion.

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Authors: Manoj Kumar Dutta

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Wavelength Division Multiplexing (WDM) technology is the most promising technology for the proper utilization of huge raw bandwidth provided by an optical fiber. One of the key problems in implementing the all-optical WDM network is the packet contention. This problem can be solved by several different techniques. In time domain approach the packet contention can be reduced by incorporating Fiber Delay Lines (FDLs) as optical buffer in the switch architecture. Different types of buffering architectures are reported in literatures. In the present paper a comparative performance analysis of three most popular FDL architectures are presented in order to obtain the best contention resolution performance. The analysis is further extended to consider the effect of different fiber non-linearities on the network performance.

Keywords: WDM network, contention resolution, optical buffering, non-linearity, throughput.

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Authors: Pham Thanh Trung, Huynh Quyet Thang

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Reliability is one of the most important quality attributes of software. Based on the approach of Reussner and the approach of Cheung, we proposed the reliability prediction model of component-based software architectures. Also, the value of the model is shown through the experimental evaluation on a web server system.

Keywords: component-based architecture, reliability prediction model, software reliability engineering.

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Authors: João Paulo Teixeira, Paula Odete Fernandes

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The authors have been developing several models based on artificial neural networks, linear regression models, Box- Jenkins methodology and ARIMA models to predict the time series of tourism. The time series consist in the “Monthly Number of Guest Nights in the Hotels" of one region. Several comparisons between the different type models have been experimented as well as the features used at the entrance of the models. The Artificial Neural Network (ANN) models have always had their performance at the top of the best models. Usually the feed-forward architecture was used due to their huge application and results. In this paper the author made a comparison between different architectures of the ANNs using simply the same input. Therefore, the traditional feed-forward architecture, the cascade forwards, a recurrent Elman architecture and a radial based architecture were discussed and compared based on the task of predicting the mentioned time series.

Keywords: Artificial Neural Network Architectures, time series forecast, tourism.

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Authors: Augustine C. Azubogu, Victor E. Idigo, Schola U. Nnebe, Obinna S. Oguejiofor, Simon E.

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The main goal of this seminal paper is to introduce the application of Wireless Sensor Networks (WSN) in long distance infrastructure monitoring (in particular in pipeline infrastructure monitoring) – one of the on-going research projects by the Wireless Communication Research Group at the department of Electronic and Computer Engineering, Nnamdi Azikiwe University, Awka. The current sensor network architectures for monitoring long distance pipeline infrastructures are previewed. These are wired sensor networks, RF wireless sensor networks, integrated wired and wireless sensor networks. The reliability of these architectures is discussed. Three reliability factors are used to compare the architectures in terms of network connectivity, continuity of power supply for the network, and the maintainability of the network. The constraints and challenges of wireless sensor networks for monitoring and protecting long distance pipeline infrastructure are discussed.

Keywords: Connectivity, maintainability, reliability, wireless sensor networks.

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Authors: Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh

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The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.

Keywords: MinRoot, CMesh, NoC, Topology, Performance Evaluation

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Authors: K. Krishna Naik, M. N. Giri Prasad

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These days wireless local area networks has become very popular, when the initial IEEE802.11 is the standard for providing wireless connectivity to automatic machinery, equipment and stations that require rapid deployment, which may be portable, handheld or which may be mounted on moving vehicles within a local area. IEEE802.11 Wireless local area network is a sharedmedium communication network that transmits information over wireless links for all IEEE802.11 stations in its transmission range to receive. When a user is moving from one location to another, how the other user knows about the required station inside WLAN. For that we designed and implemented a system to locate a mobile user inside the wireless local area network based on RSSI with the help of four specially designed architectures. These architectures are based on statistical or we can say manual configuration of mapping and radio map of indoor and outdoor location with the help of available Sniffer based and cluster based techniques. We found a better location of a mobile user in WLAN. We tested this work in indoor and outdoor environments with different locations with the help of Pamvotis, a simulator for WLAN.

Keywords: AP, RSSI, RPM, WLAN.

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Authors: A. Alexandru, C. A. Alexandru, D. Coardos, E. Tudora

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Big Data (BD) is associated with a new generation of technologies and architectures which can harness the value of extremely large volumes of very varied data through real time processing and analysis. It involves changes in (1) data types, (2) accumulation speed, and (3) data volume. This paper presents the main concepts related to the BD paradigm, and introduces architectures and technologies for BD and BD sets. The integration of BD with the Hadoop Framework is also underlined. BD has attracted a lot of attention in the public sector due to the newly emerging technologies that allow the availability of network access. The volume of different types of data has exponentially increased. Some applications of BD in the public sector in Romania are briefly presented.

Keywords: Big data, big data Analytics, Hadoop framework, cloud computing.

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Authors: David Jones, Richard McWilliam, Alan Purvis

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Morphogenesis is the process that underpins the selforganised development and regeneration of biological systems. The ability to mimick morphogenesis in artificial systems has great potential for many engineering applications, including production of biological tissue, design of robust electronic systems and the co-ordination of parallel computing. Previous attempts to mimick these complex dynamics within artificial systems have relied upon the use of evolutionary algorithms that have limited their size and complexity. This paper will present some insight into the underlying dynamics of morphogenesis, then show how to, without the assistance of evolutionary algorithms, design cellular architectures that converge to complex patterns.

Keywords: Morphogenesis, regeneration, robustness, convergence, cellular automata.

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Authors: S. Ghasemi, K. Khorasani

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In this paper, the problem of fault detection and isolation in the attitude control subsystem of spacecraft formation flying is considered. In order to design the fault detection method, an extended Kalman filter is utilized which is a nonlinear stochastic state estimation method. Three fault detection architectures, namely, centralized, decentralized, and semi-decentralized are designed based on the extended Kalman filters. Moreover, the residual generation and threshold selection techniques are proposed for these architectures.

Keywords: Formation flight of satellites, extended Kalman filter, fault detection and isolation, actuator fault.

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Authors: Arne Koschel, Irina Astrova

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Heterogeneity has to be taken into account when integrating a set of existing information sources into a distributed information system that are nowadays often based on Service- Oriented Architectures (SOA). This is also particularly applicable to distributed services such as event monitoring, which are useful in the context of Event Driven Architectures (EDA) and Complex Event Processing (CEP). Web services deal with this heterogeneity at a technical level, also providing little support for event processing. Our central thesis is that such a fully generic solution cannot provide complete support for event monitoring; instead, source specific semantics such as certain event types or support for certain event monitoring techniques have to be taken into account. Our core result is the design of a configurable event monitoring (Web) service that allows us to trade genericity for the exploitation of source specific characteristics. It thus delivers results for the areas of SOA, Web services, CEP and EDA.

Keywords: ECA, CEP, SOA, and Web services.

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Authors: Masafumi Kondo, Yoichiro Sato, Kazuyuki Tashiro, Tomoyuki Yokogawa, Michiyoshi Hayase

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Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several architectures have been proposed as bus architectures for a GALS system : shared bus, segmented bus, ring bus, and so on. In this study, we propose a ring segmented bus architecture which is a combination of segmented bus and ring bus architecture with the aim of throughput enhancement. In a segmented bus architecture, segments are connected in series. By connecting the segments at the end of the bus and constructing the ring bus, it becomes possible to allocate a channel of the bus bidirectionally. The bus channel is allocated to the shortest path between segments. We consider a metastable operation caused by asynchronous communication between segments and a burst transfer between segments. According to the result of simulation, it is shown that the GALS system designed by the proposed method has the desired operations.

Keywords: GALS systems bus architecture, segmented bus, ring bus.

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Authors: Wee Leong Son, Hasmayadi Abdul Majid, Rohana Musa

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This paper study the segmented split capacitor Digital-to-Analog Converter (DAC) implemented in a differentialtype 12-bit Successive Approximation Analog-to-Digital Converter (SA-ADC). The series capacitance split array method employed as it reduced the total area of the capacitors required for high resolution DACs. A 12-bit regular binary array structure requires 2049 unit capacitors (Cs) while the split array needs 127 unit Cs. These results in the reduction of the total capacitance and power consumption of the series split array architectures as to regular binary-weighted structures. The paper will show the 12-bit DAC series split capacitor with 4-bit thermometer coded DAC architectures as well as the simulation and measured results.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Low voltage ADC.

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Authors: Zaki Ahmad Khan, Jamshed Siddiqui, Abdus Samad

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The Scheduling and mapping of tasks on a set of processors is considered as a critical problem in parallel and distributed computing system. This paper deals with the problem of dynamic scheduling on a special type of multiprocessor architecture known as Linear Crossed Cube (LCQ) network. This proposed multiprocessor is a hybrid network which combines the features of both linear types of architectures as well as cube based architectures. Two standard dynamic scheduling schemes namely Minimum Distance Scheduling (MDS) and Two Round Scheduling (TRS) schemes are implemented on the LCQ network. Parallel tasks are mapped and the imbalance of load is evaluated on different set of processors in LCQ network. The simulations results are evaluated and effort is made by means of through analysis of the results to obtain the best solution for the given network in term of load imbalance left and execution time. The other performance matrices like speedup and efficiency are also evaluated with the given dynamic algorithms.

Keywords: Dynamic algorithm, Load imbalance, Mapping, Task scheduling.

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Authors: Namugenyi Ephrance Eunice, Julianne Sansa Otim, Marco Zennaro, Stephen D. Wolthusen

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The Internet of Things (IoT) is a network of connected data processing devices, mechanical and digital machinery, items, animals, or people that may send data across a network without requiring human-to-human or human-to-computer interaction. Each component has sensors that can pick up on specific phenomena, as well as processing software and other technologies that can link to and communicate with other systems and/or devices over the Internet or other communication networks and exchange data with them. IoT is increasingly being used in fields other than consumer electronics, such as public safety, emergency response, industrial automation, autonomous vehicles, the Internet of Medical Things (IoMT), and general environmental monitoring. Consumer-based IoT applications, like smart home gadgets and wearables, are also becoming more prevalent. This paper presents the main IoT deployment areas for environmental monitoring in developing regions and the backhaul options suitable for them based on a couple of related works. The study includes an overview of existing IoT deployments, the underlying communication architectures, protocols, and technologies that support them. This overview shows that Low Power Wireless Area Networks (LPWANs) are very well suited for monitoring environment architectures designed for remote locations. LoRa technology, particularly the LoRaWAN protocol, has an advantage over other technologies due to its low power consumption, adaptability, and suitable communication range. The current challenges of various architectures are discussed in detail, with the major issue identified as obstruction of communication paths by buildings, trees, hills, etc.

Keywords: Communication technologies, environmental monitoring, Internet of Things, IoT, IoT deployment challenges.

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Authors: Rossella Arcucci, Luisa D’Amore, Simone Celestino, Giuseppe Scotti, Giuliano Laccetti

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This work is the first dowel in a rather wide research activity in collaboration with Euro Mediterranean Center for Climate Changes, aimed at introducing scalable approaches in Ocean Circulation Models. We discuss designing and implementation of a parallel algorithm for solving the Variational Data Assimilation (DA) problem on Graphics Processing Units (GPUs). The algorithm is based on the fully scalable 3DVar DA model, previously proposed by the authors, which uses a Domain Decomposition approach (we refer to this model as the DD-DA model). We proceed with an incremental porting process consisting of 3 distinct stages: requirements and source code analysis, incremental development of CUDA kernels, testing and optimization. Experiments confirm the theoretic performance analysis based on the so-called scale up factor demonstrating that the DD-DA model can be suitably mapped on GPU architectures.

Keywords: Data Assimilation, Parallel Algorithm, GPU architectures, Ocean Models.

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Authors: Brenden M. Shutt, Lubjana Beshaj, Paul L. Goethals, Ambrose Kam

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Communication security is of particular interest to military data networks. A relatively novel approach to network security is blockchain, a cryptographically secured distribution ledger with a decentralized consensus mechanism for data transaction processing. Recent advances in blockchain technology have proposed new techniques for both data validation and trust management, as well as different frameworks for managing dataflow. The purpose of this work is to test the feasibility of different blockchain architectures as applied to military command and control networks. Various architectures are tested through discrete-event simulation and the feasibility is determined based upon a blockchain design’s ability to maintain long-term stable performance at industry standards of throughput, network latency, and security. This work proposes a consortium blockchain architecture with a computationally inexpensive consensus mechanism, one that leverages a Proof-of-Identity (PoI) concept and a reputation management mechanism.

Keywords: Blockchain, command & control network, discrete-event simulation, reputation management.

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Authors: A.Muthuramalingam, S.Himavathi

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Space Vector Modulation (SVM) is an optimum Pulse Width Modulation (PWM) technique for an inverter used in a variable frequency drive applications. It is computationally rigorous and hence limits the inverter switching frequency. Increase in switching frequency can be achieved using Neural Network (NN) based SVM, implemented on application specific chips. This paper proposes a neural network based SVM technique for a Voltage Source Inverter (VSI). The network proposed is independent of switching frequency. Different architectures are investigated keeping the total number of neurons constant. The performance of the inverter is compared for various switching frequencies for different architectures of NN based SVM. From the results obtained, the network with minimum resource and appropriate word length is identified. The bit precision required for this application is identified. The network with 8-bit precision is implemented in the IC XCV 400 and the results are presented. The performance of NN based general purpose SVM with higher bit precision is discussed.

Keywords: NN based SVM, FPGA Implementation, LayerMultiplexing, NN structure and Resource Reduction, PerformanceEvaluation

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Authors: C. Paramasivam, K. B. Jayanthi

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An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 2² FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2ⁿ based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.

Keywords: Coordinate Rotational Digital Computer(CORDIC), Complex multiplier, Fast Fourier transform (FFT), Inverse fast Fourier transform (IFFT), Multipath delay Commutator (MDC), modified scaling free CORDIC, complex multiplier, pipelining, parallel processing, radix-2^2.

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Authors: M. Raciti Castelli, S. De Betta, E. Benini

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This paper presents a means for reducing the torque variation during the revolution of a vertical-axis water turbine (VAWaterT) by increasing the blade number. For this purpose, twodimensional CFD analyses have been performed on a straight-bladed Darrieus-type rotor. After describing the computational model and the relative validation procedure, a complete campaign of simulations, based on full RANS unsteady calculations, is proposed for a three, four and five-bladed rotor architectures, characterized by a NACA 0025 airfoil. For each proposed rotor configuration, flow field characteristics are investigated at several values of tip speed ratio, allowing a quantification of the influence of blade number on flow geometric features and dynamic quantities, such as rotor torque and power. Finally, torque and power curves are compared for the three analyzed architectures, achieving a quantification of the effect of blade number on overall rotor performance.

Keywords: Vertical-Axis Water Turbine, rotor solidity, CFD, NACA 0025

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Authors: K.Sedhuraman, S.Himavathi, A.Muthuramalingam

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The performance of sensor-less controlled induction motor drive depends on the accuracy of the estimated speed. Conventional estimation techniques being mathematically complex require more execution time resulting in poor dynamic response. The nonlinear mapping capability and powerful learning algorithms of neural network provides a promising alternative for on-line speed estimation. The on-line speed estimator requires the NN model to be accurate, simpler in design, structurally compact and computationally less complex to ensure faster execution and effective control in real time implementation. This in turn to a large extent depends on the type of Neural Architecture. This paper investigates three types of neural architectures for on-line speed estimation and their performance is compared in terms of accuracy, structural compactness, computational complexity and execution time. The suitable neural architecture for on-line speed estimation is identified and the promising results obtained are presented.

Keywords: Sensorless IM drives, rotor speed estimators, artificial neural network, feed- forward architecture, single neuron cascaded architecture.

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Authors: Ch. Antonopoulos, Th. Kapourniotis, V. Triantafillou

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Optimum communication and performance in Wireless Sensor Networks, constitute multi-facet challenges due to the specific networking characteristics as well as the scarce resource availability. Furthermore, it is becoming increasingly apparent that isolated layer based approaches often do not meet the demands posed by WSNs applications due to omission of critical inter-layer interactions and dependencies. As a counterpart, cross-layer is receiving high interest aiming to exploit these interactions and increase network performance. However, in order to clearly identify existing dependencies, comprehensive performance studies are required evaluating the effect of different critical network parameters on system level performance and behavior.This paper-s main objective is to address the need for multi-parametric performance evaluations considering critical network parameters using a well known network simulator, offering useful and practical conclusions and guidelines. The results reveal strong dependencies among considered parameters which can be utilized by and drive future research efforts, towards designing and implementing highly efficient protocols and architectures.

Keywords: Wireless sensor network, Communication Systems, cross-layer architectures, simulation based performance evaluation

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Authors: Nimisha R. Shirbhate, Sanjay Bokade

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Bone Scaffolds are fundamental architecture or a support structure that allows the regeneration of lost or damaged tissues and they are developed as a crucial tool in biomedical engineering. The structure of bone scaffolds plays an important role in treating bone defects. The shape of the bone scaffold performs a vital role, specifically pore size and shape, which help understand the behavior and strength of the scaffold. In this article, first, fundamental aspects of bone scaffold design are established. Second, the behavior of each architecture of the bone scaffold with biomaterials is discussed. Finally, for each structure, the stress analysis was carried out. This study aimed to design a porous and mechanically strong bone regeneration scaffold that can be successfully manufactured. Four porous architectures of the bone scaffold were designed using Rhinoceros solid modelling software. The structure model consisted of repeatable unit cells arranged in layers to fill the chosen scaffold volume. The mechanical behavior of used biocompatible material is studied with the help of ANSYS 19.2 software. It is also playing significant role to predict the strength of defined structures or 3 dimensional models.

Keywords: Bone scaffold, stress analysis, porous structure, static loading.

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Authors: Somayeh Timarchi, Keivan Navi

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Efficient modulo 2n+1 adders are important for several applications including residue number system, digital signal processors and cryptography algorithms. In this paper we present a novel modulo 2n+1 addition algorithm for a recently represented number system. The proposed approach is introduced for the reduction of the power dissipated. In a conventional modulo 2n+1 adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit circuits, the diminished-1 and carry save diminished-1 number systems can be effectively used in applications. In the paper, we also derive two new architectures for designing modulo 2n+1 adder, based on n-bit ripple-carry adder. The first architecture is a faster design whereas the second one uses less hardware. In the proposed method, the special treatment required for zero operands in Diminished-1 number system is removed. In the fastest modulo 2n+1 adders in normal binary system, there are 3-operand adders. This problem is also resolved in this paper. The proposed architectures are compared with some efficient adders based on ripple-carry adder and highspeed adder. It is shown that the hardware overhead and power consumption will be reduced. As well as power reduction, in some cases, power-delay product will be also reduced.

Keywords: Modulo 2n+1 arithmetic, residue number system, low power, ripple-carry adders.

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Authors: Alexander Goncharenko, Andrey Denisov, Sergey Alyamkin, Evgeny Terentev

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The neural network quantization is highly desired procedure to perform before running neural networks on mobile devices. Quantization without fine-tuning leads to accuracy drop of the model, whereas commonly used training with quantization is done on the full set of the labeled data and therefore is both time- and resource-consuming. Real life applications require simplification and acceleration of quantization procedure that will maintain accuracy of full-precision neural network, especially for modern mobile neural network architectures like Mobilenet-v1, MobileNet-v2 and MNAS. Here we present a method to significantly optimize training with quantization procedure by introducing the trained scale factors for discretization thresholds that are separate for each filter. Using the proposed technique, we quantize the modern mobile architectures of neural networks with the set of train data of only ∼ 10% of the total ImageNet 2012 sample. Such reduction of train dataset size and small number of trainable parameters allow to fine-tune the network for several hours while maintaining the high accuracy of quantized model (accuracy drop was less than 0.5%). Ready-for-use models and code are available in the GitHub repository.

Keywords: Distillation, machine learning, neural networks, quantization.

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Authors: Mustafa Elfituri, Jonathan Cook

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Recently, graph-based computations have become more important in large-scale scientific computing as they can provide a methodology to model many types of relations between independent objects. They are being actively used in fields as varied as biology, social networks, cybersecurity, and computer networks. At the same time, graph problems have some properties such as irregularity and poor locality that make their performance different than regular applications performance. Therefore, parallelizing graph algorithms is a hard and challenging task. Initial evidence is that standard computer architectures do not perform very well on graph algorithms. Little is known exactly what causes this. The Graph500 benchmark is a representative application for parallel graph-based computations, which have highly irregular data access and are driven more by traversing connected data than by computation. In this paper, we present results from analyzing the performance of various example implementations of Graph500, including a shared memory (OpenMP) version, a distributed (MPI) version, and a hybrid version. We measured and analyzed all the factors that affect its performance in order to identify possible changes that would improve its performance. Results are discussed in relation to what factors contribute to performance degradation.

Keywords: Graph computation, Graph500 benchmark, parallel architectures, parallel programming, workload characterization.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

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The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Siddhartha Bhattacharyya, Paramartha Dutta, Ujjwal Maulik, Prashanta Kumar Nandi

Abstract:

The paper describes a self supervised parallel self organizing neural network (PSONN) architecture for true color image segmentation. The proposed architecture is a parallel extension of the standard single self organizing neural network architecture (SONN) and comprises an input (source) layer of image information, three single self organizing neural network architectures for segmentation of the different primary color components in a color image scene and one final output (sink) layer for fusion of the segmented color component images. Responses to the different shades of color components are induced in each of the three single network architectures (meant for component level processing) by applying a multilevel version of the characteristic activation function, which maps the input color information into different shades of color components, thereby yielding a processed component color image segmented on the basis of the different shades of component colors. The number of target classes in the segmented image corresponds to the number of levels in the multilevel activation function. Since the multilevel version of the activation function exhibits several subnormal responses to the input color image scene information, the system errors of the three component network architectures are computed from some subnormal linear index of fuzziness of the component color image scenes at the individual level. Several multilevel activation functions are employed for segmentation of the input color image scene using the proposed network architecture. Results of the application of the multilevel activation functions to the PSONN architecture are reported on three real life true color images. The results are substantiated empirically with the correlation coefficients between the segmented images and the original images.

Keywords: Colour image segmentation, fuzzy set theory, multi-level activation functions, parallel self-organizing neural network.

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