Search results for: Radix-8 Booth

Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2673

Authors: Akhilesh G. Naik, Dipankar Pal

Abstract:

In today’s scenario, the complexity of digital signal processing (DSP) applications and various microcontroller architectures have been increasing to such an extent that the traditional approaches to multiplier design in most processors are becoming outdated for being comparatively slow. Modern processing applications require suitable pipelined approaches, and therefore, algorithms that are friendlier with pipelined architectures. Traditional algorithms like Wallace Tree, Radix-4 Booth, Radix-8 Booth, Dadda architectures have been proven to be comparatively slow for pipelined architectures. These architectures, therefore, need to be optimized or combined with other architectures amongst them to enhance its performances and to be made suitable for pipelined hardware/architectures. Recently, Vedic algorithm mathematically has proven to be efficient by appearing to be less complex and with fewer steps for its output establishment and have assumed renewed importance. This paper describes and shows how the Vedic algorithm can be better suited for pipelined architectures and also can be combined with traditional architectures and algorithms for enhancing its ability even further. In this paper, we also established that for complex applications on DSP and other microcontroller architectures, using Vedic approach for multiplication proves to be the best available and efficient option.

Keywords: Wallace tree, Radix-4 Booth, Radix-8 Booth, Dadda, Vedic, Single-Stage Karatsuba, Looped Karatsuba.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 776

Authors: Andrew P. Hurt, George J. Vine, Samantha E. Booth, Nichola J. Coleman

Abstract:

Silver-exchanged zeolites and clays are used in polymer composites to confer broad-spectrum antimicrobial properties on a range of functional materials. Tobermorite is a layer lattice mineral whose potential as a carrier for Ag+ ions in antibacterial composites has not yet been investigated. Accordingly, in this study, synthetic tobermorite was ion-exchanged with 10 wt% silver ions and the resulting material was incorporated into a composite film with chitosan. Chitosan is a biocompatible, biodegradable derivative of chitin, a polysaccharide obtained from the shells of crustaceans. The solvent-cast Ag+-exchanged tobermorite-chitosan films were found to exhibit antimicrobial action against Staphylococcus aureus, Escherichia coli and Pseudomonas aeruginosa.

Keywords: Antimicrobial, chitosan, silver, tobermorite.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1852

Authors: Zulhelmi Zakaria, Shuja A. Abbasi

Abstract:

A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.

Keywords: Multiplier, Vedic Mathematics, LUTs, FPGAs.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2877

Authors: Samantha E. Booth, Andrew D. Deacon, Nichola J. Coleman

Abstract:

A study has been carried out to determine the effect of coating two commercial glass-ionomer cements in either petroleum jelly or wax. After coating, specimens were stored in water for 24 or 168 hours, then the coating removed and the surface examined. Coating in wax was found to increase the surface hardness significantly compared with the uncoated control, whereas coating the specimens in petroleum jelly led to only a slight increase in surface hardness. Coating in wax led to no detectable ion release after either 24 or 168 hours, though there was some ion release after the coating had been removed and the specimens exposed to water for a further 24 hours. This shows that soluble species remained in these specimens. Overall, this study confirms the idea that immature glass-ionomers should be protected from early exposure to moisture, and that the protection offered by petroleum jelly is only modest.

Keywords: Coating, Glass-Ionomer Cements, Ion Release, Surface Hardness, Wax.

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4509