Search results for: Interconnection network

Authors: Ahmad M. Awwad, Jehad Al-Sadi

Abstract:

The star network is one of the promising interconnection networks for future high speed parallel computers, it is expected to be one of the future-generation networks. The star network is both edge and vertex symmetry, it was shown to have many gorgeous topological proprieties also it is owns hierarchical structure framework. Although much of the research work has been done on this promising network in literature, it still suffers from having enough algorithms for load balancing problem. In this paper we try to work on this issue by investigating and proposing an efficient algorithm for load balancing problem for the star network. The proposed algorithm is called Star Clustered Dimension Exchange Method SCDEM to be implemented on the star network. The proposed algorithm is based on the Clustered Dimension Exchange Method (CDEM). The SCDEM algorithm is shown to be efficient in redistributing the load balancing as evenly as possible among all nodes of different factor networks.

Keywords: Interconnection networks, Load balancing, Star network.

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Authors: Ranjan Kumar Dash, Chita Ranjan Tripathy

Abstract:

The evaluation of residual reliability of large sized parallel computer interconnection systems is not practicable with the existing methods. Under such conditions, one must go for approximation techniques which provide the upper bound and lower bound on this reliability. In this context, a new approximation method for providing bounds on residual reliability is proposed here. The proposed method is well supported by two algorithms for simulation purpose. The bounds on residual reliability of three different categories of interconnection topologies are efficiently found by using the proposed method

Keywords: Parallel computer network, reliability, probabilisticgraph, interconnection networks.

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Authors: Ekow A. Kwofie, Emmanuel K. Anto, Godfred Mensah

Abstract:

In this paper, CYME Distribution software has been used to assess the impacts of solar Photovoltaic (PV) distributed generation (DG) plant on the Electricity Company of Ghana (ECG) 33 kV sub-transmission network at different PV penetration levels. As ECG begins to encourage DG PV interconnections within its network, there has been the need to assess the impacts on the sub-transmission losses and voltage contribution. In Tema, a city in Accra - Ghana, ECG has a 33 kV sub-transmission network made up of 20 No. 33 kV buses that was modeled. Three different locations were chosen: The source bus, a bus along the sub-transmission radial network and a bus at the tail end to determine the optimal location for DG PV interconnection. The optimal location was determined based on sub-transmission technical losses and voltage impact. PV capacities at different penetration levels were modeled at each location and simulations performed to determine the optimal PV penetration level. Interconnection at a bus along (or in the middle of) the sub-transmission network offered the highest benefits at an optimal PV penetration level of 80%. At that location, the maximum voltage improvement of 0.789% on the neighboring 33 kV buses and maximum loss reduction of 6.033% over the base case scenario were recorded. Hence, the optimal location for DG PV integration within the 33 kV sub-transmission utility network is at a bus along the sub-transmission radial network.

Keywords: Distributed generation photovoltaic, DG PV, optimal location, penetration level, sub-transmission network.

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Authors: Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis

Abstract:

Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.

Keywords: Design Methodology, FPGA, Interconnection, Low-Energy, High-Performance, CAD tool.

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Authors: Raed A. Amro

Abstract:

Standard packaging and interconnection technologies of power devices have difficulties meeting the increasing thermal demands of new application fields of power electronics devices. Main restrictions are the decreasing reliability of bond-wires and solder layers with increasing junction temperature. In the last few years intensive efforts have been invested in developing new packaging and interconnection solutions which may open a path to future application of power devices. In this paper, the main failure mechanisms of power devices are described and principle of new packaging and interconnection concepts and their power cycling reliability are presented.

Keywords: Power electronics devices, Reliability, Power Cycling, Low-temperature joining technique (LTJT)

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

Abstract:

Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: Qimin Yang

Abstract:

In this paper, 3X3 routing nodes are proposed to provide speedup and parallel processing capability in Data Vortex network architectures. The new design not only significantly improves network throughput and latency, but also eliminates the need for distributive traffic control mechanism originally embedded among nodes and the need for nodal buffering. The cost effectiveness is studied by a comparison study with the previously proposed 2- input buffered networks, and considerable performance enhancement can be achieved with similar or lower cost of hardware. Unlike previous implementation, the network leaves small probability of contention, therefore, the packet drop rate must be kept low for such implementation to be feasible and attractive, and it can be achieved with proper choice of operation conditions.

Keywords: Data Vortex, Packet Switch, Interconnection network, deflection, Network-on-chip

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Authors: Walter Hussak, Heiko Schröder

Abstract:

Star graphs are Cayley graphs of symmetric groups of permutations, with transpositions as the generating sets. A star graph is a preferred interconnection network topology to a hypercube for its ability to connect a greater number of nodes with lower degree. However, an attractive property of the hypercube is that it has a Hamiltonian decomposition, i.e. its edges can be partitioned into disjoint Hamiltonian cycles, and therefore a simple routing can be found in the case of an edge failure. The existence of Hamiltonian cycles in Cayley graphs has been known for some time. So far, there are no published results on the much stronger condition of the existence of Hamiltonian decompositions. In this paper, we give a construction of a Hamiltonian decomposition of the star graph 5-star of degree 4, by defining an automorphism for 5-star and a Hamiltonian cycle which is edge-disjoint with its image under the automorphism.

Keywords: interconnection networks, paths and cycles, graphs andgroups.

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Authors: Jin-O Kim, Hyun-Il Son

Abstract:

As the electrical power industry is restructured, the electrical power exchange is becoming extended. One of the key information used to determine how much power can be transferred through the network is known as available transfer capability (ATC). To calculate ATC, traditional deterministic approach is based on the severest case, but the approach has the complexity of procedure. Therefore, novel approach for ATC calculation is proposed using cost-optimization method in this paper, and is compared with well-being method and risk-benefit method. This paper proposes the optimal transfer capability of HVDC system between mainland and a separated island in Korea through these three methods. These methods will consider production cost, wheeling charge through HVDC system and outage cost with one depth (N-1 contingency)

Keywords: ATC, power system interconnection, well-being method, cost-optimization method, risk-benefit analysis, outage cost.

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Authors: Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh

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The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.

Keywords: MinRoot, CMesh, NoC, Topology, Performance Evaluation

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Authors: Carmen Navarrete, Eloy Anguiano

Abstract:

In the last years, the computers have increased their capacity of calculus and networks, for the interconnection of these machines. The networks have been improved until obtaining the actual high rates of data transferring. The programs that nowadays try to take advantage of these new technologies cannot be written using the traditional techniques of programming, since most of the algorithms were designed for being executed in an only processor,in a nonconcurrent form instead of being executed concurrently ina set of processors working and communicating through a network.This paper aims to present the ongoing development of a new system for the reconfiguration of grouping of computers, taking into account these new technologies.

Keywords: Dynamic network topology, resource and task allocation, parallel computing, heterogeneous computing, dynamic reconfiguration.

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Authors: Mohammad Ali Jabraeil Jamali, Ahmad khademzadeh

Abstract:

In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network. Two virtual channels shared the same buffer space. Fault tolerant mechanisms for interconnection networks are becoming a critical design issue for large massively parallel computers. It is also important to high performance SoCs as the system complexity keeps increasing rapidly. On the message switching layer, we make improvement to boost system performance when there are faults involved in the components communication. The proposed scheme is when a node or a physical channel is deemed as faulty, the previous hop node will terminate the buffer occupancy of messages destined to the failed link. The buffer usage decisions are made at switching layer without interactions with higher abstract layer, thus buffer space will be released to messages destined to other healthy nodes quickly. Therefore, the buffer space will be efficiently used in case fault occurs at some nodes.

Keywords: DAMQ, NoC, fault tolerant, odd-even routingalgorithm, buffer space.

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Authors: Shih-Yan Chen, Shin-Shin Kao

Abstract:

In this paper, a thorough review about dual-cubes, DCn, the related studies and their variations are given. DCn was introduced to be a network which retains the pleasing properties of hypercube Qn but has a much smaller diameter. In fact, it is so constructed that the number of vertices of DCn is equal to the number of vertices of Q2n +1. However, each vertex in DCn is adjacent to n + 1 neighbors and so DCn has (n + 1) × 2^2n edges in total, which is roughly half the number of edges of Q2n+1. In addition, the diameter of any DCn is 2n +2, which is of the same order of that of Q2n+1. For selfcompleteness, basic definitions, construction rules and symbols are provided. We chronicle the results, where eleven significant theorems are presented, and include some open problems at the end.

Keywords: Hypercubes, dual-cubes, fault-tolerant hamiltonian property, dual-cube extensive networks, dual-cube-like networks.

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Authors: Meng-Jou Chien, Jheng-Cheng Chen, Chang-Hsiung Tsai

Abstract:

Let max_ζG(m) denote the maximum number of edges in a subgraph of graph G induced by m nodes. The n-dimensional augmented cube, denoted as AQn, a variation of the hypercube, possesses some properties superior to those of the hypercube. We study the cases when G is the augmented cube AQn.

Keywords: Interconnection network, Augmented cube, Induced subgraph, Bisection width.

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Authors: M. İskefiyeli, İ. Özçelik

Abstract:

PROFIBUS (PROcess FIeld BUS) which is defined with international standarts (IEC61158, EN50170) is the most popular fieldbus, and provides a communication between industrial applications which are located in different control environment and location in manufacturing, process and building automation. Its communication speed is from 9.6 Kbps to 12 Mbps over distances from 100 to 1200 meters, and so it is to be often necessary to interconnect them in order to break these limits. Unfortunately this interconnection raises several issues and the solutions found so far are not very satisfactory. In this paper, we propose a new solution to interconnect PROFIBUS segments, which uses a wireless MAN based on the IEEE 802.16 standard as a backbone system. Also, the solution which is described a model for internetworking unit integrates the traffic generated by PROFIBUS segments into IEEE 802.16 wireless MAN using encapsulation technique.

Keywords: Internetworking Unit, PROFIBUS, WiMAX, WMAN, 802.16.

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Authors: Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin, Lieguang zeng

Abstract:

Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Keywords: Network on Chip (NoC), interconnect architecture, performance, area, Three Dimensional Integrate Circuit (3D IC).

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Authors: Z. Abdollahi Biron, P. Pisu

Abstract:

Connected vehicles are one of the promising technologies for future Intelligent Transportation Systems (ITS). A connected vehicle system is essentially a set of vehicles communicating through a network to exchange their information with each other and the infrastructure. Although this interconnection of the vehicles can be potentially beneficial in creating an efficient, sustainable, and green transportation system, a set of safety and reliability challenges come out with this technology. The first challenge arises from the information loss due to unreliable communication network which affects the control/management system of the individual vehicles and the overall system. Such scenario may lead to degraded or even unsafe operation which could be potentially catastrophic. Secondly, faulty sensors and actuators can affect the individual vehicle’s safe operation and in turn will create a potentially unsafe node in the vehicular network. Further, sending that faulty sensor information to other vehicles and failure in actuators may significantly affect the safe operation of the overall vehicular network. Therefore, it is of utmost importance to take these issues into consideration while designing the control/management algorithms of the individual vehicles as a part of connected vehicle system. In this paper, we consider a connected vehicle system under Co-operative Adaptive Cruise Control (CACC) and propose a fault diagnosis scheme that deals with these aforementioned challenges. Specifically, the conventional CACC algorithm is modified by adding a Kalman filter-based estimation algorithm to suppress the effect of lost information under unreliable network. Further, a sliding mode observer-based algorithm is used to improve the sensor reliability under faults. The effectiveness of the overall diagnostic scheme is verified via simulation studies.

Keywords: Fault diagnostics, communication network, connected vehicles, packet drop out, platoon.

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Authors: Hsun Su, Yuan-Kang Shih, Shin-Shin Kao

Abstract:

Many well-known interconnection networks, such as kary n-cubes, recursive circulant graphs, generalized recursive circulant graphs, circulant graphs and so on, are shown to belong to the family of cycle composition networks. Recently, various studies about mutually independent hamiltonian cycles, abbreviated as MIHC-s, on interconnection networks are published. In this paper, using an improved construction method, we obtain MIHC-s on cycle composition networks with a much weaker condition than the known result. In fact, we established the existence of MIHC-s in the cycle composition networks and the result is optimal in the sense that the number of MIHC-s we constructed is maximal.

Keywords: Hamiltonian cycle, k-ary n-cube, cycle composition networks, mutually independent.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

Abstract:

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Mihai Rebenciuc, Simona Mihaela Bibic

Abstract:

Branch of modern mathematics, graphs represent instruments for optimization and solving practical applications in various fields such as economic networks, engineering, network optimization, the geometry of social action, generally, complex systems including contemporary urban problems (path or transport efficiencies, biourbanism, & c.). In this paper is studied the interconnection of some urban network, which can lead to a simulation problem of a digraph through another digraph. The simulation is made univoc or more general multivoc. The concepts of fragment and atom are very useful in the study of connectivity in the digraph that is simulation - including an alternative evaluation of k- connectivity. Rough set approach in (bi)digraph which is proposed in premier in this paper contribute to improved significantly the evaluation of k-connectivity. This rough set approach is based on generalized rough sets - basic facts are presented in this paper.

Keywords: (Bi)digraphs, rough set theory, systems of interacting agents, complex systems.

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Authors: G. Gavrilovs, O. Borscevskis

Abstract:

This paper describes interconnection between technical and economical making decision. The reason of this dealing could be different: poor technical condition, change of substation (electrical network) regime, power transformer owner budget deficit and increasing of tariff on electricity. Establishing of recommended practice as well as to give general advice and guidance in economical sector, testing, diagnostic power transformers to establish its conditions, identify problems and provide potential remedies.

Keywords: Diagnostic results, load forecasting, power supplysystem, replacement of power transformer.

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Authors: Marko A. Rodriguez

Abstract:

There exists an injective, information-preserving function that maps a semantic network (i.e a directed labeled network) to a directed network (i.e. a directed unlabeled network). The edge label in the semantic network is represented as a topological feature of the directed network. Also, there exists an injective function that maps a directed network to an undirected network (i.e. an undirected unlabeled network). The edge directionality in the directed network is represented as a topological feature of the undirected network. Through function composition, there exists an injective function that maps a semantic network to an undirected network. Thus, aside from space constraints, the semantic network construct does not have any modeling functionality that is not possible with either a directed or undirected network representation. Two proofs of this idea will be presented. The first is a proof of the aforementioned function composition concept. The second is a simpler proof involving an undirected binary encoding of a semantic network.

Keywords: general-modeling, multi-relational networks, semantic networks

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Authors: Weng Ming Chu

Abstract:

When faced with stochastic networks with an uncertain duration for their activities, the securing of network completion time becomes problematical, not only because of the non-identical pdf of duration for each node, but also because of the interdependence of network paths. As evidenced by Adlakha & Kulkarni [1], many methods and algorithms have been put forward in attempt to resolve this issue, but most have encountered this same large-size network problem. Therefore, in this research, we focus on network reduction through a Series/Parallel combined mechanism. Our suggested algorithm, named the Activity Network Reduction Algorithm (ANRA), can efficiently transfer a large-size network into an S/P Irreducible Network (SPIN). SPIN can enhance stochastic network analysis, as well as serve as the judgment of symmetry for the Graph Theory.

Keywords: Series/Parallel network, Stochastic network, Network reduction, Interdictive Graph, Complexity Index.

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Authors: S.M. Sarwarul Islam Rizvi, Zinat Sultana, Bo Sun, Md. Washiqul Islam

Abstract:

In a very simple form a Mobile Agent is an independent piece of code that has mobility and autonomy behavior. One of the main advantages of using Mobile Agent in a network is - it reduces network traffic load. In an, ad hoc network Mobile Agent can be used to protect the network by using agent based IDS or IPS. Besides, to deploy dynamic software in the network or to retrieve information from network nodes Mobile Agent can be useful. But in an ad hoc network the Mobile Agent itself needs some security. Security services should be guaranteed both for Mobile Agent and for Agent Server. In this paper to protect the Mobile Agent and Agent Server in an ad hoc network we have proposed a solution which is based on Threshold Cryptography, a new vibe in the cryptographic world where trust is distributed among multiple nodes in the network.

Keywords: Ad hoc network, Mobile Agent, Security, Threats, Threshold Cryptography.

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Authors: A. Charlangsut, N. Rugthaicharoencheep, S. Auchariyamet

Abstract:

Network reconfiguration is an operation to modify the network topology. The implementation of network reconfiguration has many advantages such as loss minimization, increasing system security and others. In this paper, two topics about the network reconfiguration in distribution system are briefly described. The first topic summarizes its impacts while the second explains some heuristic optimization techniques for solving the network reconfiguration problem.

Keywords: Network Reconfiguration, Optimization Techniques, Distribution System

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Authors: Jheng-Cheng Chen, Chia-Jui Lai, Chang-Hsiung Tsai,

Abstract:

The crossed cube is one of the most notable variations of hypercube, but some properties of the former are superior to those of the latter. For example, the diameter of the crossed cube is almost the half of that of the hypercube. In this paper, we focus on the problem embedding a Hamiltonian cycle through an arbitrary given edge in the crossed cube. We give necessary and sufficient condition for determining whether a given permutation with n elements over Zn generates a Hamiltonian cycle pattern of the crossed cube. Moreover, we obtain a lower bound for the number of different Hamiltonian cycles passing through a given edge in an n-dimensional crossed cube. Our work extends some recently obtained results.

Keywords: Interconnection network, Hamiltonian, crossed cubes, prescribed edge.

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Authors: Martin Hans Knahl

Abstract:

The Internet is the global data communications infrastructure based on the interconnection of both public and private networks using protocols that implement Internetworking on a global scale. Hence the control of protocol and infrastructure development, resource allocation and network operation are crucial and interlinked aspects. Internet Governance is the hotly debated and contentious subject that refers to the global control and operation of key Internet infrastructure such as domain name servers and resources such as domain names. It is impossible to separate technical and political positions as they are interlinked. Furthermore the existence of a global market, transparency and competition impact upon Internet Governance and related topics such as network neutrality and security. Current trends and developments regarding Internet governance with a focus on the policy-making process, security and control have been observed to evaluate current and future implications on the Internet. The multi stakeholder approach to Internet Governance discussed in this paper presents a number of opportunities, issues and developments that will affect the future direction of the Internet. Internet operation, maintenance and advisory organisations such as the Internet Corporation for Assigned Names and Numbers (ICANN) or the Internet Governance Forum (IGF) are currently in the process of formulating policies for future Internet Governance. Given the controversial nature of the issues at stake and the current lack of agreement it is predicted that institutional as well as market governance will remain present for the network access and content.

Keywords: Internet Governance, ICANN, Democracy, Security

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Authors: D. Prangchumpol

Abstract:

This paper is a description approach to predict incoming and outgoing data rate in network system by using association rule discover, which is one of the data mining techniques. Information of incoming and outgoing data in each times and network bandwidth are network performance parameters, which needed to solve in the traffic problem. Since congestion and data loss are important network problems. The result of this technique can predicted future network traffic. In addition, this research is useful for network routing selection and network performance improvement.

Keywords: Traffic prediction, association rule, data mining.

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Authors: M. Kassim, M. Ismail, K. Jumari, M.I Yusof

Abstract:

this paper presented a survey analysis subjected on network bandwidth management from published papers referred in IEEE Explorer database in three years from 2009 to 2011. Network Bandwidth Management is discussed in today-s issues for computer engineering applications and systems. Detailed comparison is presented between published papers to look further in the IP based network critical research area for network bandwidth management. Important information such as the network focus area, a few modeling in the IP Based Network and filtering or scheduling used in the network applications layer is presented. Many researches on bandwidth management have been done in the broad network area but fewer are done in IP Based network specifically at the applications network layer. A few researches has contributed new scheme or enhanced modeling but still the issue of bandwidth management still arise at the applications network layer. This survey is taken as a basic research towards implementations of network bandwidth management technique, new framework model and scheduling scheme or algorithm in an IP Based network which will focus in a control bandwidth mechanism in prioritizing the network traffic the applications layer.

Keywords: Bandwidth Management (BM), IP Based network, modeling, algorithm, internet traffic, network Management, Quality of Service (QoS).

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Authors: M. Safaei, M. Seifert, K. D. Thoben

Abstract:

Supply network management adopts a systematic and integrative approach to managing the operations and relationships of various parties in a supply network. The objective of the manufactures in their supply network is to reduce inventory costs and increase customer satisfaction levels. One way of doing that is to synchronize delivery performance. A supply network can be described by nodes representing the companies and the links (relationships) between these nodes. Uncertainty in delivery time depends on type of network relationship between suppliers. The problem is to understand how the individual uncertainties influence the total uncertainty of the network and identify those parts of the network, which has the highest potential for improving the total delivery time uncertainty.

Keywords: Delivery time uncertainty, Distribution function, Statistical method, Supply Network.

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