Search results for: metal-oxide-semiconductor field-effect transistor (MOSFET)

Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Jun Wang, Tingcun Wei

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The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, digitally-controlled DC-DC switching converter, FPGA, PLL megafunction, time resolution

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity, and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: LDMOS, amplifier, back-off, bias circuit

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Authors: Tian-Wei Huang, Wei-Ting Bai, Yu-Tung Cheng, Jeng-Han Tsai

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In this paper, a 1-stage 6-section conventional distributed amplifier (CDA) structure distributed power amplifier (DPA) fabricated in a 28-nm HPC+ 1P9M CMOS process is proposed. The transistor size selection is introduced to achieve broadband power matching and thus remains a high flatness output power and power added efficiency (PAE) within the bandwidth. With the inductive peaking technique, the high-frequency pole appears and the high-frequency gain is increased; the gain flatness becomes better as well. The inductive elements used to form an artificial transmission line are built up with a floating ground coplanar waveguide plane (CPWFG) rather than a microstrip line, coplanar waveguide (CPW), or spiral inductor to get better performance. The DPA achieves 12.6 dB peak gain at 52.5 GHz with 2.9 to 64.9 GHz 3-dB bandwidth. The Psat is 11.4 dBm with PAEMAX of 10.6 % at 25 GHz. The output 1-dB compression point power is 9.8 dBm.

Keywords: distributed power amplifier (DPA), gain bandwidth (GBW), floating ground CPW, inductive peaking, 28-nm, CMOS, 5G.

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Authors: A. Boursali, A. Guen-Bouazza

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

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Authors: Subal Kar, Madhuja Ghosh, Soumik Das, Antara Saha

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A novel technique has been developed to generate ultra-stable millimeter-wave signal by optical heterodyning of the output from two slave laser (SL) sources injection-locked to the sidebands of a frequency modulated (FM) master laser (ML). Precise thermal tuning of the SL sources is required to lock the particular slave laser frequency to the desired FM sidebands of the ML. The output signals from the injection-locked SL when coherently heterodyned in a fast response photo detector like high electron mobility transistor (HEMT), extremely stable millimeter-wave signal having very narrow line width can be generated. The scheme may also be used to generate ultra-stable sub-millimeter-wave/terahertz signal.

Keywords: FM sideband injection locking, master-slave injection locking, millimetre-wave signal generation, optical heterodyning

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Authors: Z. Kourdi, B. Bouazza, M. Khaouani, A. Guen-Bouazza, Z. Djennati, A. Boursali

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/mm, a peak extrinsic transconductance of 590 mS/mm at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, Silvaco, field plate, genetic algorithm, quantum

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Authors: Khaled A. Madi, Abdulalhakim O. Naji, Hassouna A. Aalaoh, Elmahdi Eldeeb

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Solar energy is one of the cleanest energy sources with no environmental impact. Due to rapid increase in industrial as well as domestic needs, solar energy becomes a good candidate for safe and easy to handle energy source, especially after it becomes available due to reduction of manufacturing price. The main part of the solar inverter system is the inverter where the DC is inverted to AC, where we try to minimize the loss of power to the minimum possible level by the use of microcontroller. In this work, a deep investigation is made experimentally as well as theoretically for a microcontroller based variable frequency power inverter. The microcontroller will provide the variable frequency Pulse Width Modulation (PWM) signal that will control the switching of the gate of the Insulating Gate Bipolar Transistor (IGBT) with less harmonics at the output of power inverter which can be fed to the public grid at high quality. The proposed work for single phase as well as three phases is also simulated using Matlab/Simulink where we found a good agreement between the simulated and the practical results, even though the experimental work were done in the laboratory of the academy.

Keywords: solar, inverter, PV, solar inverter system

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Authors: F. Z. Mahi, H. Marinchio, C. Palermo, L. Varani

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We propose an analytical approach for the admittance response calculation of the high mobility InGaAs channel transistors. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The total currents and the potentials matrix relation between the gate and the drain terminals determine the frequency-dependent small-signal admittance response. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand, to control the appearance of plasma resonances, and on the other hand, can give significant information about the admittance phase frequency dependence.

Keywords: small-signal admittance, Poisson equation, currents and potentials matrix, the drain and the gate terminals, analytical model

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: low-frequency noise, random telegraph noise, dynamic variation, SRRV

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

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Authors: Mantas Sakalas, Paulius Sakalas

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This paper presents an analysis and design of a ultrawideband 1.8GHz to 43GHz Low Noise Amplifier (LNA) in 0.1 μm Galium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT) technology. The feedback based bandwidth extension techniques is analyzed and based on the outcome, a two stage LNA is designed. The impedance fine tuning is implemented by using Transmission Line (TL) structures. The measured performance shows a good agreement with simulation results and an outstanding wideband noise matching. The measured small signal gain was 12 dB, whereas a 3 dB gain flatness in range from 1.8 - 43 GHz was reached. The noise figure was below 4 dB almost all over the entire frequency band of 1.8GHz to 43GHz, the output power at 1 dB compression point was 6 dBm and the DC power consumption was 95 mW. To the best knowledge of the authors the designed LNA outperforms the State of the Art (SotA) reported LNA designs in terms of combined parameters of noise figure within the addressed ultra-wide 3 dB bandwidth, linearity and DC power consumption.

Keywords: feedback amplifiers, GaAs pHEMT, monolithic microwave integrated circuit, LNA, noise matching

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Authors: Nikhil Jain, Bin Yu

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We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: V. S. Klimash, Ye Min Thu

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Thyristor rectifiers, inverters grid-tied, and AC voltage regulators are widely used in industry, and on electrified transport, they have a lot in common both in the power circuit and in the control system. They have a common mathematical structure and switching processes. At the same time, the rectifier, but the inverter units and thyristor regulators of alternating voltage are considered separately both theoretically and practically. They are written about in different books as completely different devices. The aim of this work is to combine them into one class based on the unity of the equations describing electromagnetic processes, and then, to show this unity on the mathematical model and experimental setup. Based on research from mathematics to the product, a conclusion is made about the methodology for the rapid conduct of research and experimental design work, preparation for production and serial production of converters with a unified bundle. In recent years, there has been a transition from thyristor circuits and transistor in modular design. Showing the example of thyristor rectifiers and AC voltage regulators, we can conclude that there is a unity of mathematical structures and grid-tied thyristor converters.

Keywords: direct current, alternating current, rectifier, AC voltage regulator, generalized mathematical model

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Authors: S. Forel, F. Bouanis, L. Catala, I. Florea, V. Huc, F. Fossard, A. Loiseau, C. Cojocaru

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Single wall carbon nanotubes are seen as excellent candidate for application on nanoelectronic devices because of their remarkable electronic and mechanical properties. These unique properties are highly dependent on their chiral structures and the diameter. Therefore, structure controlled growth of SWNTs, especially directly on final device’s substrate surface, are highly desired for the fabrication of SWNT-based electronics. In this work, we present a new approach to control the diameter of SWNTs and eventually their chirality. Because of their potential to control the SWNT’s chirality, bi-metalics nanoparticles are used to prepare alloy nanoclusters with specific structure. The catalyst nanoparticles are pre-formed following a previously described process. Briefly, the oxide surface is first covered with a SAM (self-assembled monolayer) of a pyridine-functionalized silane. Then, bi-metallic (Fe-Ru, Co-Ru and Ni-Ru) complexes are assembled by coordination bonds on the pre-formed organic SAM. The resultant alloy nanoclusters were then used to catalyze SWNTs growth on SiO2/Si substrates via CH4/H2 double hot-filament chemical vapor deposition (d-HFCVD). The microscopy and spectroscopy analysis demonstrate the high quality of SWNTs that were furthermore integrated into high-quality SWNT-FET.

Keywords: nanotube, CVD, device, transistor

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Authors: Yu-Ting Chen, Shiao-Shing Chen, Hung-Te Hsu, Saikat Sinha Ray

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Forward osmosis (FO) is a crucial technology with low operating pressure and cost for water reuse and reclamation. In Taiwan, with the advance of science and technology, thin film transistor liquid crystal displays (TFT-LCD) based industries are growing exponentially. In the optoelectronic industry wastewater, the iodide is one of the valuable element; it is also used in the medical industry. In this study, it was intended to concentrate iodide by utilizing FO system and can be reused for TFT-LCD production. Cellulose triacetate (CTA) membranes were used for all these FO experiments, and potassium iodide solution was used as the feed solution. It has been found that EDTA-2Na as draw solution at pH 8 produced high water flux and minimized salt leakage. The result also demonstrated that EDTA-2Na of concentration 0.6M could achieve the highest water flux (6.69L/m2 h). Additionally, from the recovered iodide ion from pH 3-8, the I- species was found to be more than 99%, whereas I2 was measured to be less than 1%. When potassium iodide solution was used from low to high concentration (1000 ppm to 10000 ppm), the iodide rejection was found to be than more 90%. Since, CTA membrane is negatively charged and I- is anionic in nature, so it will from electrostatic repulsion and hence there will be higher rejection. The overall performance demonstrates that recovery of concentrated iodide using FO system is a promising technology.

Keywords: draw solution, EDTA-2Na, forward osmosis, potassium iodide

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Authors: Lin Gong, Holger Göbel

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In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

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Authors: Monika Rawat, Rahul Kumar

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Input output Buffer Information Specification (IBIS) models are used for describing the analog behavior of the Input Output (I/O) buffers of a digital device. They are widely used to perform signal integrity analysis. Advantages of using IBIS models include simple structure, IP protection and fast simulation time with reasonable accuracy. As design complexity of driver and receiver increases, capturing exact behavior from transistor level model into IBIS model becomes an essential task to achieve better accuracy. In this paper, an improvement in existing methodology of generating IBIS model for complex I/O interfaces such as Inter-Integrated Circuit (I2C) and Low Voltage Differential Signaling (LVDS) is proposed. Furthermore, the accuracy and computational performance of standard method and proposed approach with respect to SPICE are presented. The investigations will be useful to further improve the accuracy of IBIS models and to enhance their wider acceptance.

Keywords: IBIS, signal integrity, open-drain buffer, low voltage differential signaling, behavior modelling, transient simulation

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Authors: Ravi Kiran Jaladi, Ezz I. El-Masry

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Emerging technologies such as ultra-wide band wireless access technology that operate at ultra-low power present several challenges due to their inherent design that limits the use of voltage-mode filters. Therefore, Continuous-time current-mode (CTCM) filters have become very popular in recent times due to the fact they have a wider dynamic range, improved linearity, and extended bandwidth compared to their voltage-mode counterparts. The goal of this research is to develop analog filters which are suitable for the current scaling CMOS technologies. Bulk-driven MOSFET is one of the most popular low power design technique for the existing challenges, while other techniques have obvious shortcomings. In this work, a CTCM Gate-driven (GD) differentiator has been presented with a frequency range from dc to 100MHz which operates at very low supply voltage of 0.7 volts. A novel CTCM Bulk-driven (BD) differentiator has been designed for the first time which reduces the power consumption multiple times that of GD differentiator. These GD and BD differentiator has been simulated using CADENCE TSMC 65nm technology for all the bilinear and biquadratic band-pass frequency responses. These basic building blocks can be used to implement the higher order filters. A 6th order cascade CTCM Chebyshev band-pass filter has been designed using the GD and BD techniques. As a conclusion, a low power GD and BD 6th order chebyshev stagger-tuned band-pass filter was simulated and all the parameters obtained from all the resulting realizations are analyzed and compared. Monte Carlo analysis is performed for both the 6th order filters and the results of sensitivity analysis are presented.

Keywords: bulk-driven (BD), continuous-time current-mode filters (CTCM), gate-driven (GD)

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Authors: Aqsa Ali, Aleem Mushtaq, Attaullah Memon, Monna

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In this paper, we present a low cost design for a smart glove that can perform sign language recognition to assist the speech impaired people. Specifically, we have designed and developed an Assistive Hand Gesture Interpreter that recognizes hand movements relevant to the American Sign Language (ASL) and translates them into text for display on a Thin-Film-Transistor Liquid Crystal Display (TFT LCD) screen as well as synthetic speech. Linear Bayes Classifiers and Multilayer Neural Networks have been used to classify 11 feature vectors obtained from the sensors on the glove into one of the 27 ASL alphabets and a predefined gesture for space. Three types of features are used; bending using six bend sensors, orientation in three dimensions using accelerometers and contacts at vital points using contact sensors. To gauge the performance of the presented design, the training database was prepared using five volunteers. The accuracy of the current version on the prepared dataset was found to be up to 99.3% for target user. The solution combines electronics, e-textile technology, sensor technology, embedded system and machine learning techniques to build a low cost wearable glove that is scrupulous, elegant and portable.

Keywords: American sign language, assistive hand gesture interpreter, human-machine interface, machine learning, sensing glove

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: Young Jae Choung, Seoung Bum Kim

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Statistical Process Control (SPC) is a popular technique for process monitoring. A widely used tool in SPC is a control chart, which is used to detect the abnormal status of a process and maintain the controlled status of the process. Traditional control charts, such as Hotelling’s T2 control chart, are effective techniques to detect abnormal observations and monitor processes. However, many complicated manufacturing systems exhibit nonlinearity because of the different demands of the market. In this case, the unregulated use of a traditional linear modeling approach may not be effective. In reality, many industrial processes contain the nonlinear and time-varying properties because of the fluctuation of process raw materials, slowing shift of the set points, aging of the main process components, seasoning effects, and catalyst deactivation. The use of traditional SPC techniques with time-varying data will degrade the performance of the monitoring scheme. To address these issues, in the present study, we propose a parameterless self-organizing map (PLSOM)-based control chart. The PLSOM-based control chart not only can manage a situation where the distribution or parameter of the target observations changes, but also address the nonlinearity of modern manufacturing systems. The control limits of the proposed PLSOM chart are established by estimating the empirical level of significance on the percentile using a bootstrap method. Experimental results with simulated data and actual process data from a thin-film transistor-liquid crystal display process demonstrated the effectiveness and usefulness of the proposed chart.

Keywords: control chart, parameter-less self-organizing map, self-organizing map, time-varying property

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Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center

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Authors: Sungsoo Na, Chanho Park

Abstract:

Lung cancer is one of the most common severe diseases driving to the death of a human. Lung cancer can be divided into two cases of small-cell lung cancer (SCLC) and non-SCLC (NSCLC), and about 80% of lung cancers belong to the case of NSCLC. From several studies, the correlation between epidermal growth factor receptor (EGFR) and NSCLCs has been investigated. Therefore, EGFR inhibitor drugs such as gefitinib and erlotinib have been used as lung cancer treatments. However, the treatments result showed low response (10~20%) in clinical trials due to EGFR mutations that cause the drug resistance. Patients with resistance to EGFR inhibitor drugs usually are positive to KRAS mutation. Therefore, assessment of EGFR and KRAS mutation is essential for target therapies of NSCLC patient. In order to overcome the limitation of conventional therapies, overall EGFR and KRAS mutations have to be monitored. In this work, the only detection of EGFR will be presented. A variety of techniques has been presented for the detection of EGFR mutations. The standard detection method of EGFR mutation in ctDNA relies on real-time polymerase chain reaction (PCR). Real-time PCR method provides high sensitive detection performance. However, as the amplification step increases cost effect and complexity increase as well. Other types of technology such as BEAMing, next generation sequencing (NGS), an electrochemical sensor and silicon nanowire field-effect transistor have been presented. However, those technologies have limitations of low sensitivity, high cost and complexity of data analyzation. In this report, we propose a label-free and high-sensitive detection method of lung cancer using quartz crystal microbalance based platform. The proposed platform is able to sense lung cancer mutant DNA with a limit of detection of 1nM.

Keywords: cancer DNA, resonance frequency, quartz crystal microbalance, lung cancer

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Authors: Osamede Asowata, Christo Pienaar, Johan Bekker

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Photovoltaic (PV) modules may become a trend for future PV systems because of their greater flexibility in distributed system expansion, easier installation due to their nature, and higher system-level energy harnessing capabilities under shaded or PV manufacturing mismatch conditions. This is as compared to the single or multi-string inverters. Novel residential scale PV arrays are commonly connected to the grid by a single DC–AC inverter connected to a series, parallel or series-parallel string of PV panels, or many small DC–AC inverters which connect one or two panels directly to the AC grid. With an increasing worldwide interest in sustainable energy production and use, there is renewed focus on the power electronic converter interface for DC energy sources. Three specific examples of such DC energy sources that will have a role in distributed generation and sustainable energy systems are the photovoltaic (PV) panel, the fuel cell stack, and batteries of various chemistries. A high-efficiency inverter using Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) for all active switches is presented for a non-isolated photovoltaic and AC-module applications. The proposed configuration features a high efficiency over a wide load range, low ground leakage current and low-output AC-current distortion with no need for split capacitors. The detailed power stage operating principles, pulse width modulation scheme, multilevel bootstrap power supply, and integrated gate drivers for the proposed inverter is described. Experimental results of a hardware prototype, show that not only are MOSFET efficient in the system, it also shows that the ground leakage current issues are alleviated in the proposed inverter and also a 98 % maximum associated driver circuit is achieved. This, in turn, provides the need for a possible photovoltaic panel switching technique. This will help to reduce the effect of cloud movements as well as improve the overall efficiency of the system.

Keywords: grid connected photovoltaic (PV), Matlab efficiency simulation, maximum power point tracking (MPPT), module integrated converters (MICs), multilevel converter, series connected converter

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Authors: Alexander Kospach, Fabian Benezeder, Jürgen Abraham

Abstract:

E-mobility poses new challenges for inverters (e.g., higher switching frequencies) in terms of thermal behavior and thermal management. Due to even higher switching frequencies, thermal losses become greater, and the cooling of critical components (like insulated gate bipolar transistor and diodes) comes into focus. New manufacturing methods, such as 3D printing, enable completely new pin-fin structures that can handle higher waste heat to meet the new thermal requirements. Based on the geometrical specifications of the industrial partner regarding the manufacturing possibilities for 3D printing, different and completely new pin-fin structures were numerically investigated for their hydraulic and thermal behavior in fundamental studies assuming an indirect liquid cooling. For the 3D computational fluid dynamics (CFD) thermal simulations OpenFOAM was used, which has as numerical method the finite volume method for solving the conjugate heat transfer problem. A steady-state solver for turbulent fluid flow and solid heat conduction with conjugate heat transfer between solid and fluid regions was used for the simulations. In total, up to fifty pinfin structures and arrangements, some of them completely new, were numerically investigated. On the basis of the results of the principal investigations, the best two pin-fin structures and arrangements for the complete module cooling of an automotive inverter were numerically investigated and compared. There are clear differences in the maximum temperatures for the critical components, such as IGTBs and diodes. In summary, it was shown that 3D pin fin structures can significantly contribute to the improvement of heat transfer and cooling of an automotive inverter. This enables in the future smaller cooling designs and a better lifetime of automotive inverter modules. The new pin fin structures and arrangements can also be applied to other cooling applications where 3D printing can be used.

Keywords: pin fin heat sink optimization, 3D printed pin fins, CFD simulation, power electronic cooling, thermal management

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Authors: Chyuan Haur Kao, Hsiang Chen, Yu Sheng Tsai, Chen Hao Hung, Yu Shan Lee

Abstract:

Dielectric electrolyte-insulator-semiconductor sensing membranes-based biosensors have been intensively investigated because of their simple fabrication, low cost, and fast response. However, to enhance their sensing performance, it is worthwhile to explore alternative materials, distinct processes, and novel treatments. An ISFET can be viewed as a variation of MOSFET with the dielectric oxide layer as the sensing membrane. Then, modulation on the work function of the gate caused by electrolytes in various ion concentrations could be used to calculate the ion concentrations. Recently, owing to the advancement of CMOS technology, some high dielectric materials substrates as the sensing membranes of electrolyte-insulator-semiconductor (EIS) structures. The EIS with a stacked-layer of SiO₂ layer between the sensing membrane and the silicon substrate exhibited a high pH sensitivity and good long-term stability. IGZO is a wide-bandgap (~3.15eV) semiconductor of the III-VI semiconductor group with several preferable properties, including good transparency, high electron mobility, wide band gap, and comparable with CMOS technology. IGZO was sputtered by reactive radio frequency (RF) on a p-type silicon wafer with various gas ratios of Ar:O₂ and was treated with rapid thermal annealing in O₂ ambient. The sensing performance, including sensitivity, hysteresis, and drift rate was measured and XRD, XPS, and AFM analyses were also used to study the material properties of the IGZO membrane. Moreover, IGZO was used as a sensing membrane in dielectric EIS bio-sensor structures. In addition to traditional pH sensing capability, detection for concentrations of Na+, K+, urea, glucose, and creatinine was performed. Moreover, post rapid thermal annealing (RTA) treatment was confirmed to improve the material properties and enhance the multi-analyte sensing capability for various ions or chemicals in solutions. In this study, the IGZO sensing membrane with annealing in O₂ ambient exhibited a higher sensitivity, higher linearity, higher H+ selectivity, lower hysteresis voltage and lower drift rate. Results indicate that the IGZO dielectric sensing membrane on the EIS structure is promising for future bio-medical device applications.

Keywords: dielectric sensing membrane, IGZO, hydrogen ion, plasma, rapid thermal annealing

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Authors: Tomas Vincze, Michal Micjan, Milan Pavuk, Martin Weis

Abstract:

In recent years, alternative materials are gaining attention to replace polycrystalline and amorphous silicon, which are a standard for low requirement devices, where silicon is unnecessarily and high cost. For that reason, metal oxides are envisioned as the new materials for these low-requirement applications such as sensors, solar cells, energy storage devices, or field-effect transistors. Their most common way of layer growth is sputtering; however, this is a high-cost fabrication method, and a more industry-suitable alternative is the sol-gel method. In this group of materials, many oxides exhibit a semiconductor-like behavior with sufficiently high mobility to be applied as transistors. The sol-gel method is a cost-effective deposition technique for semiconductor-based devices. Copper oxides, as p-type semiconductors with free charge mobility up to 1 cm2/Vs., are suitable replacements for poly-Si or a-Si:H devices. However, to reach the potential of silicon devices, a fine-tuning of material properties is needed. Here we focus on the optimization of the electrical parameters of copper oxide-based field-effect transistors by modification of precursor solvent (usually 2-methoxy ethanol). However, to achieve solubility and high-quality films, a better solvent is required. Since almost no solvents have both high dielectric constant and high boiling point, an alternative approach was proposed with blend solvents. By mixing isopropyl alcohol (IPA) and 2-methoxy ethanol (2ME) the precursor reached better solubility. The quality of the layers fabricated using mixed solutions was evaluated in accordance with the surface morphology and electrical properties. The IPA:2ME solution mixture reached optimum results for the weight ratio of 1:3. The cupric oxide layers for optimal mixture had the highest crystallinity and highest effective charge mobility.

Keywords: copper oxide, field-effect transistor, semiconductor, sol-gel method

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Authors: S. Behnia, S. Fathizadeh, A. Akhshani

Abstract:

In the recent decades, DNA has increasingly interested in the potential technological applications that not directly related to the coding for functional proteins that is the expressed in form of genetic information. One of the most interesting applications of DNA is related to the construction of nanostructures of high complexity, design of functional nanostructures in nanoelectronical devices, nanosensors and nanocercuits. In this field, DNA is of fundamental interest to the development of DNA-based molecular technologies, as it possesses ideal structural and molecular recognition properties for use in self-assembling nanodevices with a definite molecular architecture. Also, the robust, one-dimensional flexible structure of DNA can be used to design electronic devices, serving as a wire, transistor switch, or rectifier depending on its electronic properties. In order to understand the mechanism of the charge transport along DNA sequences, numerous studies have been carried out. In this regard, conductivity properties of DNA molecule could be investigated in a simple, but chemically specific approach that is intimately related to the Su-Schrieffer-Heeger (SSH) model. In SSH model, the non-diagonal matrix element dependence on intersite displacements is considered. In this approach, the coupling between the charge and lattice deformation is along the helix. This model is a tight-binding linear nanoscale chain established to describe conductivity phenomena in doped polyethylene. It is based on the assumption of a classical harmonic interaction between sites, which is linearly coupled to a tight-binding Hamiltonian. In this work, the Hamiltonian and corresponding motion equations are nonlinear and have high sensitivity to initial conditions. Then, we have tried to move toward the nonlinear dynamics and phase space analysis. Nonlinear dynamics and chaos theory, regardless of any approximation, could open new horizons to understand the conductivity mechanism in DNA. For a detailed study, we have tried to study the current flowing in DNA and investigated the characteristic I-V diagram. As a result, It is shown that there are the (quasi-) ohmic areas in I-V diagram. On the other hand, the regions with a negative differential resistance (NDR) are detectable in diagram.

Keywords: DNA conductivity, Landauer resistance, negative dierential resistance, Chaos theory, mean Lyapunov exponent

Procedia PDF Downloads 396