Search results for: euler circuit and path

Authors: Milad Kaboli

Abstract:

A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

Procedia PDF Downloads 443

Authors: Victor Emeli, Akansel Cosgun

Abstract:

This paper explores the navigation among movable obstacles (NAMO) problem and proposes joint path and push planning: which path to take and in what direction the obstacles should be pushed at, given a start and goal position. We present a planning algorithm for selecting a path and the obstacles to be pushed, where a rapidly-exploring random tree (RRT)-based heuristic is employed to calculate a minimal collision path. When it is necessary to apply a pushing force to slide an obstacle out of the way, the planners leverage means-end analysis through a dynamic physics simulation to determine the sequence of linear pushes to clear the necessary space. Simulation experiments show that our approach finds solutions in higher clutter percentages (up to 49%) compared to the straight-line push planner (37%) and RRT without pushing (18%).

Keywords: motion planning, path planning, push planning, robot navigation

Procedia PDF Downloads 141

Authors: Yansong Gao, Damith C.Ranasinghe, Siad F. Al-Sarawi, Omid Kavehei, Derek Abbott

Abstract:

Passive crossbar arrays is in principle the simplest functional electrical circuit, together with memristive device in cross-point, holding great promise in future high-density, non-volatile memories. However, the greatest problem of crossbar array is the sneak path current. In this paper, we investigate one type of memristive device with intrinsic rectification behavior to address the sneak path currents. Firstly, a SPICE behavior model written in Verilog-A language of the memristive device is presented to fit experimental data published in literature. Next, systematic performance simulations including read margin and power consumption of crossbar array, which uses the self-rectifying memristive device as storage element at cross-point, with respect to different crossbar sizes, interconnect resistance, ratio of HRS/LRS (High Resistance State/ Low Resistance State), rectification ratio and different read schemes are conducted. Subsequently, Trade-offs among reading margin, power consumption, and reading schemes are analyzed to provide guidelines for circuit design. Finally, performance comparison between the memristive device with/without intrinsic rectification behavior is given to show the worthiness of this intrinsic rectification behavior.

Keywords: memristive device, memristor, crossbar, RRAM, read margin, power consumption

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Authors: Xiaohui Wang, Liwei Sun, Guilin Zhang

Abstract:

Printed circuit board (PCB) is the carrier of electronic components. Its coating is the first barrier for protecting itself. If the coating is damaged, the performance of printed circuit board will decrease rapidly until failure. Therefore, the coating plays an important role in the entire printed circuit board. There are common four kinds of coating of printed circuit board that the material of the coatings are paryleneC, acrylic, polyurethane, silicone. In this paper, we designed an accelerated degradation test of humid and heat for these four kinds of coating. And chose insulation resistance, moisture absorption and surface morphology as its test indexes. By comparing the change of insulation resistance of the coating before and after the test, we estimate failure time of these coatings based on the degradation of insulation resistance. Based on the above, we estimate the service life of the four kinds of PCB.

Keywords: printed circuit board, life assessment, insulation resistance, coating material

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Authors: Simona Ziukaite, Remigijus Ivanauskas, Gintaras Denafas

Abstract:

Market development of electrical and electronic equipment and a short life cycle is driven by the increasing waste streams. Gold Au, copper Cu, silver Ag and palladium Pd can be found on printed circuit board. These metals make up the largest value of printed circuit board. Therefore, the printed circuit boards scrap is valuable as potential raw material for precious metals recovery. A comparison of Cu, Au, Ag, Pd recovery from waste printed circuit techniques was selected metals leaching of chemical reagents. The study was conducted using the selected multistage technique for Au, Cu, Ag, Pd recovery of printed circuit board. In the first and second metals leaching stages, as the elution reagent, 2M H2SO4 and H2O2 (35%) was used. In the third stage, leaching of precious metals used solution of 20 g/l of thiourea and 6 g/l of Fe2 (SO4)3. Verify the efficiency of the method was carried out the metals leaching test with aqua regia. Based on the experimental study, the leaching efficiency, using the preferred methodology, 60 % of Au and 85,5 % of Cu dissolution was achieved. Metals leaching efficiency after waste mechanical crushing and thermal treatment have been increased by 1,7 times (40 %) for copper, 1,6 times (37 %) for gold and 1,8 times (44 %) for silver. It was noticed that, the Au amount in old (> 20 years) waste is 17 times more, Cu amount - 4 times more, and Ag - 2 times more than in the new (< 1 years) waste. Palladium in the new printed circuit board waste has not been found, however, it was established that from 1 t of old printed circuit board waste can be recovered 1,064 g of Pd (leaching with aqua regia). It was found that from 1 t of old printed circuit board waste can be recovered 1,064 g of Ag. Precious metals recovery in Lithuania was estimated in this study. Given the amounts of generated printed circuit board waste, the limits for recovery of precious metals were identified.

Keywords: leaching efficiency, limits for recovery, precious metals recovery, printed circuit board waste

Procedia PDF Downloads 363

Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

Abstract:

For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

Procedia PDF Downloads 356

Authors: Peng Lu, Branimir Radisavljevic, Martin Seeger, Daniel Over, Torsten Votteler, Bernardo Galletti

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CO₂-based gas mixtures exhibit huge potential as the interruption medium for replacing SF₆ in high voltage switchgears. In this paper, the recovery characteristics of dielectric strength of CO₂-O₂ mixture in the post arc phase after the current zero are presented. As representative examples, the dielectric recovery curves under conditions of different gas filling pressures and short-circuit current amplitudes are presented. A series of dielectric recovery measurements suggests that the dielectric recovery rate is proportional to the mass flux of the blowing gas, and the dielectric strength recovers faster in the case of lower short circuit currents.

Keywords: CO₂ mixture, high voltage circuit breakers, dielectric recovery rate, short-circuit current, mass flux

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Authors: Chor Nejmeddine, Ines Ben Omrane, Mohamed Abdelwahed

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In this paper, we present a posteriori analysis of the discretization of the heat equation by spectral element method. We apply Euler's implicit scheme in time and spectral method in space. We propose two families of error indicators, both of which are built from the residual of the equation and we prove that they satisfy some optimal estimates. We present some numerical results which are coherent with the theoretical ones.

Keywords: heat equation, spectral elements discretization, error indicators, Euler

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Authors: R. K. Saket, K. S. Anand Kumar

Abstract:

This paper presents an innovative 3-wire capacitor circuit system used to increase the efficiency and comfort improvement of permanent split-capacitor ceiling fan. In this innovative circuit, current has been reduced to save electrical power. The system could be used to replace standard single phase motor 2-wire capacitor configuration by cost effective split value X rated of optimized AC capacitors with the auxiliary winding to provide reliable ceiling fan operation and improved machine performance to save power. In basic system operations, comparisons with conventional ceiling fan are described.

Keywords: permanent split-capacitor motor, innovative 3-wire capacitor circuit system, standard 2-wire capacitor circuit system, metalized film X-rated capacitor

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Authors: Rajesh Kumar, Roopali Dogra, Puneet Aggarwal

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In the era of technological advancement, use of computer technology has become inevitable. Hence it has become the need of the hour to integrate software methods in engineering curriculum as a part to boost pedagogy techniques. Simulations software is a great help to graduates of disciplines such as electrical engineering. Since electrical engineering deals with high voltages and heavy instruments, extra care must be taken while operating with them. The viable solution would be to have appropriate control. The appropriate control could be well designed if engineers have knowledge of kind of waveforms associated with the system. Though these waveforms can be plotted manually, but it consumes a lot of time. Hence aid of simulation helps to understand steady state of system and resulting in better performance. In this paper computer, aided teaching of transformer is carried out using MATLAB/Simulink. The test carried out on a transformer includes open circuit test and short circuit respectively. The respective parameters of transformer are then calculated using the values obtained from open circuit and short circuit test respectively using Simulink.

Keywords: computer aided teaching, open circuit test, short circuit test, simulink, transformer

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Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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Authors: Palwinder Singh, Munish Sandhir, Tejinder Singh

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The ordinary differential equations (ODE) represent a natural framework for mathematical modeling of many real-life situations in the field of engineering, control systems, physics, chemistry and astronomy etc. Such type of differential equations can be solved by analytical methods or by numerical methods. If the solution is calculated using analytical methods, it is done through calculus theories, and thus requires a longer time to solve. In this paper, we compare the numerical accuracy of the solutions given by the three main types of one-step initial value solvers: Taylor’s Series Method, Euler’s Method and Runge-Kutta Fourth Order Method (RK4). The comparison of accuracy is obtained through comparing the solutions of ordinary differential equation given by these three methods. Furthermore, to verify the accuracy; we compare these numerical solutions with the exact solutions.

Keywords: Ordinary differential equations (ODE), Taylor’s Series Method, Euler’s Method, Runge-Kutta Fourth Order Method

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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Authors: V. Nagammai

Abstract:

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. Development of technology increases the complexity in IC manufacturing which may vary the power consumption, increase the size and latency period. Topology defines a number of connections between network. In this project, NoC topology is generated using atlas tool which will increase performance in turn determination of constraints are effective. The routing is performed by XY routing algorithm and wormhole flow control. In NoC topology generation, the value of power, area and latency are predetermined. In previous work, placement, routing and shortest path evaluation is performed using an algorithm called floor planning with cluster reconstruction and path allocation algorithm (FCRPA) with the account of 4 3x3 switch, 6 4x4 switch, and 2 5x5 switches. The usage of the 4x4 and 5x5 switch will increase the power consumption and area of the block. In order to avoid the problem, this paper has used one 8x8 switch and 4 3x3 switches. This paper uses IPRCA which of 3 steps they are placement, clustering, and shortest path evaluation. The placement is performed using min – cut placement and clustering are performed using an algorithm called cluster generation. The shortest path is evaluated using an algorithm called Dijkstra's algorithm. The power consumption of each block is determined. The experimental result shows that the area, power, and wire length improved simultaneously.

Keywords: application specific noc, b* tree representation, floor planning, t tree representation

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Authors: Satyam Raikwar, Thomas Herlitzius, Jens Fehrmann

Abstract:

In recent years, the autonomous navigation of orchard and field robots is an emerging technology of the mobile robotics in agriculture. One of the core aspects of autonomous navigation builds upon path planning, which is still a crucial issue. Generally, for simple representation, the path planning for a mobile robot is performed in a two-dimensional space, which creates a path between the start and goal point. This paper presents the automatic path planning approach for robots used in orchards and vineyards using occupancy grid maps with field consideration. The orchards and vineyards are usually structured environment and their topology is assumed to be constant over time; therefore, in this approach, an RGB image of a field is used as a working environment. These images undergone different image processing operations and then discretized into two-dimensional grid matrices. The individual grid or cell of these grid matrices represents the occupancy of the space, whether it is free or occupied. The grid matrix represents the robot workspace for motion and path planning. After the grid matrix is described, a probabilistic roadmap (PRM) path algorithm is used to create the obstacle-free path over these occupancy grids. The path created by this method was successfully verified in the test area. Furthermore, this approach is used in the navigation of the orchard robot.

Keywords: orchard robots, automatic path planning, occupancy grid, probabilistic roadmap

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Authors: A. Suresh, Sreehari Rao Patri, K. S. R. Krishnaprasad

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An ultra low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gain-enhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 µA. An undershoot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 µs for the output voltage undershoot case. The load regulation is of 2.77 µV/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: capacitor-less LDO, frequency compensation, transient response, latch, self-biased differential amplifier

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Authors: A. Khernane, N. Khelil, L. Djerou

Abstract:

The aim of this work is to study the numerical implementation of the Hilbert uniqueness method for the exact boundary controllability of Euler-Bernoulli beam equation. This study may be difficult. This will depend on the problem under consideration (geometry, control, and dimension) and the numerical method used. Knowledge of the asymptotic behaviour of the control governing the system at time T may be useful for its calculation. This idea will be developed in this study. We have characterized as a first step the solution by a minimization principle and proposed secondly a method for its resolution to approximate the control steering the considered system to rest at time T.

Keywords: boundary control, exact controllability, finite difference methods, functional optimization

Procedia PDF Downloads 314

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Nuttawoot Nupo, Sayan Panma

Abstract:

A semigroup S is said to be a left (right) zero semigroup if S satisfies the equation xy=x (xy=y) for all x,y in S. In addition, the semigroup S is called a left (right) group if S is isomorphic to the direct product of a group and a left (right) zero semigroup. The Cayley digraph Cay(S,A) of a semigroup S with a connection set A is defined to be a digraph with the vertex set S and the arc set E(Cay(S,A))={(x,xa) | x∈S, a∈A} where A is any subset of S. All sets in this research are assumed to be finite. Let D be a digraph together with a vertex set V and an arc set E. Let u and v be two different vertices in V and I a nonempty subset of V. The vertices u and v are said to be independent if (u,v)∉E and (v,u)∉E. The set I is called an independent set of D if any two different vertices in I are independent. The independence number of D is the maximum cardinality of an independent set of D. Moreover, the vertices u and v are said to be path independent if there is no dipath from u to v and there is no dipath from v to u. The set I is called a path independent set of D if any two different vertices in I are path independent. The path independence number of D is the maximum cardinality of a path independent set of D. In this research, we describe a lower bound and an upper bound of the independence number of Cayley digraphs of left groups and right groups. Some examples corresponding to those bounds are illustrated here. Furthermore, the exact value of the path independence number of Cayley digraphs of left groups and right groups are also presented.

Keywords: Cayley digraphs, independence number, left groups, path independence number, right groups

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Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

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This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver

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Authors: C. S. Bianca Sabrina, N. Egidio Raimundo, L. Alexandre Baratella, C. H. João Paulo

Abstract:

This paper aims to present a study, with the theoretical concepts and applications of the Quadcopter, using the MATLAB simulator. In order to use this tool, the study of the stability of the drone through a Proportional - Integral - Derivative (PID) controller will be presented. After the stability study, some tests are done on the simulator and its results will be presented. From the mathematical model, it is possible to find the Newton-Euler angles, so that it is possible to stabilize the quadcopter in a certain position in the air, starting from the ground. In order to understand the impact of the controllers gain values on the stabilization of the Euler-Newton angles, three conditions will be tested with different controller gain values.

Keywords: controllers, drones, quadcopter, stability

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Authors: Qing Lyu, Hang Zhu

Abstract:

Various flows in the network require to go through different types of middlebox. The improper placement of network middlebox and path assignment for flows could greatly increase the network latency and also decrease the performance of network. Minimizing the total end to end latency of all the ows requires to assign path for the incoming flows. In this paper, the flow path assignment problem in regard to the placement of various kinds of middlebox is studied. The flow path assignment problem is formulated to a linear programming problem, which is very time consuming. On the other hand, a naive greedy algorithm is studied. Which is very fast but causes much more latency than the linear programming algorithm. At last, the paper presents a heuristic algorithm named FPA, which takes bottleneck link information and estimated bandwidth occupancy into consideration, and achieves near optimal latency in much less time. Evaluation results validate the effectiveness of the proposed algorithm.

Keywords: flow path, latency, middlebox, network

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Authors: Zhiguo Shi, Cheng Ning Loong, Jiazeng Shan, Weichao Wu

Abstract:

This study proposes an equivalent circuit model to simulate the eddy current damping force with shaking table tests and finite element modeling. The model is firstly proposed and applied to a simple eddy current damper, which is modelled in ANSYS, indicating that the proposed model can simulate the eddy current damping force under different types of excitations. Then, a non-contact and friction-free eddy current damper is designed and tested, and the proposed model can reproduce the experimental observations. The excellent agreement between the simulated results and the experimental data validates the accuracy and reliability of the equivalent circuit model. Furthermore, a more complicated model is performed in ANSYS to verify the feasibility of the equivalent circuit model in complex eddy current damper, and the higher-order fractional model and viscous model are adopted for comparison.

Keywords: equivalent circuit model, eddy current damping, finite element model, shake table test

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

Abstract:

In this paper, we proposed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuit for latch-up immunity. The proposed circuit has a lower trigger voltage and a higher holding voltage characteristic by using the zener diode structure. These characteristics prevent latch-up problem in normal operating conditions. The proposed circuit was analyzed to figure out the electrical characteristics by the variations of design parameters D1, D2 and stack technology to obtain the n-fold electrical characteristics. The simulations are accomplished by using the Synopsys TCAD simulator. When using the stack technology, 2-stack has the holding voltage of 6.9V and 3-stack has the holding voltage of 10.9V.

Keywords: ESD, SCR, trigger voltage, holding voltage

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Authors: Alan C. Lin, Tsong Der Lin

Abstract:

This study proposes a deviation control method to add interpolation points to numerical control (NC) codes of five-axis machining in order to achieve the required machining accuracy. Specific research issues include: (1) converting machining data between the CL (cutter location) domain and the NC domain, (2) calculating the deviation between the deviated path and the linear path, (3) finding interpolation points, and (4) determining tool orientations for the interpolation points. System implementation with practical examples will also be included to highlight the applicability of the proposed methodology.

Keywords: CAD/CAM, cutter path, five-axis machining, numerical control

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Authors: Amit Kumar Sinha

Abstract:

A coal preparation plant typically operates with multiple beneficiation circuits to process individual size fractions of coal obtained from mine so that the targeted overall plant efficiency in terms of yield and ash is achieved. Conventional coal beneficiation plant in India or overseas operates generally in two methods of processing; coarse beneficiation with treatment in dense medium cyclones or in baths and fines beneficiation with treatment in flotation cell. This paper seeks to address the proven application of intermediate circuit along with coarse and fines circuit in Jamadoba New Coal Preparation Plant of capacity 2 Mt/y to treat -0.5 mm+0.25 mm size particles in reflux classifier. Previously this size of particles was treated directly in Flotation cell which had operational and metallurgical limitations which will be discussed in brief in this paper. The paper also details test work results performed on the representative samples of TSL coal washeries to determine the top size of intermediate and fines circuit and discusses about the overlapping process of intermediate circuit and how it is process wise suitable to beneficiate misplaced particles from coarse circuit and fines circuit. This paper also compares the separation efficiency (Ep) of various intermediate circuit process equipment and tries to validate the use of reflux classifier over fine coal DMC or spirals. An overview of Modern coal preparation plant treating Indian coal especially Washery Grade IV coal with reference to Jamadoba New Coal Preparation Plant which was commissioned in 2018 with basis of selection of equipment and plant profile, application of reflux classifier in intermediate circuit and process design criteria is also outlined in this paper.

Keywords: intermediate circuit, overlapping process, reflux classifier

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Authors: Ali Mustafa Elshawesh, Mohamed Abdulali

Abstract:

The paper presents an approach to dimension circuit switched networks and find the relationship between the parameters of the circuit switched networks on the condition of specific probability of call blocking. Our work is creating a Simulation code based on Erlang (B) formula to draw graphs which show two curves for each graph; one of simulation and the other of calculated. These curves represent the relationships between average number of calls and average call duration with the probability of call blocking. This simulation code facilitates to select the appropriate parameters for circuit switched networks.

Keywords: Erlang B formula, call blocking, telephone system dimension, Markov model, link capacity

Procedia PDF Downloads 566

Authors: Sherif M. Hafez, Remon F. Aziz, May S. A. Elalim

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Project managers today rely on scheduling tools based on the Critical Path Method (CPM) to determine the overall project duration and the activities’ float times which lead to greater efficiency in planning and control of projects. CPM was useful for scheduling construction projects, but researchers had highlighted a number of serious drawbacks that limit its use as a decision support tool and lacks the ability to clearly record and represent detailed information. This paper discusses the drawbacks of CPM as a scheduling technique and presents a modified critical path method (CPM) model which is called critical path segments (CPS). The CPS scheduling mechanism addresses the problems of CPM in three ways: decomposing the activity duration of separated but connected time segments; all relationships among activities are converted into finish–to–start relationship; and analysis and calculations are made with forward path. Sample cases are included to illustrate the shortages in CPM, CPS full analysis and calculations are explained in details, and how schedules can be handled better with the CPS technique.

Keywords: construction management, scheduling, critical path method, critical path segments, forward pass, float, project control

Procedia PDF Downloads 329

Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

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Authors: M. Abuziarov

Abstract:

The designed complex is intended for the numerical simulation of fast dynamic processes of interaction of heterogeneous environments susceptible to the significant formability. The main challenges in solving such problems are associated with the construction of the numerical meshes. Currently, there are two basic approaches to solve this problem. One is using of Lagrangian or Lagrangian Eulerian grid associated with the boundaries of media and the second is associated with the fixed Eulerian mesh, boundary cells of which cut boundaries of the environment medium and requires the calculation of these cut volumes. Both approaches require the complex grid generators and significant time for preparing the code’s data for simulation. In this codes these problems are solved using two grids, regular fixed and mobile local Euler Lagrange - Eulerian (ALE approach) accompanying the contact and free boundaries, the surfaces of shock waves and phase transitions, and other possible features of solutions, with mutual interpolation of integrated parameters. For modeling of both liquids and gases, and deformable solids the Godunov scheme of increased accuracy is used in Lagrangian - Eulerian variables, the same for the Euler equations and for the Euler- Cauchy, describing the deformation of the solid. The increased accuracy of the scheme is achieved by using 3D spatial time dependent solution of the discontinuity problem (3D space time dependent Riemann's Problem solver). The same solution is used to calculate the interaction at the liquid-solid surface (Fluid Structure Interaction problem). The codes does not require complex 3D mesh generators, only the surfaces of the calculating objects as the STL files created by means of engineering graphics are given by the user, which greatly simplifies the preparing the task and makes it convenient to use directly by the designer at the design stage. The results of the test solutions and applications related to the generation and extension of the detonation and shock waves, loading the constructions are presented.

Keywords: fluid structure interaction, Riemann's solver, Euler variables, 3D codes

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