Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 60061
Analysis of Stacked SCR-Based ESD Protection Circuit with Low Trigger Voltage and Latch-Up Immunity

Authors: Yong-Seo Koo, Kyoung-Il Do, Min-ju Kwon, Jun-Geol Park, Kyung-Hyun Park

Abstract:

In this paper, we proposed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuit for latch-up immunity. The proposed circuit has a lower trigger voltage and a higher holding voltage characteristic by using the zener diode structure. These characteristics prevent latch-up problem in normal operating conditions. The proposed circuit was analyzed to figure out the electrical characteristics by the variations of design parameters D1, D2 and stack technology to obtain the n-fold electrical characteristics. The simulations are accomplished by using the Synopsys TCAD simulator. When using the stack technology, 2-stack has the holding voltage of 6.9V and 3-stack has the holding voltage of 10.9V.

Keywords: holding voltage, ESD, SCR, trigger voltage

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