Search results for: high gain power amplifier

Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

Abstract:

This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

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Authors: M. H. Al-Mansoori, W. S. Al-Ghaithi, F. N. Hasoon

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In this paper, we experimentally investigate the performance of an efficient high gain triple-pass L-band Erbium-Doped Fiber (EDF) amplifier structure with a single pump source. The amplifier gain and noise figure variation with EDF pump power, input signal power and wavelengths have been investigated. The generated backward Amplified Spontaneous Emission (ASE) noise of the first amplifier stage is suppressed by using a tunable band-pass filter. The amplifier achieves a signal gain of 55 dB with low noise figure of 3.8 dB at -50 dBm input signal power. The amplifier gain shows significant improvement of 12.8 dB compared to amplifier structure without ASE suppression.

Keywords: optical amplifiers, EDFA, L-band, optical networks

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Authors: Alpana Agarwal, Akhil Sharma

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This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter

Procedia PDF Downloads 264

Authors: Tian-Wei Huang, Wei-Ting Bai, Yu-Tung Cheng, Jeng-Han Tsai

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In this paper, a 1-stage 6-section conventional distributed amplifier (CDA) structure distributed power amplifier (DPA) fabricated in a 28-nm HPC+ 1P9M CMOS process is proposed. The transistor size selection is introduced to achieve broadband power matching and thus remains a high flatness output power and power added efficiency (PAE) within the bandwidth. With the inductive peaking technique, the high-frequency pole appears and the high-frequency gain is increased; the gain flatness becomes better as well. The inductive elements used to form an artificial transmission line are built up with a floating ground coplanar waveguide plane (CPWFG) rather than a microstrip line, coplanar waveguide (CPW), or spiral inductor to get better performance. The DPA achieves 12.6 dB peak gain at 52.5 GHz with 2.9 to 64.9 GHz 3-dB bandwidth. The Psat is 11.4 dBm with PAEMAX of 10.6 % at 25 GHz. The output 1-dB compression point power is 9.8 dBm.

Keywords: distributed power amplifier (DPA), gain bandwidth (GBW), floating ground CPW, inductive peaking, 28-nm, CMOS, 5G.

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

Abstract:

This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

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A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

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Authors: Karandeep Kaur

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This paper presents the design of power amplifier (PA) for mmWave communication systems. The designed amplifier uses GlobalFoundries 22 FDX technology and works at an operational frequency of 140 GHz in the D-Band. With a supply voltage of 0.8V for the super low threshold voltage transistors, the amplifier is biased in class AB and has a total current consumption of 50 mA. The measured saturated output power from the power amplifier is 5.6 dBm with an output-referred 1dB-compression point of 1.6dBm. The measured gain of PA is 19 dB with 3 dB-bandwidth ranging from 120 GHz to 140 GHz. The chip occupies an area of 795µm × 410µm.

Keywords: mmWave communication system, power amplifiers, 22FDX, D-Band, cross-coupled capacitive neutralization

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Authors: Belloui Bouzid

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In this paper, broadband design of erbium doped fiber amplifier (EDFA) is demonstrated and proved experimentally. High and broad gain is covered in C and L bands. The used technique combines, in one configuration, two double passes with split band structure for the amplification of two traveled signals one for the C band and the other for L band. This new topology is to investigate the trends of high gain and wide amplification at different status of pumping power, input wavelength, and input signal power. The presented paper is to explore the performance of EDFA gain using what it can be called double pass double branch wide band amplification configuration. The obtained results show high gain and wide broadening range of 44.24 dB and 80 nm amplification respectively.

Keywords: erbium doped fiber amplifier, erbium doped fiber laser, optical amplification, fiber laser

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Authors: A. Anitha, M. Aishwariya

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The realization of truly ubiquitous wireless sensor networks (WSN) demands Ultra-low power wireless communication capability. Because the radio transceiver in a wireless sensor node consumes more power when compared to the computation part it is necessary to reduce the power consumption. Hence, a low power transceiver is designed and implemented in a 120 nm CMOS technology for wireless sensor nodes. The power consumption of the transceiver is reduced still by maintaining the sensitivity. The transceiver designed combines the blocks including differential oscillator, mixer, envelope detector, power amplifiers, and LNA. RF signal modulation and demodulation is carried by On-Off keying method at 2.4 GHz which is said as ISM band. The transmitter demonstrates an output power of 2.075 mW while consuming a supply voltage of range 1.2 V-5.0 V. Here the comparison of LNA and power amplifier is done to obtain an amplifier which produces a high gain of 1.608 dB at receiver which is suitable to produce a desired sensitivity. The multistage RF amplifier is used to improve the gain at the receiver side. The power dissipation of the circuit is in the range of 0.183-0.323 mW. The receiver achieves a sensitivity of about -95 dBm with data rate of 1 Mbps.

Keywords: CMOS, envelope detector, ISM band, LNA, low power electronics, PA, wireless transceiver

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Authors: Abdalla Mohamed Eblabla

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Due to the high increase and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E, and F are the main techniques for realizing power amplifiers. An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), gallium nitride (GaN), Agilent’s Advanced Design System (ADS), lumped elements

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Authors: Jan Doutreloigne

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The main goal of this paper is to develop a switching amplifier with optimized power efficiency for analog signals with a very high crest factor such as audio or DSL signals. Theoretical calculations show that a switching amplifier architecture based on multi-level pulse width modulation outperforms all other types of linear or switching amplifiers in that respect. Simulations on a 2 W multi-level switching audio amplifier, designed in a 50 V 0.35 mm IC technology, confirm its superior performance in terms of power efficiency. A real silicon implementation of this audio amplifier design is currently underway to provide experimental validation.

Keywords: audio amplifier, multi-level switching amplifier, power efficiency, pulse width modulation, PWM, self-oscillating amplifier

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Authors: Meng-Jie Hsiao, Cam Nguyen

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Wide-band devices in Ku band (12-18 GHz) and K band (18-27 GHz) have received significant attention for high-data-rate communications and high-resolution sensing. Especially, devices operating around 24 GHz is attractive due to the 24-GHz unlicensed applications. One of the most important components in RF systems is power amplifier (PA). Various PAs have been developed in the Ku and K bands on GaAs, InP, and silicon (Si) processes. Although the PAs using GaAs or InP process could have better power handling and efficiency than those realized on Si, it is very hard to integrate the entire system on the same substrate for GaAs or InP. Si, on the other hand, facilitates single-chip systems. Hence, good PAs on Si substrate are desirable. Especially, Si-based PA having good linearity is necessary for next generation communication protocols implemented on Si. We report a 16.5 to 25.5 GHz Si-based PA having flat saturated power of 19.5 ± 1.5 dBm, output 1-dB power compression (OP1dB) of 16.5 ± 1.5 dBm, and 15-23 % power added efficiency (PAE). The PA consists of a drive amplifier, two main amplifiers, and lump-element Wilkinson power divider and combiner designed and fabricated in TowerJazz 0.18µm SiGe BiCMOS process having unity power gain frequency (fMAX) of more than 250 GHz. The PA is realized as a cascode amplifier implementing both heterojunction bipolar transistor (HBT) and n-channel metal–oxide–semiconductor field-effect transistor (NMOS) devices for gain, frequency response, and linearity consideration. Particularly, a body-floating technique is utilized for the NMOS devices to improve the voltage swing and eliminate parasitic capacitances. The developed PA has measured flat gain of 20 ± 1.5 dB across 16.5-25.5 GHz. At 24 GHz, the saturated power, OP1dB, and maximum PAE are 20.8 dBm, 18.1 dBm, and 23%, respectively. Its high performance makes it attractive for use in Ku/K-band, especially 24 GHz, communication and radar systems. This paper was made possible by NPRP grant # 6-241-2-102 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.

Keywords: power amplifiers, amplifiers, communication systems, radar systems

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Authors: Ow Tze Weng, Suhaila Isaak, Yusmeeraz Yusof

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The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability, especially in the most common electrocardiogram (ECG) monitoring system. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip (SoC) is increasing in exponential way, the front end ECG sensors are still suffering from flicker noise for low frequency cardiac signal acquisition, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a high performance CMOS amplifier for ECG sensors that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13 µm CMOS technology from Silterra, the simulation results show that this front end circuit can achieve a very low input referred noise of 1 pV/√Hz and high common mode rejection ratio (CMRR) of 174.05 dB. It also gives voltage gain of 75.45 dB with good power supply rejection ratio (PSSR) of 92.12 dB. The total power consumption is only 3 µW and thus suitable to be implemented with further signal processing and classification back end for low power biomedical SoC.

Keywords: CMOS, ECG, amplifier, low power

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Authors: Maninder Kaur Gill, Alpana Agarwal

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It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device Under Test (DUT), open loop voltage gain, operational amplifier, test circuit

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Authors: Noha Al Majid, Said Mazer, Moulhime El Bekkali, Catherine Algani, Mahmoud Mehdi

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A low noise figure (NF) and high linearity V-band Low Noise Amplifier (LNA) is reported in this article. The LNA compromises a three-stage cascode configuration. This LNA will be used as a part of a WPAN (Wireless Personal Area Network) receiver in the millimeter-wave band at 60 GHz. It is designed according to the MMIC technology (Monolithic Microwave Integrated Circuit) in PH 15 process from UMS foundry and uses a 0.15 μm GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor). The particularity of this LNA compared to other LNAs in literature is its very low noise figure which is equal to 1 dB and its high linearity (IIP3 is about 22 dB). The LNA consumes 0.24 Watts, achieving a high gain which is about 23 dB, an input return loss better than -10 dB and an output return loss better than -8 dB.

Keywords: low noise amplifier, V-band, MMIC technology, LNA, amplifier, cascode, pseudomorphic high electron mobility transistor (PHEMT), high linearity

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Hassan Jassim Motlak

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A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: A. Suresh, Sreehari Rao Patri, K. S. R. Krishnaprasad

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An ultra low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gain-enhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 µA. An undershoot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 µs for the output voltage undershoot case. The load regulation is of 2.77 µV/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: capacitor-less LDO, frequency compensation, transient response, latch, self-biased differential amplifier

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Authors: Mantas Sakalas, Paulius Sakalas

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This paper presents an analysis and design of a ultrawideband 1.8GHz to 43GHz Low Noise Amplifier (LNA) in 0.1 μm Galium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT) technology. The feedback based bandwidth extension techniques is analyzed and based on the outcome, a two stage LNA is designed. The impedance fine tuning is implemented by using Transmission Line (TL) structures. The measured performance shows a good agreement with simulation results and an outstanding wideband noise matching. The measured small signal gain was 12 dB, whereas a 3 dB gain flatness in range from 1.8 - 43 GHz was reached. The noise figure was below 4 dB almost all over the entire frequency band of 1.8GHz to 43GHz, the output power at 1 dB compression point was 6 dBm and the DC power consumption was 95 mW. To the best knowledge of the authors the designed LNA outperforms the State of the Art (SotA) reported LNA designs in terms of combined parameters of noise figure within the addressed ultra-wide 3 dB bandwidth, linearity and DC power consumption.

Keywords: feedback amplifiers, GaAs pHEMT, monolithic microwave integrated circuit, LNA, noise matching

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Authors: Surinder Singh, Adish Bindal

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The effects of the pumping wavelength and their power on the gain flattening of a fiber Raman amplifier (FRA) are investigated. The multi-wavelength pumping scheme is utilized to achieve gain flatness in FRA. It is proposed that gain flatness becomes better with increase in number of pumping wavelengths applied. We have achieved flat gain with 0.27 dB fluctuation in a spectral range of 1475-1600 nm for a Raman fiber length of 10 km by using six pumps with wavelengths with in the 1385-1495 nm interval. The effect of multi-wavelength pumping scheme on gain saturation in FRA is also studied. It is proposed that gain saturation condition gets improved by using this scheme and this scheme is more useful for higher spans of Raman fiber length.

Keywords: FRA, WDM, pumping, flat gain

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity, and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: LDMOS, amplifier, back-off, bias circuit

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Authors: Yo-Sheng Lin, Chien-Chin Wang, Yun-Wen Lin, Chien-Yo Lee

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A wide band power amplifier (PA) for 60 GHz and 77 GHz direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with a wide band T-type input-matching network and inductive interconnection and load, followed by a common-source (CS) gain stage and a CS output stage. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wide band input and output impedance matching to 100 ohm. This in turn results in further PSAT and PAE enhancement. The PA consumes 92.2 mW and achieves maximum power gain (S21) of 23.3 dB at 56 GHz, and S21 of 21.7 dB and 14 dB, respectively, at 60 GHz and 77 GHz. In addition, the PA achieves excellent saturated output power (PSAT) of 10.6 dB and maximum power added efficiency (PAE) of 12.3% at 60 GHz. At 77 GHz, the PA achieves excellent PSAT of 10.4 dB and maximum PAE of 6%. These results demonstrate the proposed wide band PA architecture is very promising for 60 GHz wireless personal local network (WPAN) and 77 GHz automobile radar systems.

Keywords: 60 GHz, 77 GHz, PA, WPAN, automotive radar

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Authors: Yo-Sheng Lin, Jen-How Lee, Chien-Chin Wang

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A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA), and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential (STD) converter, an LO Marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4 GHz to 65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are -33.1 dBm and -23.3 dBm, respectively, at 60 GHz. These results demonstrate the proposed receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications.

Keywords: CMOS, 60 GHz, direct-conversion transceiver, LNA, down-conversion mixer, marchand balun, current-reused

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Authors: S. Aisyah Azizan, M. Syafiq Azmi, Yuki Harada, Yoshinobu Maeda, Takaomi Matsutani

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We introduced an all-optical multi-casting characteristics with wavelength conversion based on a novel all-optical triode using negative feedback semiconductor optical amplifier. This study was demonstrated with a transfer speed of 10 Gb/s to a non-return zero 231-1 pseudorandom bit sequence system. This multi-wavelength converter device can simultaneously provide three channels of output signal with the support of non-inverted and inverted conversion. We studied that an all-optical multi-casting and wavelength conversion accomplishing cross gain modulation is effective in a semiconductor optical amplifier which is effective to provide an inverted conversion thus negative feedback. The relationship of received power of back to back signal and output signals with wavelength 1535 nm, 1540 nm, 1545 nm, 1550 nm, and 1555 nm with bit error rate was investigated. It was reported that the output signal wavelengths were successfully converted and modulated with a power penalty of less than 8.7 dB, which the highest is 8.6 dB while the lowest is 4.4 dB. It was proved that all-optical multi-casting and wavelength conversion using an optical triode with a negative feedback by three channels at the same time at a speed of 10 Gb/s is a promising device for the new wavelength conversion technology.

Keywords: cross gain modulation, multicasting, negative feedback optical amplifier, semiconductor optical amplifier

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Authors: Moez ul Hassan, Bushra Noman, Sarmad Hameed, Shahab Mehmood, Asma Bashir

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The importance of Noble prize winning “Patch Clamp Technique” is well documented. However, Patch Clamp Technique is very expensive and hence hinders research in developing countries. In this paper, detection, processing and recording of ultra low current from induced cells by using transimpedence amplifier is described. The sensitivity of the proposed amplifier is in the range of femto amperes (fA). Capacitive-feedback is used with active load to obtain a 20MΩ transimpedance gain. The challenging task in designing includes achieving adequate performance in gain, noise immunity and stability. The circuit designed by the authors was able to measure current in the rangeof 300fA to 100pA. Adequate performance shown by the amplifier with different input current and outcome result was found to be within the acceptable error range. Results were recorded using LabVIEW 8.5®for further research.

Keywords: drug discovery, ionic current, operational amplifier, patch clamp

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Authors: Nidhi Vijay, A. K. Sharma

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Many industrial applications require power from dc source. DC-DC boost converters are now being used all over the world for rapid transit system. Although these provide high efficiency, smooth control, fast response and regeneration, conventional DC-DC boost converters are unable to provide high step up voltage gain due to effect of power switches, rectifier diodes and equivalent series resistance of inductor and capacitor. This paper proposes new transformerless dc-dc converters to achieve high step up voltage gain as compared to the conventional converter without an extremely high duty ratio. Only one power stage is used in this converter. Steady-state analysis of voltage gain is discussed in brief. Finally, a comparative analysis is given in order to verify the results.

Keywords: MATLAB, DC-DC boost converter, voltage gain, voltage stress

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Authors: Abdelhamid Louliej, Younes Jabrane

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Satellites are becoming indispensable assets to fifth-generation (5G) new radio architecture, complementing wireless and terrestrial communication links. The combination of satellites and 5G architecture allows consumers to access all next-generation services anytime, anywhere, including scenarios, like traveling to remote areas (without coverage). Nevertheless, this solution faces several challenges, such as a significant propagation delay, Doppler frequency shift, and high Peak-to-Average Power Ratio (PAPR), causing signal distortion due to the non-linear saturation of the High-Power Amplifier (HPA). To compensate for HPA non-linearity in 5G satellite transmission, an efficient pre-distorter scheme using Neural Networks (NN) is proposed. To assess the proposed NN pre-distorter, two types of HPA were investigated: Travelling Wave Tube Amplifier (TWTA) and Solid-State Power Amplifier (SSPA). The results show that the NN pre-distorter design presents EVM improvement by 95.26%. NMSE and ACPR were reduced by -43,66 dB and 24.56 dBm, respectively. Moreover, the system suffers no degradation of the Bit Error Rate (BER) for TWTA and SSPA amplifiers.

Keywords: satellites, 5G, neural networks, HPA, TWTA, SSPA, EVM, NMSE, ACPR

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Authors: Hyunwon Moon

Abstract:

It is necessary to realize new biomedical wireless communication systems which send the signals collected from various bio sensors located at human body in order to monitor our health. Also, it should seamlessly connect to the existing wireless communication systems. A 5.8 GHz ISM band low power RF front-end receiver for a biomedical wireless communication system is implemented using a 0.5 µm SiGe BiCMOS process. To achieve low power RF front-end, the current optimization technique for selecting device size is utilized. The implemented low noise amplifier (LNA) shows a power gain of 9.8 dB, a noise figure (NF) of below 1.75 dB, and an IIP3 of higher than 7.5 dBm while current consumption is only 6 mA at supply voltage of 2.5 V. Also, the performance of a down-conversion mixer is measured as a conversion gain of 11 dB and SSB NF of 10 dB.

Keywords: biomedical, LNA, mixer, receiver, RF front-end, SiGe

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Authors: Shreyas Srinivas Rangan, Jurgis Porins

Abstract:

The internet traffic has increased exponentially due to the high demand for data rates by the users, and the constantly increasing metro networks and access networks are focused on improving the maximum transmit distance of the long-reach optical networks. One of the common methods to improve the maximum transmit distance of the long-reach optical networks at the component level is to use broadband optical amplifiers. The Erbium Doped Fiber Amplifier (EDFA) provides high amplification with low noise figure but due to the characteristics of EDFA, its operation is limited to C-band and L-band. In contrast, the Raman amplifier exhibits a wide amplification spectrum, and negative noise figure values can be achieved. To obtain such results, high powered pumping sources are required. Operating Raman amplifiers with such high-powered optical sources may cause fire hazards and it may damage the optical system. In this paper, we implement a hybrid optical amplifier configuration. EDFA and Raman amplifiers are used in this hybrid setup to combine the advantages of both EDFA and Raman amplifiers to improve the reach of the system. Using this setup, we analyze the maximum transmit distance of the network by obtaining a correlation diagram between the length of the single-mode fiber (SMF) and the Bit Error Rate (BER). This hybrid amplifier configuration is implemented in a Wavelength Division Multiplexing (WDM) system with a BER of 10⁻⁹ by using NRZ modulation format, and the gain uniformity noise ratio (signal-to-noise ratio (SNR)), the efficiency of the pumping source, and the optical signal gain efficiency of the amplifier are studied experimentally in a mathematical modelling environment. Numerical simulations were implemented in RSoft OptSim simulation software based on the nonlinear Schrödinger equation using the Split-Step method, the Fourier transform, and the Monte Carlo method for estimating BER.

Keywords: Raman amplifier, erbium doped fibre amplifier, bit error rate, hybrid optical amplifiers

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