Search results for: Verilog hardware descriptive language

Authors: Jong-Bae Lee, Seongsoo Lee

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Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: local interconnect network, controller, transceiver, processor

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Authors: Rozita Borhan, Lam Kien Sieng

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This paper describes I²C Slave implementation using I²C master obtained from the OpenCores website. This website provides free Verilog and VHDL Codes to users. The design implementation for the I²C slave is in Verilog Language and uses EDA tools for ASIC design known as ModelSim from Mentor Graphic. This tool is used for simulation and verification purposes. Common application for this I²C Master-Slave integration is also included. This paper also addresses the advantages and limitations of the said design.

Keywords: I²C, master, OpenCores, slave, Verilog, verification

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Authors: Jugal Bhandari, K. Hari Priya

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The ECG signal provides important clinical information which could be used to pretend the diseases related to heart. Accordingly, delineation of ECG signal is an important task. Whereas delineation of P and T waves is a complex task. This paper deals with the Study of ECG signal and analysis of signal by means of Verilog Design of efficient filters and MATLAB tool effectively. It includes generation and simulation of ECG signal, by means of real time ECG data, ECG signal filtering and processing by analysis of different algorithms and techniques. In this paper, we design a basic particle filter which generates a dynamic model depending on the present and past input samples and then produces the desired output. Afterwards, the output will be processed by MATLAB to get the actual shape and accurate values of the ranges of P-wave and T-wave of ECG signal. In this paper, Questasim is a tool of mentor graphics which is being used for simulation and functional verification. The same design is again verified using Xilinx ISE which will be also used for synthesis, mapping and bit file generation. Xilinx FPGA board will be used for implementation of system. The final results of FPGA shall be verified with ChipScope Pro where the output data can be observed.

Keywords: ECG, MATLAB, Bayesian filtering, particle filter, Verilog hardware descriptive language

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Authors: N. N. Joshi, G. K. Singh

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We present the stimuli implementation and verification of a Programmable Peripheral Interface (PPI) 8255. It involves a designing and verification of configurable intellectual property (IP) module of PPI protocol using Verilog HDL for implementation part and System Verilog for verification. The overview of the PPI-8255 presented then the design specification implemented for the work following the functional description and pin configuration of PPI-8255. The coverage report of design shows that our design and verification environment covered 100% functionality in accordance with the design specification generated by the Questa Sim 10.0b.

Keywords: Programmable Peripheral Interface (PPI), verilog HDL, system verilog, questa sim

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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Authors: Jongbae Lee, Seongsoo Lee

Abstract:

Modern sensors often embed small-size digital controller for sensor control, value calibration, and signal processing. These sensors require digital data communication with host microprocessors, but conventional digital communication protocols are too heavy for price reduction. SAE J2716 SENT (single edge nibble transmission) protocol transmits direct digital waveforms instead of complicated analog modulated signals. In this paper, a SENT interface is designed in Verilog HDL (hardware description language) and implemented in FPGA (field-programmable gate array) evaluation board. The designed SENT interface consists of frame encoder/decoder, configuration register, tick period generator, CRC (cyclic redundancy code) generator/checker, and TX/RX (transmission/reception) buffer. Frame encoder/decoder is implemented as a finite state machine, and it controls whole SENT interface. Configuration register contains various parameters such as operation mode, tick length, CRC option, pause pulse option, and number of nibble data. Tick period generator generates tick signals from input clock. CRC generator/checker generates or checks CRC in the SENT data frame. TX/RX buffer stores transmission/received data. The designed SENT interface can send or receives digital data in 25~65 kbps at 3 us tick. Synthesized in 0.18 um fabrication technologies, it is implemented about 2,500 gates.

Keywords: digital sensor interface, SAE J2716, SENT, verilog HDL

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Authors: Diyah Atiek Mustikawati

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Language register refers to a variety of a language used for particular purpose or in a particular social setting. Language register also means as a concept of adapting one’s use of language to conform to standards or tradition in a given professional or social situation. This descriptive study tends to discuss about the form of language register in transportation aspect, factors, also the function of use it. Mostly, language register in transportation aspect uses short sentences in form of informal register. The factor caused language register used are speaker, word choice, background of language. The functions of language register in transportations aspect are to make communication between crew easily, also to keep safety when they were in bad condition. Transportation language register developed naturally as one of variety of language used.

Keywords: language register, language variety, communication, transportation

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: Youngjae Jin, Daeshik Kim

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This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in Verilog HDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

Keywords: auto-encoder, behavior model simulation, digital hardware design, pre-route simulation, Unsupervised feature learning

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Authors: Vladimir Simovic, Matija Varga, Robert Svetlacic

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Scientific work analytically explores and demonstrates techniques that can animate objects and geometric characters using CSS3 language by applying proper formatting and positioning of elements. This paper presents examples of optimum application of the CSS3 descriptive language when generating general web animations (e.g., billiards and movement of geometric characters, etc.). The paper presents analytically, the optimal development and animation design with the frames within which the animated objects are. The originally developed content is based on the upgrading of existing CSS3 descriptive language animations with more complex syntax and project-oriented work. The purpose of the developed animations is to provide an overview of the interactive features of CSS3 descriptive language design for computer games and the animation of important analytical data based on the web view. It has been analytically demonstrated that CSS3 as a descriptive language allows inserting of various multimedia elements into websites for public and internal sites.

Keywords: web animation recording, KML GML HTML5 forms, Cascading Style Sheets 3, Google Earth Professional

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Authors: K. K. Soundra Pandian, Bhupendra Gupta

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In the modern era, as the application data’s are massive and complex, it needs to be secured from the adversary attack. In this context, a non-recursive key based integrated spritz stream cipher with the circulant hash function using delayed feedback with carry shift register (d-FCSR) is proposed in this paper. The novelty of this proposed stream cipher algorithm is to engender the improved keystream using d-FCSR. The proposed algorithm is coded using Verilog HDL to produce dynamic binary key stream and implemented on commercially available FPGA device Virtex 5 xc5vlx110t-2ff1136. The implementation of stream cipher using d-FCSR on the FPGA device operates at a maximum frequency of 60.62 MHz. It achieved the data throughput of 492 Mbps and improved in terms of efficiency (throughput/area) compared to existing techniques. This paper also briefs the cryptanalysis of proposed circulant hash value based spritz stream cipher using d-FCSR is against the adversary attack on a hardware platform for the hardware based cryptography applications.

Keywords: cryptography, circulant function, field programmable gated array, hash value, spritz stream cipher

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Authors: Longfei Wang, Selçuk Köse

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Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Oluwabukola Oluwaseyi Oduntan

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The English Language plays a central and strategic role in the school system because almost all the school subjects are taught using the English language. However, students’ achievement in this subject at senior secondary school is not encouraging. Therefore, this study examined the effects of oral-written mode of assessment on senior secondary school students’ achievement in a descriptive essay. It also examined the moderating effects of students’ gender and class on students’ achievement in a descriptive essay. The study adopted a pretest-posttest, control group, quasi-experimental design with a 2x2x3 factorial matrix. The participant consisted of 140 Senior Secondary II students drawn from four intact classes from four schools randomly selected from four Local Government Areas randomly selected from Oyo town in Oyo State. Two schools were assigned each to the treatment group and the control group. The following instruments were used for the study: Descriptive Essay Achievement Test (r = 0.78); Descriptive Achievement Test Marking Scheme; Check List of Oral-Written Assessment and Teachers’ Instructional Guide on Descriptive Essay (r = 0.81). Seven null hypotheses guided the study and tested at 0.05 level of significance. Data were analyzed using Analysis of Covariance, Estimated Marginal Means and Scheffe post-hoc test. The result revealed that treatment had a significant main effect on students’ achievement in descriptive essay (F(1,127) = 25.407, P < .05, η2 = .167). Students exposed to oral-written assessment had a higher achievement scores ((x ) ̅= 36.15) than those exposed to written assessment ((x ) ̅= 28.55). There was no significant main effect of gender on students’ achievement in descriptive essay (F₍₁, ₁₂₇₎ = .349, P > .05, η2 = .003). The result also revealed that the effects of class was not significant on students’ students’ achievement in descriptive essay (F₍₁, ₁₂₇₎ = .679, P > .05, η2 = .006). Oral-written mode of assessment enhanced students’ achievement in a descriptive essay. It is, therefore, recommended that teachers and curriculum developers should adopt the use of oral-written assessment for better improvement of students’ achievement in a descriptive essay.

Keywords: class, gender, oral-written assessment, written assessment

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Authors: Inuwa Danladi Bawa

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One of the challenges of African states in the development of education in the past and the present is the problem of literacy. Literacy in the first language is seen as a strong base for the development of second language; they are mostly the language of education. Language development is an offshoot of language planning; so the need to develop literacy in both first and second language affects language education and predicts the extent of achievement of the entire education sector. The need to balance literacy acquisition in first language for good conditioning the acquisition of second language is paramount. Likely constraints that includes; non-standardization, underdeveloped and undeveloped first languages are among many. Solutions to some of these include the development of materials and use of the stages and levels of literacy acquisition. This is with believed that a child writes well in second language if he has literacy in the first language.

Keywords: first language, second language, literacy, english language, linguistics

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Authors: Jun Young Moon, Hyeonggeon Lee, Jong Tae Kim

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In this paper, we present Cortex-M3 based virtual platform which can virtualize wearable hardware platform and evaluate hardware performance. Cortex-M3 is very popular microcontroller in wearable devices, hardware sensors and display devices. This platform can be used to implement software layer for specific hardware architecture. By using the proposed platform the software development process can be parallelized with hardware development process. We present internal mechanism to implement the proposed virtual platform and describe how to use the proposed platform to develop software by using case study which is low cost wearable device that uses Cortex-M3.

Keywords: electronic system level design, software development, virtual platform, wearable device

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Authors: Ugwu Elias Ikechukwu

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Discussions on bilingualism have always dwelt on how the mother tongue interferes with the target language. This interference is considered a serious problem in second language learning. Usually, the interference has been phonological. But the objective of this research is to explore how the target language interferes with the mother tongue. In the case of the Igbo language, it interferes with English mostly at the phonological level while English interferes with Igbo at the realm of vocabulary. The result is a new language \"Engligbo\" which is a hybrid of English and Igbo. The Igbo language spoken by about 25 million people is one of the three most prominent languages in Nigeria. This paper discusses the phenomenal Engligbo, and other implications for Igbo learners of English. The method of analysis is descriptive. A number of recommendations were made that would help teachers handle problems arising from such mutual interferences.

Keywords: reciprocal interferences, bilingualism, implications, language pedagogy

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Authors: Joy Aworookoroh

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Writing is one of the active skills in language learning. Students of English as a foreign language are expected to write efficiently and proficiently in the language; however, there are usually challenges to optimal performance and competence in writing. Errors, on the other hand, in a foreign language learning situation are more positive than negative as they provide the basis for solving the limitations of the students. This paper investigates the situation in the Department of English, Taraba State University Jalingo. Students are administered a descriptive writing test across different levels of study. The target students are multilingual with an L1 of either Kuteb, Hausa or Junkun languages. The essays are accessed to identify the different kinds of errors in them alongside the classification of the order. Errors of correctness, clarity, engagement, and delivery were identified. However, the study identified that the degree of errors reduces alongside the experience and exposure of the students to an EFL classroom.

Keywords: errors, writings, descriptive essay, multilingual

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Authors: Zhang Xingnan, Huang Jingjia, Feng Yue, Burra Venkata Durga Kumar

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This paper proposes a comprehensive approach to mitigate ROP (Return-Oriented Programming) attacks by combining internal operating system protection mechanisms and hardware-assisted techniques. Through extensive literature review, we identify the effectiveness of ASLR (Address Space Layout Randomization) and LBR (Last Branch Record) in preventing ROP attacks. We present a process involving buffer overflow detection, hardware-assisted ROP attack detection, and the use of Turing detection technology to monitor control flow behavior. We envision a specialized tool that views and analyzes the last branch record, compares control flow with a baseline, and outputs differences in natural language. This tool offers a graphical interface, facilitating the prevention and detection of ROP attacks. The proposed approach and tool provide practical solutions for enhancing software security.

Keywords: operating system, ROP attacks, returning-oriented programming attacks, ASLR, LBR, CFI, DEP, code randomization, hardware-assisted CFI

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Thi Phuong Ly Tran

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Being a basic and unique to human beings, cognitive activity possesses spiritualistic characteristics and is conveyed through languages. Words that represent rational cognition or processes related to rationality as follow: know, think, understand, doubt, be afraid, remember, forget, think (that), realize (that), find (that), etc. can reflect the process by which human beings have transformed cognitive activities into diversified and delicate manners through linguistic tasks. In this research article, applying the descriptive method and comparative method, we would like to utilize the application of the theoretical system of linguistic characteristics of cognitive verbs in Vietnamese language in comparison with English language. These achievements of this article will meaningfully contribute to highlight characteristics of Vietnamese language and identify the similarities and differences in the linguistic processes of Vietnamese and English people as well as supply more knowledge for social requirements such as foreign language learning, dictionary editing, language teaching in schools.

Keywords: cognitive activity, cognitive perspective, Vietnamese language, English language

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Authors: Fariborz Ahmadi, Reza Tati

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Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only do not this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.

Keywords: hardware, genetic algorithm, computer science, engineering

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Authors: Anita Puspawati

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A failure in obtaining informed consent from patient occurs because there is not effective communication skill in doctors. Therefore, the language is very important in communication between doctor and patient. This study uses descriptive analysis method, that is a method used mainly in researching the status of a group of people, an object, a condition, a system of thought or a class of events in the present. The result of this study indicates that the communicative language between doctors and patients will increase the trust of patients to their doctors and accordingşy, patients will provide the informed consent voluntarily.

Keywords: communicative, language, doctor, patient

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Japhet Asanji

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The bases of this research were to explore student’s perception of home background and the acquisition of English Language in Mbonge Municipality by examining how financial status, level of education, marital status and parenting styles of their parents influence English Language Acquisition. Using random sampling techniques, closed-ended questionnaires were administered to 60 students, and the data was analysed using descriptive statistical analysis. The results reaffirm the positive relationship between student’s perception of home background and the acquisition of English language. Contributions, limitations, and direction for further research are also discussed.

Keywords: student, home background, English language acquisition, Cameroon

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Authors: Hu Yinyao

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Learning and using a second language have become more and more common in daily life. Understanding the complexity of second language proficiency can help students develop their interpersonal relationships with their friends and professors, even enhancing intimacy. This paper examines Wenzhou-Kean University students' second language proficiency and interpersonal relationships. The purpose of the research was to explore the relationship between second language proficiency, extent of intimacy, and interpersonal relationships of the 100 Wenzhou-Kean University students. A mixed methodology was utilized in the research study. Student respondents from Wenzhou-Kean University were chosen randomly by using random sampling. The data analysis used descriptive data in terms of figures and thematical data in the table. The researcher found that Wenzhou-Kean University’s students have shown lower intermediate level of second language proficiency and that their intimacy is middle when using a second language. Especially when talking about some sensitive topics, students tend not to use a second language due to low proficiency. This research project has a strong implication on interpersonal relationships and second language proficiency. The outcome of the study would be greatly helpful to enhance the interpersonal relationship and intimacy between students and students, students and professors who use.

Keywords: Interpersonal relationship, second language proficiency, intimacy, education, univeristy students

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Authors: Ukhtie Nantika Mena, Ahmad Juntika Nurihsan, Ilfiandra

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This study aims to explore perspective on Foreign Language Classroom Anxiety (FLCA) of an international student. Descriptive narrative is used to discover written and spoken responses from the student. An online survey was employed as a secondary data to identify the level of FLCA among six UPI international students. A student with the highest score volunteered to be interviewed. Several symptoms were found; lack of concentration, excessive worry, fear, unwanted thoughts, and sweating. The results showed that difficulties to understand lecturers' correction, presentation, and fear of getting left behind are three major causes of his anxiety.

Keywords: foreign language classroom anxiety, FLCA, international students, language anxiety

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Authors: Ankita R. Bansal, Naren S. Burade

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Idea is to create a cloud based virtual lab for Deaf Students, “A language acquisition program using Visual Phonics and Cued Speech” using VMware Virtual Lab. This lab will demonstrate students the sounds of letters associated with the Language, building letter blocks, making words, etc Virtual labs are used for demos, training, for the Lingual development of children in their vernacular language. The main potential benefits are reduced labour and hardware costs, faster response times to users. Virtual Computing Labs allows any of the software as a service solutions, virtualization solutions, and terminal services solutions available today to offer as a service on demand, where a single instance of the software runs on the cloud and services multiple end users. VMWare, XEN, MS Virtual Server, Virtuoso, and Citrix are typical examples.

Keywords: visual phonics, language acquisition, vernacular language, cued speech, virtual lab

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Authors: Saleh Mohammad Alqahtani

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Foreign language Anxiety has been found to be a key issue in learning English as foreign language in the classroom. This study investigated the impact of foreign language anxiety on Saudi EFL learners' proficiency in the classroom. A total of 197 respondents had participated in the study, comprising of 96 male and 101 female, who enrolled in preparatory year, first year, second year, and fourth year of English language department at the University of Jeddah. Two instruments were used to answer the study questions. The Foreign Language Classroom Anxiety Scale (FLCAS) was used to identify the levels of foreign language (FL) anxiety for Saudi learners. Moreover, an International English Language Testing System (IELTS) test was used as an objective measure of the learners’ English language proficiency. The data were analyzed using descriptive analyses, t-test, one-way ANOVA, correlation, and regression analysis. The findings revealed that Saudi EFL learners' experience a level of anxiety in the classroom, and there is a significant differences between the course levels in their level of language anxiety. Moreover, it is also found that female students are less anxious in learning English as a foreign language than male students. The results show that foreign language anxiety and English proficiency are negatively related to each other. Furthermore, the study revealed that there were significant differences between Saudi learners in language use anxiety, while there were no significant differences in language class anxiety. The study suggested that teachers should employ a diversity of designed techniques to encourage the environment of the classroom in order to control learners’ FLA, which in turns will improve their EFL proficiency.

Keywords: foreign language anxiety, FLA, language use anxiety, language class anxiety, gender, L2 proficiency

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Authors: Khaleel Bader Bataineh

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Past studies have maintained that the Arab learners' beliefs about language learning hold vital effects on their performance. Thus, this study was carried out to investigate the language learning beliefs of Irbid National University students. It aimed at identifying the language learning beliefs according to gender. This study is a descriptive design that employed survey questionnaire of Language Learning Beliefs Inventory (BALLI). The data were elicited from 83 English major students during the class sessions. The data were analyzed using an SPSS program in which frequency analysis and t-test were performed to examine the students’ responses. Thus, the major findings of this research indicated that there is a variation in responses with regards to the subjects’ beliefs about English learning. Also, the findings show significant differences in four questionnaire items according to gender. It is hoped that the findings provide valuable insights to educators about the learners’ beliefs which assist them to develop the teaching and learning English language process in Jordan universities.

Keywords: foreign language, students’ beliefs, language learning, Arab students

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Authors: Ziyuan Wu, Yulong Jia, Xiang Zhang, Wanting Zhou, Lei Li

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The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method.

Keywords: IoT, security, SoC, bus architecture, lightweight hardware firewall, FPGA

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