Search results for: Integrated Circuits

Authors: Zhangquan Zhou, Guilin Qi

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Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes.

Keywords: ontology materialization, parallel reasoning, datalog, Boolean circuit

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Zhengming Wu

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NanoFrazor lithography systems were developed as a first true alternative or extension to standard mask-less nanolithography methods like electron beam lithography (EBL). In contrast to EBL they are based on thermal scanning probe lithography (t-SPL). Here a heatable ultra-sharp probe tip with an apex of a few nm is used for patterning and simultaneously inspecting complex nanostructures. The heat impact from the probe on a thermal responsive resist generates those high-resolution nanostructures. The patterning depth of each individual pixel can be controlled with better than 1 nm precision using an integrated in-situ metrology method. Furthermore, the inherent imaging capability of the Nanofrazor technology allows for markerless overlay, which has been achieved with sub-5 nm accuracy as well as it supports stitching layout sections together with < 10 nm error. Pattern transfer from such resist features below 10 nm resolution were demonstrated. The technology has proven its value as an enabler of new kinds of ultra-high resolution nanodevices as well as for improving the performance of existing device concepts. The application range for this new nanolithography technique is very broad spanning from ultra-high resolution 2D and 3D patterning to chemical and physical modification of matter at the nanoscale. Nanometer-precise markerless overlay and non-invasiveness to sensitive materials are among the key strengths of the technology. However, while patterning at below 10 nm resolution is achieved, significantly increasing the patterning speed at the expense of resolution is not feasible by using the heated tip alone. Towards this end, an integrated laser write head for direct laser sublimation (DLS) of the thermal resist has been introduced for significantly faster patterning of micrometer to millimeter-scale features. Remarkably, the areas patterned by the tip and the laser are seamlessly stitched together and both processes work on the very same resist material enabling a true mix-and-match process with no developing or any other processing steps in between. The presentation will include examples for (i) high-quality metal contacting of 2D materials, (ii) tuning photonic molecules, (iii) generating nanofluidic devices and (iv) generating spintronic circuits. Some of these applications have been enabled only due to the various unique capabilities of NanoFrazor lithography like the absence of damage from a charged particle beam.

Keywords: nanofabrication, grayscale lithography, 2D materials device, nano-optics, photonics, spintronic circuits

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Authors: Takoua Soltani, Imen Soltani, Taoufik Aguili

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The communications' and radar systems' demands give rise to new developments in the domain of active integrated antennas (AIA) and arrays. The main advantages of AIA arrays are the simplicity of fabrication, low cost of manufacturing, and the combination between free space power and the scanner without a phase shifter. The integrated active antenna modeling is the coupling between the electromagnetic model and the transport model that will be affected in the high frequencies. Global modeling of active circuits is important for simulating EM coupling, interaction between active devices and the EM waves, and the effects of EM radiation on active and passive components. The current review focuses on the modeling of the active element which is a MESFET transistor immersed in a rectangular waveguide. The proposed EM analysis is based on the Method of Moments combined with the Generalised Equivalent Circuit method (MOM-GEC). The Method of Moments which is the most common and powerful software as numerical techniques have been used in resolving the electromagnetic problems. In the class of numerical techniques, MOM is the dominant technique in solving of Maxwell and Transport’s integral equations for an active integrated antenna. In this situation, the equivalent circuit is introduced to the development of an integral method formulation based on the transposition of field problems in a Generalised equivalent circuit that is simpler to treat. The method of Generalised Equivalent Circuit (MGEC) was suggested in order to represent integral equations circuits that describe the unknown electromagnetic boundary conditions. The equivalent circuit presents a true electric image of the studied structures for describing the discontinuity and its environment. The aim of our developed method is to investigate the antenna parameters such as the input impedance and the current density distribution and the electric field distribution. In this work, we propose a global EM modeling of the MESFET AsGa transistor using an integral method. We will begin by describing the modeling structure that allows defining an equivalent EM scheme translating the electromagnetic equations considered. Secondly, the projection of these equations on common-type test functions leads to a linear matrix equation where the unknown variable represents the amplitudes of the current density. Solving this equation resulted in providing the input impedance, the distribution of the current density and the electric field distribution. From electromagnetic calculations, we were able to present the convergence of input impedance for different test function number as a function of the guide mode numbers. This paper presents a pilot study to find the answer to map out the variation of the existing current evaluated by the MOM-GEC. The essential improvement of our method is reducing computing time and memory requirements in order to provide a sufficient global model of the MESFET transistor.

Keywords: active integrated antenna, current density, input impedance, MESFET transistor, MOM-GEC method

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Authors: Geetal Mahajan, R. V. Adivarekar

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In this research, an attempt has been made to develop integrated finish on textile fabrics. The demand for mosquito repellent, flame retardant, and water repellent finished fabric has increased. Integrated finishing was done using commercially available products. These finishing agents were first assessed individually for their functional properties and then used in combination with other agents. Dip-air dry and pad-dry-cure (PDC) were two different methods used for fabric finishing. The finished fabric was assessed using spray test, limiting oxygen index and mosquito repellence test. Integrated finished fabric is in great demand by the customers as it increases the aesthetic as well as the functional properties of the fabric with added benefit of water and energy conservation.

Keywords: flame retardant, integrated finishing, mosquito repellent, textiles, water repellent

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Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

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The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

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Authors: Taekyoon Park, Seokgoo Lee, Sungho Kim, Ung Lee, Jong Min Lee, Chonghun Han

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CO2 capture and storage/sequestration (CCS) is a key technology for addressing the global warming issue. This paper proposes an integrated model for the whole chain of CCS, from a power plant to a reservoir. The integrated model is further utilized to determine optimal operating conditions and study responses to various changes in input variables.

Keywords: CCS, caron dioxide, carbon capture and storage, simulation, optimization

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Authors: Peerawat Chailom, Pimgarn Suwan-Natada

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The objective of this study is to examine the effects of e-commerce integrated for export marketing strategy on export advantage and firm performance. This study indicates that e-commerce infrastructure, organizational learning for e-commerce, and internet dissemination were antecedent of e-commerce integrated for export marketing strategy. In additional, export expertise is moderating variable of the research. In this study, 151 export businesses in Thailand are the sample of study. The results of study indicate that e-commerce integrated for export marketing strategy has significant positive influences on export advantage and export performance. Moreover, e-commerce infrastructure, organizational learning for e-commerce, and internet dissemination are have positive effects on e-commerce integrated for export marketing strategy. For moderating effect, export expertise significant influences on the relationships between e-commerce integrated for export marketing strategy and export advantage, and significant influences on the relationships between e-commerce integrated for export marketing strategy and export performance. Theoretical and practical implications are presented. Conclusion and suggestions for future research are also discussed.

Keywords: e-commerce integrated for export marketing, e-commerce infrastructure, organizational learning for e-commerce, export performance

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Authors: Romain Lestage, Marc Bourreau

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In this paper we analyze the interplay between access to the last-mile network and net neutrality in the market for Internet access. We consider two Internet Service Providers (ISPs), which act as platforms between Internet users and Content Providers (CPs). One of the ISPs is vertically integrated and provides access to its last-mile network to the other (non-integrated) ISP. We show that a lower access price increases the integrated ISP's incentives to charge CPs positive termination fees (i.e., to deviate from net neutrality), and decreases the non-integrated ISP's incentives to charge positive termination fees.

Keywords: net neutrality, access regulation, internet access, two-sided markets

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Authors: Jalal M. Abdallah

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This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer.

Keywords: frequency response analysis (FRA), measurements, transfer function, transformer

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Authors: Nuttha Kirdsinsap, Watchaneeporn Setthasakko

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This paper aims to gain opinions and perspectives of Certified Public Accountants (CPA) in Thailand regarding the driven force of Integrated Reporting. It employs in-depth interviews with CPA from different big 4 audits firms in Thailand, including PWC, Ernst and Young, Deloitte, and KPMG. It is found that the driven force of Integrated Reporting made CPA in Thailand awaken to the big change that is coming in the future, and it is said to be another big learning and integrating period between certified public accountants and other professionals (for example, engineers, environmentalists and lawyers), which, certified public accountants in Thailand will have to push themselves so hard to catch up.

Keywords: integrated reporting, learning, knowledge, certified public accountants, Thailand

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Authors: Christian Meinecke, Bernd Scholz-Reiter

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The integrated problem of production and distribution scheduling is relevant in many industrial applications. Thus, many heuristics to solve this integrated problem have been developed in the last decade. Most of these heuristics use a sequential working principal or a single decomposition and integration approach to separate and solve sub-problems. A heuristic using a multi-step decomposition and integration approach is presented in this paper and evaluated in a case study. The result show significant improved results compared with sequential scheduling heuristics.

Keywords: production and outbound distribution, integrated planning, heuristic, decomposition, integration

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Authors: Arabi Abderrazak, Bourouba Nacerdine, Ayad Mouloud, Belaout Abdeslam

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In this paper, a new test technique of analog circuits using time mode simulation is proposed for the single catastrophic faults detection in analog circuits. This test process is performed to overcome the problem of catastrophic faults being escaped in a DC mode test applied to the inverter amplifier in previous research works. The circuit under test is a second-order low pass filter constructed around this type of amplifier but performing a function that differs from that of the previous test. The test approach performed in this work is based on two key- elements where the first one concerns the unique square pulse signal selected as an input vector test signal to stimulate the fault effect at the circuit output response. The second element is the filter response conversion to a square pulses sequence obtained from an analog comparator. This signal conversion is achieved through a fixed reference threshold voltage of this comparison circuit. The measurement of the three first response signal pulses durations is regarded as fault effect detection parameter on one hand, and as a fault signature helping to hence fully establish an analog circuit fault diagnosis on another hand. The results obtained so far are very promising since the approach has lifted up the fault coverage ratio in both modes to over 90% and has revealed the harmful side of faults that has been masked in a DC mode test.

Keywords: analog circuits, analog faults diagnosis, catastrophic faults, fault detection

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Authors: Azizi Cherifa, O. Benzaoui

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The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

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Authors: Eduwin Eko Franjaya, Andi Gunawan, Wahju Qamara Mugnisjah

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Sustainable agriculture in the form of integrated farming with its LEISA (Low External Input Sustainable Agriculture) concept has brought a positive impact on agriculture development and ambient amelioration. But, most of the small farmers in Indonesia did not know how to put the concept of it and how to combine agricultural commodities on the site effectively and efficiently. This research has an aim to promote integrated farming (agrofisheries, etc) to the farmers by designing the agricultural landscape to become integrated farming landscape as medium of education for the farmers. The method used in this research is closely related with the rule of design in the landscape architecture science. The first step is inventarization for the existing condition on the research site. The second step is analysis. Then, the third step is concept-making that consists of base concept, design concept, and developing concept. The base concept used in this research is sustainable agriculture with LEISA. The concept design is related with activity base on site. The developing concept consists of space concept, circulation, vegetation and commodity, production system, etc. The fourth step as the final step is planning and design. This step produces site plan of integrated farming based on LEISA. The result of this research is site plan of integrated farming with its explanation, including the energy flow of integrated farming system on site and the production calendar of integrated farming commodities for education and agri-tourism opportunity. This research become the right way to promote the integrated farming and also as a medium for the farmers to learn and to develop it.

Keywords: integrated farming, LEISA, planning and design, site plan

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Authors: Nahla Elazab, Mohamed Aboudina, Ghada Ibrahim, Hossam Fahmy, Ahmed Khalil

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This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented.

Keywords: BFSK, demodulator, high frequency memristor applications, memristor based analog circuits, nonlinear dopant drift model, QAM

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Authors: Sally A. Brown

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Over the last 30 years, researchers have developed models or frameworks to provide a more structured understanding of the reading comprehension process. Cognitive information processing models and social cognitive theories both provide frameworks to inform reading comprehension instruction. The purpose of this paper is to (a) provide an overview of the historical development of reading comprehension theory, (b) review the literature framed by cognitive information processing, social cognitive, and integrated reading comprehension theories, and (c) demonstrate how these frameworks inform instruction. As integrated models of reading can guide the interpretation of various factors related to student learning, an integrated framework designed by the researcher will be presented. Results indicated that features of cognitive processing and social cognitivism theory—represented in the integrated framework—highlight the importance of the role of the teacher. This model can aid teachers in not only improving reading comprehension instruction but in identifying areas of challenge for students.

Keywords: explicit instruction, integrated models of reading comprehension, reading comprehension, teacher’s role

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Authors: Suleiman Babani, Jazuli Sanusi Kazaure

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In this paper, two coupled-line couplers are designed and simulated using stripline technology. The coupled-line couplers (A and B) are designed with different values of coupling coefficient 6dB and 10dB respectively. Both of circuits have a coupled output port, a through output port and an isolated output port. Moreover, both circuits are tuned to function around 2.45 GHz. The design results are presented by simulation results obtained using ADS 2012.08 (Advanced Design System) software.

Keywords: ADS, coupled-line coupler, directional coupler, stripline

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Diogo Ferreira Lima Filho, José Roberto Amazonas

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Nanotechnology opens the door to new paradigms that introduces a variety of novel tools enabling a plethora of potential applications in the biomedical, industrial, environmental, and military fields. This work proposes an integrated node model by applying the same concepts of TCNet to networks of nanodevices where the nodes are cooperatively interconnected with a low-complexity Mealy Machine (MM) topology integrating in the same electronic system the modules necessary for independent operation in wireless sensor networks (WSNs), consisting of Rectennas (RF to DC power converters), Code Generators based on Finite State Machine (FSM) & Trellis Decoder and On-chip Transmit/Receive with autonomy in terms of energy sources applying the Energy Harvesting technique. This approach considers the use of a Graphene Composite Substrate (GCS) for the integrated electronic circuits meeting the following characteristics: mechanical flexibility, miniaturization, and optical transparency, besides being ecological. In addition, graphene consists of a layer of carbon atoms with the configuration of a honeycomb crystal lattice, which has attracted the attention of the scientific community due to its unique Electrical Characteristics.

Keywords: composite substrate, energy harvesting, finite state machine, graphene, nanotechnology, rectennas, wireless sensor networks

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Authors: Kwangin Kim, Taewon Yoo, Haksoo Han

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Polyimide is a superior polymer in the electronics industry, and we conducted a study to synthesize poly(amide-imide) at low temperatures. Poly(amide-imide) was synthesized at low-temperature curing to offer a thermal stable membrane with low residual stress and good processability. As a result, the low crack polymer with good processability could be used to various applications such as semiconductors, integrated circuits, coating materials, membranes, and display. The synthesis of poly(amide-imide) at low temperatures was confirmed by Fourier transform infrared spectroscopy (FT-IR). Thermal stabilities of the polymer was confirmed by thermogravimetric analysis (TGA) and differential scanning calorimetry (DSC).

Keywords: poly(amide-imide), residual stress, thermal stability

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Authors: Ching-Feng Chen, Ching-Chih Tsai

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With the size of the transistor gradually approaching the physical limit, it challenges the persistence of Moore’s Law due to the development of the high numerical aperture (high-NA) lithography equipment and other issues such as short channel effects. In the context of the ever-increasing technical requirements of portable devices and high-performance computing, relying on the law continuation to enhance the chip density will no longer support the prospects of the electronics industry. Weighing the chip’s power consumption-performance-area-cost-cycle time to market (PPACC) is an updated benchmark to drive the evolution of the advanced wafer nanometer (nm). The advent of two and half- and three-dimensional (2.5 and 3D)- Very-Large-Scale Integration (VLSI) packaging based on Through Silicon Via (TSV) technology has updated the traditional die assembly methods and provided the solution. This overview investigates the up-to-date and cutting-edge packaging technologies for 2.5D and 3D integrated circuits (ICs) based on the updated transistor structure and technology nodes. The author concludes that multi-chip solutions for 2.5D and 3D IC packagings are feasible to prolong Moore’s Law.

Keywords: moore’s law, high numerical aperture, power consumption-performance-area-cost-cycle time to market, 2.5 and 3D- very-large-scale integration, packaging, through silicon via

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: V. Swarnalatha, A. V. Narasimha Rao, P. Pal

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The present research reports the investigation of fast etching of silicon for the fabrication of microelectromechanical systems (MEMS) structures using silicon wet bulk micromachining. Low concentration tetramethyl-ammonium hydroxide (TMAH) and hydroxylamine (NH₂OH) are used as main etchant and additive, respectively. The concentration of NH₂OH is varied to optimize the composition to achieve best etching characteristics such as high etch rate, significantly high undercutting at convex corner for the fast release of the microstructures from the substrate, and improved etched surface morphology. These etching characteristics are studied on Si{100} and Si{110} wafers as they are most widely used in the fabrication of MEMS structures as wells diode, transistors and integrated circuits.

Keywords: KOH, MEMS, micromachining, silicon, TMAH, wet anisotropic etching

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Authors: Tijing Cai, Qimeng Xu, Daijin Zhou

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This paper puts forward a short-baseline dual-antenna BDS/MEMS-IMU integrated navigation, constructs the carrier phase double difference model of BDS (BeiDou Navigation Satellite System), and presents a 2-position initial orientation method on BDS. The Extended Kalman-filter has been introduced for the integrated navigation system. The differences between MEMS-IMU and BDS position, velocity and carrier phase indications are used as measurements. To show the performance of the short-baseline dual-antenna BDS/MEMS-IMU integrated navigation system, the experiment results show that the position error is less than 1m, the pitch angle error and roll angle error are less than 0.1°, and the heading angle error is about 1°.

Keywords: MEMS-IMU (Micro-Electro-Mechanical System Inertial Measurement Unit), BDS (BeiDou Navigation Satellite System), dual-antenna, integrated navigation

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Authors: Saurabh Chaudhury, Sanjeet Kumar Sinha

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The MOSFET has been the main building block in high performance and low power VLSI chips for the last several decades. Device scaling is fundamental to technological advancements, which allows more devices to be integrated on a single die providing greater functionality per chip. Ultimately, the goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consumes less power. Scaling continued following Moore's law initially and now we see an exponential growth in today's nano scaled chip. However, device scaling to deep nano meter regime leads to exponential increase in leakage currents and excessive heat generation. Moreover, fabrication process variability causing a limitation to further scaling. Researchers believe that with a mix of chemistry, physics, and engineering, nano electronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nano tube (CNT) and nano wires (NW) based FETs have been analyzed and characterized in laboratory and also been demonstrated as prototypes. This work presents an extensive simulation based study and analysis of CNTFET and NW-FET devices and comparison of the results with conventional MOSFET. From this study, we can conclude that these devices have got some excellent properties and favorable characteristics which will definitely lead the future semiconductor devices in post silicon era.

Keywords: carbon nanotube, nanowire FET, low power, nanoscaled devices, VLSI

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Authors: Siwanit Autthawuttikul, Prakob Koraneekid, Sayamon Insa-ard

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The purposes of this research were to development creatively integrated teaching skills using Information and Communication Technology (ICT) for professional teacher in schools under the education area of the basic education commission, ministry of education both schools under the office of primary education and those under The office of secondary education in eight western region provinces of Thailand. This is useful in defining a vision for the school strategy and restructuring schools in addition, teachers will have developed skills in teaching creative integrated ICT. The research methodology comprises quantitative and qualitative data collection. The Baseline Survey, focus group for discussions and then the model was developed creatively integrated teaching skills using ICT. The findings showed that 7 elements were important: (1) Academy Transformation (2) Information Technology Infrastructure (3) Personal Development (4) Supervision, Monitoring and Evaluation (5) Motivating and Rewarding (6) Important factor affecting the success of teaching integrated with ICT were knowledge, skills, attitudes and (7) The role of the individual concerned. The comparison creatively integrated teaching skills before and after participating in the overall shows that the average creatively integrated teaching skills using ICT after attending the event is 3.27, and standard deviation was 0.56, higher than before which is 2.60 and the standard deviation was 0.56. There are significant differences significant statistically level of .05. The final average score of the evaluation plan design creatively integrated teaching skills using ICT teachers' average score was 26.94 at the high levels.

Keywords: integrated curriculum, information and communications technology, teachers in the western region, schools

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Authors: Felipe M. de Freitas, Ícaro V. Soares, Lucas L. L. Fortes, Sandro T. M. Gonçalves, Úrsula D. C. Resende

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There is a dispersed energy in Radio Frequencies (RF) that can be reused to power electronics circuits such as: sensors, actuators, identification devices, among other systems, without wire connections or a battery supply requirement. In this context, there are different types of energy harvesting systems, including rectennas, coil systems, graphene and new materials. A secondary step of an energy harvesting system is the rectification of the collected signal which may be carried out, for example, by the combination of one or more Schottky diodes connected in series or shunt. In the case of a rectenna-based system, for instance, the diode used must be able to receive low power signals at ultra-high frequencies. Therefore, it is required low values of series resistance, junction capacitance and potential barrier voltage. Due to this low-power condition, voltage multiplier configurations are used such as voltage doublers or modified bridge converters. Lowpass filter (LPF) at the input, DC output filter, and a resistive load are also commonly used in the rectifier design. The electronic circuits projects are commonly analyzed through simulation in SPICE (Simulation Program with Integrated Circuit Emphasis) environment. Despite the remarkable potential of SPICE-based simulators for complex circuit modeling and analysis of quasi-static electromagnetic fields interaction, i.e., at low frequency, these simulators are limited and they cannot model properly applications of microwave hybrid circuits in which there are both, lumped elements as well as distributed elements. This work proposes, therefore, the electromagnetic modelling of electronic components in order to create models that satisfy the needs for simulations of circuits in ultra-high frequencies, with application in rectifiers coupled to antennas, as in energy harvesting systems, that is, in rectennas. For this purpose, the numerical method FDTD (Finite-Difference Time-Domain) is applied and SPICE computational tools are used for comparison. In the present work, initially the Ampere-Maxwell equation is applied to the equations of current density and electric field within the FDTD method and its circuital relation with the voltage drop in the modeled component for the case of lumped parameter using the FDTD (Lumped-Element Finite-Difference Time-Domain) proposed in for the passive components and the one proposed in for the diode. Next, a rectifier is built with the essential requirements for operating rectenna energy harvesting systems and the FDTD results are compared with experimental measurements.

Keywords: energy harvesting system, LE-FDTD, rectenna, rectifier, wireless power systems

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Authors: Nemanja Kajtez, Yue Zhan, Basel Halak

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The significant rise in the cost of manufacturing of nanoscale integrated circuits (IC) has led the majority of IC design companies to outsource the fabrication of their products to other companies, often located in different countries. This multinational nature of the hardware supply chain has led to a host of security threats, including IP piracy, IC overproduction, and Trojan insertion. To combat that, researchers have proposed logic locking techniques to protect the intellectual properties of the design and increase the difficulty of malicious modification of its functionality. However, the adoption of logic locking approaches is rather slow due to the lack of the integration with IC production process and the lack of efficacy of existing algorithms. This work automates the logic locking process by developing software using Python that performs the locking on a gate-level netlist and can be integrated with the existing digital synthesis tools. Analysis of the latest logic locking algorithms has demonstrated that the SFLL-HD algorithm is one of the most secure and versatile in trading-off levels of protection against different types of attacks and was thus selected for implementation. The presented tool can also be expanded to incorporate the latest locking mechanisms to keep up with the fast-paced development in this field. The paper also presents a case study to demonstrate the functionality of the tool and how it could be used to explore the design space and compare different locking solutions. The source code of this tool is available freely from (https://www.researchgate.net/publication/353195333_Source_Code_for_The_Lockit_Tool).

Keywords: design automation, hardware security, IP piracy, logic locking

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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